History

Merge branch 'pci/dt-bindings'

- Add Qualcomm QCS615 to SM8150 DT binding (Ziyue Zhang) - Add Qualcomm QCS8300 to SA8775p DT binding (Ziyue Zhang) - Add '6' (64 GT/s, aka Gen6) as a legal value for the DT endpoint 'max-link-speed' property (Hans Zhang) - Drop TBU and ref clocks from Qualcomm SM8150 and SC8180x DT bindings (Konrad Dybcio) - Convert amazon,al-alpine-v[23]-pcie, apm,xgene-pcie, axis,artpec6-pcie, marvell,armada-3700-pcie, st,spear1340-pcie to DT schema format (Rob Herring) - Document 'link_down' reset in Qualcomm SA8775P DT binding (Ziyue Zhang) * pci/dt-bindings: dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset dt-bindings: PCI: Remove 83xx-512x-pci.txt dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema dt-bindings: PCI: Convert apm,xgene-pcie to DT schema dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema dt-bindings: PCI: Convert st,spear1340-pcie to DT schema dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated clocks from PCIe hosts dt-bindings: PCI: qcom,pcie-sc8180x: Drop unrelated clocks from PCIe hosts dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6 dt-bindings: PCI: qcom,pcie-sa8775p: Document QCS8300 dt-bindings: PCI: qcom,pcie-sm8150: Document QCS615

Bjorn Helgaas committed 1 year ago

Commit 11fdf082 parents 29ccb7b fbcbd6617 files · +450 −288Browse files

Unified · Split

17 files
  1. Documentation/devicetree/bindings/pci/83xx-512x-pci.txt +0 −39
  2. Documentation/devicetree/bindings/pci/aardvark-pci.txt +0 −59
  3. Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml +71 −0
  4. Documentation/devicetree/bindings/pci/apm,xgene-pcie.yaml +84 −0
  5. Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +0 −50
  6. Documentation/devicetree/bindings/pci/axis,artpec6-pcie.yaml +118 −0
  7. Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml +99 −0
  8. Documentation/devicetree/bindings/pci/pci-ep.yaml +1 −1
  9. Documentation/devicetree/bindings/pci/pcie-al.txt +0 −46
  10. Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +14 −4
  11. Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml +4 −10
  12. Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml +10 −11
  13. Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +1 −1
  14. Documentation/devicetree/bindings/pci/spear13xx-pcie.txt +0 −14
  15. Documentation/devicetree/bindings/pci/st,spear1340-pcie.yaml +45 −0
  16. Documentation/devicetree/bindings/pci/xgene-pci.txt +0 −50
  17. MAINTAINERS +3 −3
Documentation/devicetree/bindings/pci/83xx-512x-pci.txt+0−39
@@ -1,39 +0,0 @@
1* Freescale 83xx and 512x PCI bridges
2
3Freescale 83xx and 512x SOCs include the same PCI bridge core.
4
583xx/512x specific notes:
6- reg: should contain two address length tuples
7 The first is for the internal PCI bridge registers
8 The second is for the PCI config space access registers
9
10Example (MPC8313ERDB)
11 pci0: pci@e0008500 {
12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
13 interrupt-map = <
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
19
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
24 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
25 interrupt-parent = <&ipic>;
26 interrupts = <66 0x8>;
27 bus-range = <0x0 0x0>;
28 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
29 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
30 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
31 clock-frequency = <66666666>;
32 #interrupt-cells = <1>;
33 #size-cells = <2>;
34 #address-cells = <3>;
35 reg = <0xe0008500 0x100 /* internal registers */
36 0xe0008300 0x8>; /* config space access registers */
37 compatible = "fsl,mpc8349-pci";
38 device_type = "pci";
39 };
Documentation/devicetree/bindings/pci/aardvark-pci.txt+0−59
@@ -1,59 +0,0 @@
1Aardvark PCIe controller
2
3This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
4
5The Device Tree node describing an Aardvark PCIe controller must
6contain the following properties:
7
8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
17 handle MSI interrupts
18 - msi-parent: pointer to the MSI controller to be used
19 - interrupt-map-mask and interrupt-map: standard PCI properties to
20 define the mapping of the PCIe interface to interrupt numbers.
21 - bus-range: PCI bus numbers covered
22 - phys: the PCIe PHY handle
23 - max-link-speed: see pci.txt
24 - reset-gpios: see pci.txt
25
26In addition, the Device Tree describing an Aardvark PCIe controller
27must include a sub-node that describes the legacy interrupt controller
28built into the PCIe controller. This sub-node must have the following
29properties:
30
31 - interrupt-controller
32 - #interrupt-cells: set to <1>
33
34Example:
35
36 pcie0: pcie@d0070000 {
37 compatible = "marvell,armada-3700-pcie";
38 device_type = "pci";
39 reg = <0 0xd0070000 0 0x20000>;
40 #address-cells = <3>;
41 #size-cells = <2>;
42 bus-range = <0x00 0xff>;
43 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
44 #interrupt-cells = <1>;
45 msi-controller;
46 msi-parent = <&pcie0>;
47 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
48 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
49 interrupt-map-mask = <0 0 0 7>;
50 interrupt-map = <0 0 0 1 &pcie_intc 0>,
51 <0 0 0 2 &pcie_intc 1>,
52 <0 0 0 3 &pcie_intc 2>,
53 <0 0 0 4 &pcie_intc 3>;
54 phys = <&comphy1 0>;
55 pcie_intc: interrupt-controller {
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 };
59 };
Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml+71−0
@@ -0,0 +1,71 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Amazon Annapurna Labs Alpine v3 PCIe Host Bridge
8
9maintainers:
10 - Jonathan Chocron <jonnyc@amazon.com>
11
12description:
13 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys
14 DesignWare PCI controller.
15
16allOf:
17 - $ref: snps,dw-pcie.yaml#
18
19properties:
20 compatible:
21 enum:
22 - amazon,al-alpine-v2-pcie
23 - amazon,al-alpine-v3-pcie
24
25 reg:
26 items:
27 - description: PCIe ECAM space
28 - description: AL proprietary registers
29 - description: Designware PCIe registers
30
31 reg-names:
32 items:
33 - const: config
34 - const: controller
35 - const: dbi
36
37 interrupts:
38 maxItems: 1
39
40unevaluatedProperties: false
41
42required:
43 - compatible
44 - reg
45 - reg-names
46
47examples:
48 - |
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50
51 bus {
52 #address-cells = <2>;
53 #size-cells = <2>;
54
55 pcie@fb600000 {
56 compatible = "amazon,al-alpine-v3-pcie";
57 reg = <0x0 0xfb600000 0x0 0x00100000
58 0x0 0xfd800000 0x0 0x00010000
59 0x0 0xfd810000 0x0 0x00001000>;
60 reg-names = "config", "controller", "dbi";
61 bus-range = <0 255>;
62 device_type = "pci";
63 #address-cells = <3>;
64 #size-cells = <2>;
65 #interrupt-cells = <1>;
66 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
67 interrupt-map-mask = <0x00 0 0 7>;
68 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
69 ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
70 };
71 };
Documentation/devicetree/bindings/pci/apm,xgene-pcie.yaml+84−0
@@ -0,0 +1,84 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/apm,xgene-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: AppliedMicro X-Gene PCIe interface
8
9maintainers:
10 - Toan Le <toan@os.amperecomputing.com>
11
12allOf:
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14
15properties:
16 compatible:
17 oneOf:
18 - items:
19 - const: apm,xgene-storm-pcie
20 - const: apm,xgene-pcie
21 - items:
22 - const: apm,xgene-pcie
23
24 reg:
25 items:
26 - description: Controller configuration registers
27 - description: PCI configuration space registers
28
29 reg-names:
30 items:
31 - const: csr
32 - const: cfg
33
34 clocks:
35 maxItems: 1
36
37 clock-names:
38 items:
39 - const: pcie
40
41 dma-coherent: true
42
43 msi-parent:
44 maxItems: 1
45
46required:
47 - compatible
48 - reg
49 - reg-names
50 - '#interrupt-cells'
51 - interrupt-map-mask
52 - interrupt-map
53 - clocks
54
55unevaluatedProperties: false
56
57examples:
58 - |
59 bus {
60 #address-cells = <2>;
61 #size-cells = <2>;
62
63 pcie@1f2b0000 {
64 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
65 device_type = "pci";
66 #interrupt-cells = <1>;
67 #size-cells = <2>;
68 #address-cells = <3>;
69 reg = <0x00 0x1f2b0000 0x0 0x00010000>, /* Controller registers */
70 <0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
71 reg-names = "csr", "cfg";
72 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000>, /* io */
73 <0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
74 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000>,
75 <0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
76 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
77 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1>,
78 <0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1>,
79 <0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1>,
80 <0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
81 dma-coherent;
82 clocks = <&pcie0clk 0>;
83 };
84 };
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt+0−50
@@ -1,50 +0,0 @@
1* Axis ARTPEC-6 PCIe interface
2
3This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4and thus inherits all the common properties defined in snps,dw-pcie.yaml.
5
6Required properties:
7- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11- reg: base addresses and lengths of the PCIe controller (DBI),
12 the PHY controller, and configuration address space.
13- reg-names: Must include the following entries:
14 - "dbi"
15 - "phy"
16 - "config"
17- interrupts: A list of interrupt outputs of the controller. Must contain an
18 entry for each entry in the interrupt-names property.
19- interrupt-names: Must include the following entries:
20 - "msi": The interrupt that is asserted when an MSI is received
21- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
22 used to enable and control the Synopsys IP.
23
24Example:
25
26 pcie@f8050000 {
27 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
28 reg = <0xf8050000 0x2000
29 0xf8040000 0x1000
30 0xc0000000 0x2000>;
31 reg-names = "dbi", "phy", "config";
32 #address-cells = <3>;
33 #size-cells = <2>;
34 device_type = "pci";
35 /* downstream I/O */
36 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
37 /* non-prefetchable memory */
38 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
39 num-lanes = <2>;
40 bus-range = <0x00 0xff>;
41 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
42 interrupt-names = "msi";
43 #interrupt-cells = <1>;
44 interrupt-map-mask = <0 0 0 0x7>;
45 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
46 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
47 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
48 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
49 axis,syscon-pcie = <&syscon>;
50 };
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.yaml+118−0
@@ -0,0 +1,118 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2025 Axis AB
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Axis ARTPEC-6 PCIe host controller
9
10maintainers:
11 - Jesper Nilsson <jesper.nilsson@axis.com>
12
13description:
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
15
16select:
17 properties:
18 compatible:
19 contains:
20 enum:
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
24 - axis,artpec7-pcie-ep
25 required:
26 - compatible
27
28properties:
29 compatible:
30 items:
31 - enum:
32 - axis,artpec6-pcie
33 - axis,artpec6-pcie-ep
34 - axis,artpec7-pcie
35 - axis,artpec7-pcie-ep
36 - const: snps,dw-pcie
37
38 reg:
39 minItems: 3
40 maxItems: 4
41
42 reg-names:
43 minItems: 3
44 maxItems: 4
45
46 interrupts:
47 maxItems: 1
48
49 interrupt-names:
50 items:
51 - const: msi
52
53 axis,syscon-pcie:
54 $ref: /schemas/types.yaml#/definitions/phandle
55 description:
56 System controller phandle used to enable and control the Synopsys IP.
57
58required:
59 - compatible
60 - reg
61 - reg-names
62 - interrupts
63 - interrupt-names
64 - axis,syscon-pcie
65
66oneOf:
67 - $ref: snps,dw-pcie.yaml#
68 properties:
69 reg:
70 maxItems: 3
71
72 reg-names:
73 items:
74 - const: dbi
75 - const: phy
76 - const: config
77
78 - $ref: snps,dw-pcie-ep.yaml#
79 properties:
80 reg:
81 minItems: 4
82
83 reg-names:
84 items:
85 - const: dbi
86 - const: dbi2
87 - const: phy
88 - const: addr_space
89
90unevaluatedProperties: false
91
92examples:
93 - |
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
95
96 pcie@f8050000 {
97 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
98 device_type = "pci";
99 reg = <0xf8050000 0x2000
100 0xf8040000 0x1000
101 0xc0000000 0x2000>;
102 reg-names = "dbi", "phy", "config";
103 #address-cells = <3>;
104 #size-cells = <2>;
105 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>,
106 <0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
107 num-lanes = <2>;
108 bus-range = <0x00 0xff>;
109 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-names = "msi";
111 #interrupt-cells = <1>;
112 interrupt-map-mask = <0 0 0 0x7>;
113 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
114 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
115 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
116 <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
117 axis,syscon-pcie = <&syscon>;
118 };
Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml+99−0
@@ -0,0 +1,99 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/marvell,armada-3700-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell Armada 3700 (Aardvark) PCIe Controller
8
9maintainers:
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
11 - Pali Rohár <pali@kernel.org>
12
13allOf:
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
15
16properties:
17 compatible:
18 const: marvell,armada-3700-pcie
19
20 reg:
21 maxItems: 1
22
23 clocks:
24 maxItems: 1
25
26 interrupts:
27 maxItems: 1
28
29 msi-controller: true
30
31 msi-parent:
32 maxItems: 1
33
34 phys:
35 maxItems: 1
36
37 reset-gpios:
38 description: PCIe reset GPIO signals.
39
40 interrupt-controller:
41 type: object
42 additionalProperties: false
43
44 properties:
45 interrupt-controller: true
46
47 '#interrupt-cells':
48 const: 1
49
50 required:
51 - interrupt-controller
52 - '#interrupt-cells'
53
54required:
55 - compatible
56 - reg
57 - interrupts
58 - '#interrupt-cells'
59
60unevaluatedProperties: false
61
62examples:
63 - |
64 #include <dt-bindings/interrupt-controller/arm-gic.h>
65 #include <dt-bindings/gpio/gpio.h>
66
67 bus {
68 #address-cells = <2>;
69 #size-cells = <2>;
70
71 pcie@d0070000 {
72 compatible = "marvell,armada-3700-pcie";
73 device_type = "pci";
74 reg = <0 0xd0070000 0 0x20000>;
75 #address-cells = <3>;
76 #size-cells = <2>;
77 bus-range = <0x00 0xff>;
78 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
79 msi-controller;
80 msi-parent = <&pcie0>;
81 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000>,
82 <0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>;
83
84 #interrupt-cells = <1>;
85 interrupt-map-mask = <0 0 0 7>;
86 interrupt-map = <0 0 0 1 &pcie_intc 0>,
87 <0 0 0 2 &pcie_intc 1>,
88 <0 0 0 3 &pcie_intc 2>,
89 <0 0 0 4 &pcie_intc 3>;
90 phys = <&comphy1 0>;
91 max-link-speed = <2>;
92 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
93
94 pcie_intc: interrupt-controller {
95 interrupt-controller;
96 #interrupt-cells = <1>;
97 };
98 };
99 };
Documentation/devicetree/bindings/pci/pci-ep.yaml+1−1
@@ -51,7 +51,7 @@ properties: · 50 unmodified lines
51 51
52 max-link-speed:52 max-link-speed:
53 $ref: /schemas/types.yaml#/definitions/uint3253 $ref: /schemas/types.yaml#/definitions/uint32
54 enum: [ 1, 2, 3, 4 ]54 enum: [ 1, 2, 3, 4, 5, 6 ]
55 55
56 msi-map:56 msi-map:
57 description: |57 description: |
Documentation/devicetree/bindings/pci/pcie-al.txt+0−46
@@ -1,46 +0,0 @@
1* Amazon Annapurna Labs PCIe host bridge
2
3Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
4PCI core. It inherits common properties defined in
5Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
6
7Properties of the host controller node that differ from it are:
8
9- compatible:
10 Usage: required
11 Value type: <stringlist>
12 Definition: Value should contain
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
15
16- reg:
17 Usage: required
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
20
21- reg-names:
22 Usage: required
23 Value type: <stringlist>
24 Definition: Must include the following entries
25 - "config" PCIe ECAM space
26 - "controller" AL proprietary registers
27 - "dbi" Designware PCIe registers
28
29Example:
30
31 pcie-external0: pcie@fb600000 {
32 compatible = "amazon,al-alpine-v3-pcie";
33 reg = <0x0 0xfb600000 0x0 0x00100000
34 0x0 0xfd800000 0x0 0x00010000
35 0x0 0xfd810000 0x0 0x00001000>;
36 reg-names = "config", "controller", "dbi";
37 bus-range = <0 255>;
38 device_type = "pci";
39 #address-cells = <3>;
40 #size-cells = <2>;
41 #interrupt-cells = <1>;
42 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
43 interrupt-map-mask = <0x00 0 0 7>;
44 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
45 ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
46 };
Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml+14−4
@@ -16,7 +16,12 @@ description: · 15 unmodified lines
16 16
17properties:17properties:
18 compatible:18 compatible:
19 const: qcom,pcie-sa8775p19 oneOf:
20 - const: qcom,pcie-sa8775p
21 - items:
22 - enum:
23 - qcom,pcie-qcs8300
24 - const: qcom,pcie-sa8775p
20 25
21 reg:26 reg:
22 minItems: 627 minItems: 6
@@ -61,11 +66,14 @@ properties: · 38 unmodified lines
61 - const: global66 - const: global
62 67
63 resets:68 resets:
64 maxItems: 169 items:
70 - description: PCIe controller reset
71 - description: PCIe link down reset
65 72
66 reset-names:73 reset-names:
67 items:74 items:
68 - const: pci75 - const: pci
76 - const: link_down
69 77
70required:78required:
71 - interconnects79 - interconnects
@@ -161,8 +169,10 @@ examples: · 89 unmodified lines
161 169
162 power-domains = <&gcc PCIE_0_GDSC>;170 power-domains = <&gcc PCIE_0_GDSC>;
163 171
164 resets = <&gcc GCC_PCIE_0_BCR>;172 resets = <&gcc GCC_PCIE_0_BCR>,
165 reset-names = "pci";173 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
174 reset-names = "pci",
175 "link_down";
166 176
167 perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;177 perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
168 wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;178 wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml+4−10
@@ -33,8 +33,8 @@ properties: · 32 unmodified lines
33 - const: mhi # MHI registers33 - const: mhi # MHI registers
34 34
35 clocks:35 clocks:
36 minItems: 836 minItems: 6
37 maxItems: 837 maxItems: 6
38 38
39 clock-names:39 clock-names:
40 items:40 items:
@@ -44,8 +44,6 @@ properties: · 3 unmodified lines
44 - const: bus_master # Master AXI clock44 - const: bus_master # Master AXI clock
45 - const: bus_slave # Slave AXI clock45 - const: bus_slave # Slave AXI clock
46 - const: slave_q2a # Slave Q2A clock46 - const: slave_q2a # Slave Q2A clock
47 - const: ref # REFERENCE clock
48 - const: tbu # PCIe TBU clock
49 47
50 interrupts:48 interrupts:
51 minItems: 849 minItems: 8
@@ -117,17 +115,13 @@ examples: · 65 unmodified lines
117 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,115 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
118 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,116 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
119 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,117 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
120 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,118 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
121 <&gcc GCC_PCIE_0_CLKREF_CLK>,
122 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
123 clock-names = "pipe",119 clock-names = "pipe",
124 "aux",120 "aux",
125 "cfg",121 "cfg",
126 "bus_master",122 "bus_master",
127 "bus_slave",123 "bus_slave",
128 "slave_q2a",124 "slave_q2a";
129 "ref",
130 "tbu";
131 125
132 dma-coherent;126 dma-coherent;
133 127
Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml+10−11
@@ -16,7 +16,12 @@ description: · 15 unmodified lines
16 16
17properties:17properties:
18 compatible:18 compatible:
19 const: qcom,pcie-sm815019 oneOf:
20 - const: qcom,pcie-sm8150
21 - items:
22 - enum:
23 - qcom,pcie-qcs615
24 - const: qcom,pcie-sm8150
20 25
21 reg:26 reg:
22 minItems: 527 minItems: 5
@@ -33,8 +38,8 @@ properties: · 10 unmodified lines
33 - const: mhi # MHI registers38 - const: mhi # MHI registers
34 39
35 clocks:40 clocks:
36 minItems: 841 minItems: 6
37 maxItems: 842 maxItems: 6
38 43
39 clock-names:44 clock-names:
40 items:45 items:
@@ -44,8 +49,6 @@ properties: · 3 unmodified lines
44 - const: bus_master # Master AXI clock49 - const: bus_master # Master AXI clock
45 - const: bus_slave # Slave AXI clock50 - const: bus_slave # Slave AXI clock
46 - const: slave_q2a # Slave Q2A clock51 - const: slave_q2a # Slave Q2A clock
47 - const: tbu # PCIe TBU clock
48 - const: ref # REFERENCE clock
49 52
50 interrupts:53 interrupts:
51 minItems: 854 minItems: 8
@@ -111,17 +114,13 @@ examples: · 59 unmodified lines
111 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,114 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
112 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,115 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
113 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,116 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
114 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,117 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
115 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
116 <&rpmhcc RPMH_CXO_CLK>;
117 clock-names = "pipe",118 clock-names = "pipe",
118 "aux",119 "aux",
119 "cfg",120 "cfg",
120 "bus_master",121 "bus_master",
121 "bus_slave",122 "bus_slave",
122 "slave_q2a",123 "slave_q2a";
123 "tbu",
124 "ref";
125 124
126 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,125 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,126 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml+1−1
@@ -108,7 +108,7 @@ properties: · 107 unmodified lines
108 - description: See native 'dbi' CSR region for details.108 - description: See native 'dbi' CSR region for details.
109 enum: [ ctrl ]109 enum: [ ctrl ]
110 - description: See native 'elbi/app' CSR region for details.110 - description: See native 'elbi/app' CSR region for details.
111 enum: [ apb, mgmt, link, ulreg, appl ]111 enum: [ apb, mgmt, link, ulreg, appl, controller ]
112 - description: See native 'atu' CSR region for details.112 - description: See native 'atu' CSR region for details.
113 enum: [ atu_dma ]113 enum: [ atu_dma ]
114 - description: Syscon-related CSR regions.114 - description: Syscon-related CSR regions.
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt+0−14
@@ -1,14 +0,0 @@
1SPEAr13XX PCIe DT detail:
2================================
3
4SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
5controller.
6
7Required properties:
8- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
9- phys : phandle to PHY node associated with PCIe controller
10- phy-names : must be "pcie-phy"
11- All other definitions as per generic PCI bindings
12
13 Optional properties:
14- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
Documentation/devicetree/bindings/pci/st,spear1340-pcie.yaml+45−0
@@ -0,0 +1,45 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/st,spear1340-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ST SPEAr1340 PCIe controller
8
9maintainers:
10 - Pratyush Anand <pratyush.anand@gmail.com>
11
12description:
13 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
14 controller.
15
16select:
17 properties:
18 compatible:
19 contains:
20 const: st,spear1340-pcie
21 required:
22 - compatible
23
24properties:
25 compatible:
26 items:
27 - const: st,spear1340-pcie
28 - const: snps,dw-pcie
29
30 phys:
31 maxItems: 1
32
33 st,pcie-is-gen1:
34 type: boolean
35 description: Indicates forced gen1 initialization is needed.
36
37required:
38 - compatible
39 - phys
40 - phy-names
41
42allOf:
43 - $ref: snps,dw-pcie.yaml#
44
45unevaluatedProperties: false
Documentation/devicetree/bindings/pci/xgene-pci.txt+0−50
@@ -1,50 +0,0 @@
1* AppliedMicro X-Gene PCIe interface
2
3Required properties:
4- device_type: set to "pci"
5- compatible: should contain "apm,xgene-pcie" to identify the core.
6- reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names
8 property.
9- reg-names: Must include the following entries:
10 "csr": controller configuration registers.
11 "cfg": PCIe configuration space registers.
12- #address-cells: set to <3>
13- #size-cells: set to <2>
14- ranges: ranges for the outbound memory, I/O regions.
15- dma-ranges: ranges for the inbound memory regions.
16- #interrupt-cells: set to <1>
17- interrupt-map-mask and interrupt-map: standard PCI properties
18 to define the mapping of the PCIe interface to interrupt
19 numbers.
20- clocks: from common clock binding: handle to pci clock.
21
22Optional properties:
23- status: Either "ok" or "disabled".
24- dma-coherent: Present if DMA operations are coherent
25
26Example:
27
28 pcie0: pcie@1f2b0000 {
29 status = "disabled";
30 device_type = "pci";
31 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
32 #interrupt-cells = <1>;
33 #size-cells = <2>;
34 #address-cells = <3>;
35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
37 reg-names = "csr", "cfg";
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
46 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
47 dma-coherent;
48 clocks = <&pcie0clk 0>;
49 };
50
MAINTAINERS+3−3
@@ -18898,7 +18898,7 @@ M: Pali Rohár <pali@kernel.org> · 18897 unmodified lines
18898L: linux-pci@vger.kernel.org18898L: linux-pci@vger.kernel.org
18899L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)18899L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
18900S: Maintained18900S: Maintained
18901F: Documentation/devicetree/bindings/pci/aardvark-pci.txt18901F: Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml
18902F: drivers/pci/controller/pci-aardvark.c18902F: drivers/pci/controller/pci-aardvark.c
18903 18903
18904PCI DRIVER FOR ALTERA PCIE IP18904PCI DRIVER FOR ALTERA PCIE IP
@@ -18913,7 +18913,7 @@ M: Toan Le <toan@os.amperecomputing.com> · 8 unmodified lines
18913L: linux-pci@vger.kernel.org18913L: linux-pci@vger.kernel.org
18914L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)18914L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
18915S: Maintained18915S: Maintained
18916F: Documentation/devicetree/bindings/pci/xgene-pci.txt18916F: Documentation/devicetree/bindings/pci/apm,xgene-pcie.yaml
18917F: drivers/pci/controller/pci-xgene.c18917F: drivers/pci/controller/pci-xgene.c
18918 18918
18919PCI DRIVER FOR ARM VERSATILE PLATFORM18919PCI DRIVER FOR ARM VERSATILE PLATFORM
@@ -19232,7 +19232,7 @@ PCIE DRIVER FOR AMAZON ANNAPURNA LABS · 312 unmodified lines
19232M: Jonathan Chocron <jonnyc@amazon.com>19232M: Jonathan Chocron <jonnyc@amazon.com>
19233L: linux-pci@vger.kernel.org19233L: linux-pci@vger.kernel.org
19234S: Maintained19234S: Maintained
19235F: Documentation/devicetree/bindings/pci/pcie-al.txt19235F: Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml
19236F: drivers/pci/controller/dwc/pcie-al.c19236F: drivers/pci/controller/dwc/pcie-al.c
19237 19237
19238PCIE DRIVER FOR AMLOGIC MESON19238PCIE DRIVER FOR AMLOGIC MESON