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drm/radeon/kms: fix channel_remap setup (v2)

Most asics just use the hw default value which requires no explicit programming. For those that need a different value, the vbios will program it properly. As such, there's no need to program these registers explicitly in the driver. Changing MC_SHARED_CHREMAP requires a reload of all data in vram otherwise its contents will be scambled. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=40103 v2: drop now unused channel_remap functions.

Alex Deucher committed 15 years ago

Commit 12d51801 parent 02e68593 files · +0 −127Browse files

Unified · Split

3 files
  1. drivers/gpu/drm/radeon/evergreen.c +0 −44
  2. drivers/gpu/drm/radeon/ni.c +0 −32
  3. drivers/gpu/drm/radeon/rv770.c +0 −51
drivers/gpu/drm/radeon/evergreen.c+0−44
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, · 1589 unmodified lines
15901590 return backend_map;
15911591 }
15921592
1593−static void evergreen_program_channel_remap(struct radeon_device *rdev)
1594−{
1595− u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1596−
1597− tmp = RREG32(MC_SHARED_CHMAP);
1598− switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1599− case 0:
1600− case 1:
1601− case 2:
1602− case 3:
1603− default:
1604− /* default mapping */
1605− mc_shared_chremap = 0x00fac688;
1606− break;
1607− }
1608−
1609− switch (rdev->family) {
1610− case CHIP_HEMLOCK:
1611− case CHIP_CYPRESS:
1612− case CHIP_BARTS:
1613− tcp_chan_steer_lo = 0x54763210;
1614− tcp_chan_steer_hi = 0x0000ba98;
1615− break;
1616− case CHIP_JUNIPER:
1617− case CHIP_REDWOOD:
1618− case CHIP_CEDAR:
1619− case CHIP_PALM:
1620− case CHIP_SUMO:
1621− case CHIP_SUMO2:
1622− case CHIP_TURKS:
1623− case CHIP_CAICOS:
1624− default:
1625− tcp_chan_steer_lo = 0x76543210;
1626− tcp_chan_steer_hi = 0x0000ba98;
1627− break;
1628− }
1629−
1630− WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1631− WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1632− WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1633−}
1634−
16351593 static void evergreen_gpu_init(struct radeon_device *rdev)
16361594 {
16371595 u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev) · 440 unmodified lines
20782036 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
20792037 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
20802038
2081− evergreen_program_channel_remap(rdev);
2082−
20832039 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
20842040 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
20852041
drivers/gpu/drm/radeon/ni.c+0−32
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, · 568 unmodified lines
569569 return backend_map;
570570 }
571571
572−static void cayman_program_channel_remap(struct radeon_device *rdev)
573−{
574− u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
575−
576− tmp = RREG32(MC_SHARED_CHMAP);
577− switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
578− case 0:
579− case 1:
580− case 2:
581− case 3:
582− default:
583− /* default mapping */
584− mc_shared_chremap = 0x00fac688;
585− break;
586− }
587−
588− switch (rdev->family) {
589− case CHIP_CAYMAN:
590− default:
591− //tcp_chan_steer_lo = 0x54763210
592− tcp_chan_steer_lo = 0x76543210;
593− tcp_chan_steer_hi = 0x0000ba98;
594− break;
595− }
596−
597− WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
598− WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
599− WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
600−}
601−
602572 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
603573 u32 disable_mask_per_se,
604574 u32 max_disable_mask_per_se,
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev) · 237 unmodified lines
842812 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
843813 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
844814
845− cayman_program_channel_remap(rdev);
846−
847815 /* primary versions */
848816 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
849817 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
drivers/gpu/drm/radeon/rv770.c+0−51
@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, · 535 unmodified lines
536536 return backend_map;
537537 }
538538
539−static void rv770_program_channel_remap(struct radeon_device *rdev)
540−{
541− u32 tcp_chan_steer, mc_shared_chremap, tmp;
542− bool force_no_swizzle;
543−
544− switch (rdev->family) {
545− case CHIP_RV770:
546− case CHIP_RV730:
547− force_no_swizzle = false;
548− break;
549− case CHIP_RV710:
550− case CHIP_RV740:
551− default:
552− force_no_swizzle = true;
553− break;
554− }
555−
556− tmp = RREG32(MC_SHARED_CHMAP);
557− switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
558− case 0:
559− case 1:
560− default:
561− /* default mapping */
562− mc_shared_chremap = 0x00fac688;
563− break;
564− case 2:
565− case 3:
566− if (force_no_swizzle)
567− mc_shared_chremap = 0x00fac688;
568− else
569− mc_shared_chremap = 0x00bbc298;
570− break;
571− }
572−
573− if (rdev->family == CHIP_RV740)
574− tcp_chan_steer = 0x00ef2a60;
575− else
576− tcp_chan_steer = 0x00fac688;
577−
578− /* RV770 CE has special chremap setup */
579− if (rdev->pdev->device == 0x944e) {
580− tcp_chan_steer = 0x00b08b08;
581− mc_shared_chremap = 0x00b08b08;
582− }
583−
584− WREG32(TCP_CHAN_STEER, tcp_chan_steer);
585− WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
586−}
587−
588539 static void rv770_gpu_init(struct radeon_device *rdev)
589540 {
590541 int i, j, num_qd_pipes;
@@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev) · 194 unmodified lines
785736 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
786737 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
787738
788− rv770_program_channel_remap(rdev);
789−
790739 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
791740 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
792741 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);