History

phy: qcom-qmp-combo: rename DP_PHY register pointer

The DP_PHY registers have erroneously been referred to as "PCS" registers since DisplayPort support was added to the QMP drivers (including in the devicetree binding). Rename the corresponding pointer to match the register names. Note that the repeated "dp" in the field name is intentional and this DP register block is called "DP_PHY" (not just "PHY").

Johan Hovold committed 3 years ago

Commit 133836a1 parent 9e5b59e1 file · +70 −69Browse files

Unified · Split

drivers/phy/qualcomm/phy-qcom-qmp-combo.c+70−69
@@ -878,7 +878,7 @@ struct qmp_combo { · 877 unmodified lines
878 void __iomem *dp_serdes;878 void __iomem *dp_serdes;
879 void __iomem *dp_tx;879 void __iomem *dp_tx;
880 void __iomem *dp_tx2;880 void __iomem *dp_tx2;
881 void __iomem *dp_pcs;881 void __iomem *dp_dp_phy;
882 882
883 struct clk *pipe_clk;883 struct clk *pipe_clk;
884 struct clk_bulk_data *clks;884 struct clk_bulk_data *clks;
@@ -1252,20 +1252,20 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) · 367 unmodified lines
1252{1252{
1253 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |1253 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1254 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,1254 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
1255 qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);1255 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1256 1256
1257 /* Turn on BIAS current for PHY/PLL */1257 /* Turn on BIAS current for PHY/PLL */
1258 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |1258 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
1259 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,1259 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
1260 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);1260 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
1261 1261
1262 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);1262 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1263 1263
1264 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |1264 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1265 DP_PHY_PD_CTL_LANE_0_1_PWRDN |1265 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
1266 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |1266 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
1267 DP_PHY_PD_CTL_DP_CLAMP_EN,1267 DP_PHY_PD_CTL_DP_CLAMP_EN,
1268 qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);1268 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1269 1269
1270 writel(QSERDES_V3_COM_BIAS_EN |1270 writel(QSERDES_V3_COM_BIAS_EN |
1271 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |1271 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
@@ -1273,22 +1273,22 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) · 1 unmodified line
1273 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,1273 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
1274 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);1274 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
1275 1275
1276 writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG0);1276 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
1277 writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);1277 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1278 writel(0x24, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);1278 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1279 writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG3);1279 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
1280 writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG4);1280 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
1281 writel(0x26, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG5);1281 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
1282 writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG6);1282 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
1283 writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG7);1283 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
1284 writel(0xbb, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG8);1284 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
1285 writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG9);1285 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
1286 qmp->dp_aux_cfg = 0;1286 qmp->dp_aux_cfg = 0;
1287 1287
1288 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |1288 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
1289 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |1289 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
1290 PHY_AUX_REQ_ERR_MASK,1290 PHY_AUX_REQ_ERR_MASK,
1291 qmp->dp_pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);1291 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
1292}1292}
1293 1293
1294static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,1294static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
@@ -1372,12 +1372,12 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) · 77 unmodified lines
1372 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)1372 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
1373 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;1373 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
1374 * if (orientation == ORIENTATION_CC2)1374 * if (orientation == ORIENTATION_CC2)
1375 * writel(0x4c, qmp->dp_pcs + QSERDES_V3_DP_PHY_MODE);1375 * writel(0x4c, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_MODE);
1376 */1376 */
1377 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;1377 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
1378 writel(val, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);1378 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1379 1379
1380 writel(0x5c, qmp->dp_pcs + QSERDES_DP_PHY_MODE);1380 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
1381 1381
1382 return reverse;1382 return reverse;
1383}1383}
@@ -1390,8 +1390,8 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) · 6 unmodified lines
1390 1390
1391 qmp_combo_configure_dp_mode(qmp);1391 qmp_combo_configure_dp_mode(qmp);
1392 1392
1393 writel(0x05, qmp->dp_pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);1393 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
1394 writel(0x05, qmp->dp_pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);1394 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
1395 1395
1396 switch (dp_opts->link_rate) {1396 switch (dp_opts->link_rate) {
1397 case 1620:1397 case 1620:
@@ -1414,16 +1414,16 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) · 16 unmodified lines
1414 /* Other link rates aren't supported */1414 /* Other link rates aren't supported */
1415 return -EINVAL;1415 return -EINVAL;
1416 }1416 }
1417 writel(phy_vco_div, qmp->dp_pcs + QSERDES_V3_DP_PHY_VCO_DIV);1417 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV);
1418 1418
1419 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);1419 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
1420 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);1420 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
1421 1421
1422 writel(0x04, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);1422 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1423 writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1423 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1424 writel(0x05, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1424 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1425 writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1425 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1426 writel(0x09, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1426 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1427 1427
1428 writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL);1428 writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL);
1429 1429
@@ -1434,20 +1434,20 @@ static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) · 4 unmodified lines
1434 10000))1434 10000))
1435 return -ETIMEDOUT;1435 return -ETIMEDOUT;
1436 1436
1437 writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1437 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1438 1438
1439 if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V3_DP_PHY_STATUS,1439 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
1440 status,1440 status,
1441 ((status & BIT(1)) > 0),1441 ((status & BIT(1)) > 0),
1442 500,1442 500,
1443 10000))1443 10000))
1444 return -ETIMEDOUT;1444 return -ETIMEDOUT;
1445 1445
1446 writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1446 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1447 udelay(2000);1447 udelay(2000);
1448 writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1448 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1449 1449
1450 return readl_poll_timeout(qmp->dp_pcs + QSERDES_V3_DP_PHY_STATUS,1450 return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
1451 status,1451 status,
1452 ((status & BIT(1)) > 0),1452 ((status & BIT(1)) > 0),
1453 500,1453 500,
@@ -1467,7 +1467,7 @@ static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) · 13 unmodified lines
1467 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);1467 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
1468 val = cfg1_settings[qmp->dp_aux_cfg];1468 val = cfg1_settings[qmp->dp_aux_cfg];
1469 1469
1470 writel(val, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);1470 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1471 1471
1472 return 0;1472 return 0;
1473}1473}
@@ -1476,27 +1476,27 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) · 2 unmodified lines
1476{1476{
1477 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |1477 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1478 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,1478 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
1479 qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);1479 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1480 1480
1481 /* Turn on BIAS current for PHY/PLL */1481 /* Turn on BIAS current for PHY/PLL */
1482 writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);1482 writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
1483 1483
1484 writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG0);1484 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
1485 writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);1485 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1486 writel(0xa4, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);1486 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1487 writel(0x00, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG3);1487 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
1488 writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG4);1488 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
1489 writel(0x26, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG5);1489 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
1490 writel(0x0a, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG6);1490 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
1491 writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG7);1491 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
1492 writel(0xb7, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG8);1492 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
1493 writel(0x03, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG9);1493 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
1494 qmp->dp_aux_cfg = 0;1494 qmp->dp_aux_cfg = 0;
1495 1495
1496 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |1496 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
1497 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |1497 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
1498 PHY_AUX_REQ_ERR_MASK,1498 PHY_AUX_REQ_ERR_MASK,
1499 qmp->dp_pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);1499 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
1500}1500}
1501 1501
1502static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)1502static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
@@ -1518,15 +1518,15 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 15 unmodified lines
1518 u32 phy_vco_div, status;1518 u32 phy_vco_div, status;
1519 unsigned long pixel_freq;1519 unsigned long pixel_freq;
1520 1520
1521 writel(0x0f, qmp->dp_pcs + QSERDES_V4_DP_PHY_CFG_1);1521 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
1522 1522
1523 qmp_combo_configure_dp_mode(qmp);1523 qmp_combo_configure_dp_mode(qmp);
1524 1524
1525 writel(0x13, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);1525 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1526 writel(0xa4, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG2);1526 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1527 1527
1528 writel(0x05, qmp->dp_pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);1528 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
1529 writel(0x05, qmp->dp_pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);1529 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
1530 1530
1531 switch (dp_opts->link_rate) {1531 switch (dp_opts->link_rate) {
1532 case 1620:1532 case 1620:
@@ -1549,15 +1549,15 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 16 unmodified lines
1549 /* Other link rates aren't supported */1549 /* Other link rates aren't supported */
1550 return -EINVAL;1550 return -EINVAL;
1551 }1551 }
1552 writel(phy_vco_div, qmp->dp_pcs + QSERDES_V4_DP_PHY_VCO_DIV);1552 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
1553 1553
1554 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);1554 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
1555 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);1555 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
1556 1556
1557 writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1557 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1558 writel(0x05, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1558 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1559 writel(0x01, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1559 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1560 writel(0x09, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1560 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1561 1561
1562 writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL);1562 writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL);
1563 1563
@@ -1582,16 +1582,16 @@ static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) · 18 unmodified lines
1582 10000))1582 10000))
1583 return -ETIMEDOUT;1583 return -ETIMEDOUT;
1584 1584
1585 writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1585 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1586 1586
1587 if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,1587 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
1588 status,1588 status,
1589 ((status & BIT(0)) > 0),1589 ((status & BIT(0)) > 0),
1590 500,1590 500,
1591 10000))1591 10000))
1592 return -ETIMEDOUT;1592 return -ETIMEDOUT;
1593 1593
1594 if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,1594 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
1595 status,1595 status,
1596 ((status & BIT(1)) > 0),1596 ((status & BIT(1)) > 0),
1597 500,1597 500,
@@ -1640,11 +1640,11 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) · 42 unmodified lines
1640 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);1640 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
1641 writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);1641 writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
1642 1642
1643 writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1643 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1644 udelay(2000);1644 udelay(2000);
1645 writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1645 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1646 1646
1647 if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,1647 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
1648 status,1648 status,
1649 ((status & BIT(1)) > 0),1649 ((status & BIT(1)) > 0),
1650 500,1650 500,
@@ -1697,11 +1697,11 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) · 46 unmodified lines
1697 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);1697 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
1698 writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);1698 writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
1699 1699
1700 writel(0x18, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1700 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1701 udelay(2000);1701 udelay(2000);
1702 writel(0x19, qmp->dp_pcs + QSERDES_DP_PHY_CFG);1702 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
1703 1703
1704 if (readl_poll_timeout(qmp->dp_pcs + QSERDES_V4_DP_PHY_STATUS,1704 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
1705 status,1705 status,
1706 ((status & BIT(1)) > 0),1706 ((status & BIT(1)) > 0),
1707 500,1707 500,
@@ -1733,7 +1733,7 @@ static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) · 25 unmodified lines
1733 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);1733 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
1734 val = cfg1_settings[qmp->dp_aux_cfg];1734 val = cfg1_settings[qmp->dp_aux_cfg];
1735 1735
1736 writel(val, qmp->dp_pcs + QSERDES_DP_PHY_AUX_CFG1);1736 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1737 1737
1738 return 0;1738 return 0;
1739}1739}
@@ -1906,7 +1906,7 @@ static int qmp_combo_dp_power_off(struct phy *phy) · 166 unmodified lines
1906 struct qmp_combo *qmp = phy_get_drvdata(phy);1906 struct qmp_combo *qmp = phy_get_drvdata(phy);
1907 1907
1908 /* Assert DP PHY power down */1908 /* Assert DP PHY power down */
1909 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_pcs + QSERDES_DP_PHY_PD_CTL);1909 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1910 1910
1911 return 0;1911 return 0;
1912}1912}
@@ -2463,15 +2463,16 @@ static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_nod · 550 unmodified lines
2463 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;2463 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
2464 * tx2 -> 3; rx2 -> 42464 * tx2 -> 3; rx2 -> 4
2465 *2465 *
2466 * Note that only tx/tx2 and pcs are used by the DP implementation.2466 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
2467 * implementation.
2467 */2468 */
2468 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);2469 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
2469 if (IS_ERR(qmp->dp_tx))2470 if (IS_ERR(qmp->dp_tx))
2470 return PTR_ERR(qmp->dp_tx);2471 return PTR_ERR(qmp->dp_tx);
2471 2472
2472 qmp->dp_pcs = devm_of_iomap(dev, np, 2, NULL);2473 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
2473 if (IS_ERR(qmp->dp_pcs))2474 if (IS_ERR(qmp->dp_dp_phy))
2474 return PTR_ERR(qmp->dp_pcs);2475 return PTR_ERR(qmp->dp_dp_phy);
2475 2476
2476 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);2477 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
2477 if (IS_ERR(qmp->dp_tx2))2478 if (IS_ERR(qmp->dp_tx2))