| @@ -1579,6 +1579,7 @@ static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) · 1578 unmodified lines |
| 1579 | { | 1579 | { |
| 1580 | /* Initialize qm port parameters */ | 1580 | /* Initialize qm port parameters */ |
| 1581 | u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; | 1581 | u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; |
| | 1582 | struct qed_dev *cdev = p_hwfn->cdev; |
| 1582 | | 1583 | |
| 1583 | /* indicate how ooo and high pri traffic is dealt with */ | 1584 | /* indicate how ooo and high pri traffic is dealt with */ |
| 1584 | active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? | 1585 | active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? |
| @@ -1588,11 +1589,13 @@ static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) · 3 unmodified lines |
| 1588 | for (i = 0; i < num_ports; i++) { | 1589 | for (i = 0; i < num_ports; i++) { |
| 1589 | struct init_qm_port_params *p_qm_port = | 1590 | struct init_qm_port_params *p_qm_port = |
| 1590 | &p_hwfn->qm_info.qm_port_params[i]; | 1591 | &p_hwfn->qm_info.qm_port_params[i]; |
| | 1592 | u16 pbf_max_cmd_lines; |
| 1591 | | 1593 | |
| 1592 | p_qm_port->active = 1; | 1594 | p_qm_port->active = 1; |
| 1593 | p_qm_port->active_phys_tcs = active_phys_tcs; | 1595 | p_qm_port->active_phys_tcs = active_phys_tcs; |
| 1594 | p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; | 1596 | pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev); |
| 1595 | p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; | 1597 | p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports; |
| | 1598 | p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports; |
| 1596 | } | 1599 | } |
| 1597 | } | 1600 | } |
| 1598 | | 1601 | |
| @@ -3607,14 +3610,39 @@ __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, · 2008 unmodified lines |
| 3607 | return 0; | 3610 | return 0; |
| 3608 | } | 3611 | } |
| 3609 | | 3612 | |
| | 3613 | static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = { |
| | 3614 | {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2}, |
| | 3615 | {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2}, |
| | 3616 | {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2}, |
| | 3617 | {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,}, |
| | 3618 | {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2}, |
| | 3619 | {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2}, |
| | 3620 | {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2}, |
| | 3621 | {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2}, |
| | 3622 | {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2}, |
| | 3623 | {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2}, |
| | 3624 | {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS}, |
| | 3625 | {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES}, |
| | 3626 | {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2}, |
| | 3627 | }; |
| | 3628 | |
| | 3629 | u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type) |
| | 3630 | { |
| | 3631 | enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2; |
| | 3632 | |
| | 3633 | if (type >= QED_NUM_HSI_DEFS) { |
| | 3634 | DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type); |
| | 3635 | return 0; |
| | 3636 | } |
| | 3637 | |
| | 3638 | return qed_hsi_def_val[type][chip_id]; |
| | 3639 | } |
| 3610 | static int | 3640 | static int |
| 3611 | qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) | 3641 | qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
| 3612 | { | 3642 | { |
| 3613 | bool b_ah = QED_IS_AH(p_hwfn->cdev); | | |
| 3614 | u32 resc_max_val, mcp_resp; | 3643 | u32 resc_max_val, mcp_resp; |
| 3615 | u8 res_id; | 3644 | u8 res_id; |
| 3616 | int rc; | 3645 | int rc; |
| 3617 | | | |
| 3618 | for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { | 3646 | for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { |
| 3619 | switch (res_id) { | 3647 | switch (res_id) { |
| 3620 | case QED_LL2_RAM_QUEUE: | 3648 | case QED_LL2_RAM_QUEUE: |
| @@ -3630,8 +3658,8 @@ qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) · 9 unmodified lines |
| 3630 | resc_max_val = NUM_OF_GLOBAL_QUEUES; | 3658 | resc_max_val = NUM_OF_GLOBAL_QUEUES; |
| 3631 | break; | 3659 | break; |
| 3632 | case QED_RDMA_STATS_QUEUE: | 3660 | case QED_RDMA_STATS_QUEUE: |
| 3633 | resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 | 3661 | resc_max_val = |
| 3634 | : RDMA_NUM_STATISTIC_COUNTERS_BB; | 3662 | NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev); |
| 3635 | break; | 3663 | break; |
| 3636 | case QED_BDQ: | 3664 | case QED_BDQ: |
| 3637 | resc_max_val = BDQ_NUM_RESOURCES; | 3665 | resc_max_val = BDQ_NUM_RESOURCES; |
| @@ -3664,28 +3692,24 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, · 26 unmodified lines |
| 3664 | u32 *p_resc_num, u32 *p_resc_start) | 3692 | u32 *p_resc_num, u32 *p_resc_start) |
| 3665 | { | 3693 | { |
| 3666 | u8 num_funcs = p_hwfn->num_funcs_on_engine; | 3694 | u8 num_funcs = p_hwfn->num_funcs_on_engine; |
| 3667 | bool b_ah = QED_IS_AH(p_hwfn->cdev); | 3695 | struct qed_dev *cdev = p_hwfn->cdev; |
| 3668 | | 3696 | |
| 3669 | switch (res_id) { | 3697 | switch (res_id) { |
| 3670 | case QED_L2_QUEUE: | 3698 | case QED_L2_QUEUE: |
| 3671 | *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : | 3699 | *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs; |
| 3672 | MAX_NUM_L2_QUEUES_BB) / num_funcs; | | |
| 3673 | break; | 3700 | break; |
| 3674 | case QED_VPORT: | 3701 | case QED_VPORT: |
| 3675 | *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : | 3702 | *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs; |
| 3676 | MAX_NUM_VPORTS_BB) / num_funcs; | | |
| 3677 | break; | 3703 | break; |
| 3678 | case QED_RSS_ENG: | 3704 | case QED_RSS_ENG: |
| 3679 | *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : | 3705 | *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs; |
| 3680 | ETH_RSS_ENGINE_NUM_BB) / num_funcs; | | |
| 3681 | break; | 3706 | break; |
| 3682 | case QED_PQ: | 3707 | case QED_PQ: |
| 3683 | *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : | 3708 | *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs; |
| 3684 | MAX_QM_TX_QUEUES_BB) / num_funcs; | | |
| 3685 | *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ | 3709 | *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ |
| 3686 | break; | 3710 | break; |
| 3687 | case QED_RL: | 3711 | case QED_RL: |
| 3688 | *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; | 3712 | *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs; |
| 3689 | break; | 3713 | break; |
| 3690 | case QED_MAC: | 3714 | case QED_MAC: |
| 3691 | case QED_VLAN: | 3715 | case QED_VLAN: |
| @@ -3693,8 +3717,7 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, · 1 unmodified line |
| 3693 | *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; | 3717 | *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; |
| 3694 | break; | 3718 | break; |
| 3695 | case QED_ILT: | 3719 | case QED_ILT: |
| 3696 | *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : | 3720 | *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs; |
| 3697 | PXP_NUM_ILT_RECORDS_BB) / num_funcs; | | |
| 3698 | break; | 3721 | break; |
| 3699 | case QED_LL2_RAM_QUEUE: | 3722 | case QED_LL2_RAM_QUEUE: |
| 3700 | *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs; | 3723 | *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs; |
| @@ -3708,8 +3731,7 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, · 7 unmodified lines |
| 3708 | *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; | 3731 | *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; |
| 3709 | break; | 3732 | break; |
| 3710 | case QED_RDMA_STATS_QUEUE: | 3733 | case QED_RDMA_STATS_QUEUE: |
| 3711 | *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 : | 3734 | *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs; |
| 3712 | RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs; | | |
| 3713 | break; | 3735 | break; |
| 3714 | case QED_BDQ: | 3736 | case QED_BDQ: |
| 3715 | if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && | 3737 | if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && |