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drm/i915: Implement w/a 22010492432 for adl-s

adl-s needs the combo PLL DCO fraction w/a as well. Gets us slightly more accurate clock out of the PLL.

Ville Syrjälä committed 4 years ago

Commit 13bd2591 parent a111daf1 file · +2 −2Browse files

Unified · Split

drivers/gpu/drm/i915/display/intel_dpll_mgr.c+2−2
@@ -2396,7 +2396,7 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params, · 2395 unmodified lines
2396}2396}
2397 2397
2398/*2398/*
2399 * Display WA #22010492432: ehl, tgl, adl-p2399 * Display WA #22010492432: ehl, tgl, adl-s, adl-p
2400 * Program half of the nominal DCO divider fraction value.2400 * Program half of the nominal DCO divider fraction value.
2401 */2401 */
2402static bool2402static bool
@@ -2404,7 +2404,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) · 1 unmodified line
2404{2404{
2405 return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&2405 return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
2406 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||2406 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
2407 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&2407 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
2408 i915->dpll.ref_clks.nssc == 38400;2408 i915->dpll.ref_clks.nssc == 38400;
2409}2409}
2410 2410