drm-misc-next for 5.2: UAPI Changes: -syncobj: Add TIMELINE_WAIT|QUERY|TRANSFER|TIMELINE_SIGNAL ioctls (Chunming) -Clarify that 1.0 can be represented by drm_color_lut (Daniel) Cross-subsystem Changes: -dt-bindings: Add binding for rk3066 hdmi (Johan) -dt-bindings: Add binding for Feiyang FY07024DI26A30-D panel (Jagan) -dt-bindings: Add Rocktech vendor prefix and jh057n00900 panel bindings (Guido) -MAINTAINERS: Add lima and ASPEED entries (Joel & Qiang) Core Changes: -memory: use dma_alloc_coherent when mem encryption is active (Christian) -dma_buf: add support for a dma_fence chain (Christian) -shmem_gem: fix off-by-one bug in new shmem gem helpers (Dan) Driver Changes: -rockchip: Add support for rk3066 hdmi (Johan) -ASPEED: Add driver supporting ASPEED BMC display controller to drm (Joel) -lima: Add driver supporting Arm Mali4xx gpus to drm (Qiang) -vc4/v3d: Various cleanups and improved error handling (Eric) -panel: Add support for Feiyang FY07024DI26A30-D MIPI-DSI panel (Jagan) -panel: Add support for Rocktech jh057n00900 MIPI-DSI panel (Guido) Cc: Johan Jonker <jbx6244@gmail.com> Cc: Christian König <christian.koenig@amd.com> Cc: Chunming Zhou <david1.zhou@amd.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: Eric Anholt <eric@anholt.net> Cc: Qiang Yu <yuq825@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Guido Günther <agx@sigxcpu.org> Cc: Joel Stanley <joel@jms.id.au> [airlied: fixed XA limit build breakage, Rodrigo also submitted the same patch, but I squashed it in the merge.] Signed-off-by: Dave Airlie <airlied@redhat.com>
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| @@ -735,8 +735,18 @@ struct drm_syncobj_handle { · 734 unmodified lines | |||
| 735 | __u32 pad; | 735 | __u32 pad; |
| 736 | }; | 736 | }; |
| 737 | 737 | ||
| 738 | struct drm_syncobj_transfer { | ||
| 739 | __u32 src_handle; | ||
| 740 | __u32 dst_handle; | ||
| 741 | __u64 src_point; | ||
| 742 | __u64 dst_point; | ||
| 743 | __u32 flags; | ||
| 744 | __u32 pad; | ||
| 745 | }; | ||
| 746 | |||
| 738 | #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) | 747 | #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) |
| 739 | #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) | 748 | #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) |
| 749 | #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ | ||
| 740 | struct drm_syncobj_wait { | 750 | struct drm_syncobj_wait { |
| 741 | __u64 handles; | 751 | __u64 handles; |
| 742 | /* absolute timeout */ | 752 | /* absolute timeout */ |
| @@ -747,12 +757,33 @@ struct drm_syncobj_wait { · 4 unmodified lines | |||
| 747 | __u32 pad; | 757 | __u32 pad; |
| 748 | }; | 758 | }; |
| 749 | 759 | ||
| 760 | struct drm_syncobj_timeline_wait { | ||
| 761 | __u64 handles; | ||
| 762 | /* wait on specific timeline point for every handles*/ | ||
| 763 | __u64 points; | ||
| 764 | /* absolute timeout */ | ||
| 765 | __s64 timeout_nsec; | ||
| 766 | __u32 count_handles; | ||
| 767 | __u32 flags; | ||
| 768 | __u32 first_signaled; /* only valid when not waiting all */ | ||
| 769 | __u32 pad; | ||
| 770 | }; | ||
| 771 | |||
| 772 | |||
| 750 | struct drm_syncobj_array { | 773 | struct drm_syncobj_array { |
| 751 | __u64 handles; | 774 | __u64 handles; |
| 752 | __u32 count_handles; | 775 | __u32 count_handles; |
| 753 | __u32 pad; | 776 | __u32 pad; |
| 754 | }; | 777 | }; |
| 755 | 778 | ||
| 779 | struct drm_syncobj_timeline_array { | ||
| 780 | __u64 handles; | ||
| 781 | __u64 points; | ||
| 782 | __u32 count_handles; | ||
| 783 | __u32 pad; | ||
| 784 | }; | ||
| 785 | |||
| 786 | |||
| 756 | /* Query current scanout sequence number */ | 787 | /* Query current scanout sequence number */ |
| 757 | struct drm_crtc_get_sequence { | 788 | struct drm_crtc_get_sequence { |
| 758 | __u32 crtc_id; /* requested crtc_id */ | 789 | __u32 crtc_id; /* requested crtc_id */ |
| @@ -909,6 +940,11 @@ extern "C" { · 150 unmodified lines | |||
| 909 | #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) | 940 | #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) |
| 910 | #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) | 941 | #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) |
| 911 | 942 | ||
| 943 | #define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) | ||
| 944 | #define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) | ||
| 945 | #define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) | ||
| 946 | #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) | ||
| 947 | |||
| 912 | /** | 948 | /** |
| 913 | * Device specific ioctls should only be in their respective headers | 949 | * Device specific ioctls should only be in their respective headers |
| 914 | * The device specific ioctl range is from 0x40 to 0x9f. | 950 | * The device specific ioctl range is from 0x40 to 0x9f. |
| @@ -621,7 +621,8 @@ struct drm_color_ctm { · 620 unmodified lines | |||
| 621 | 621 | ||
| 622 | struct drm_color_lut { | 622 | struct drm_color_lut { |
| 623 | /* | 623 | /* |
| 624 | * Data is U0.16 fixed point format. | 624 | * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and |
| 625 | * 0xffff == 1.0. | ||
| 625 | */ | 626 | */ |
| 626 | __u16 red; | 627 | __u16 red; |
| 627 | __u16 green; | 628 | __u16 green; |
| @@ -0,0 +1,169 @@ | |||
| 1 | /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */ | ||
| 2 | /* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */ | ||
| 3 | |||
| 4 | #ifndef __LIMA_DRM_H__ | ||
| 5 | #define __LIMA_DRM_H__ | ||
| 6 | |||
| 7 | #include "drm.h" | ||
| 8 | |||
| 9 | #if defined(__cplusplus) | ||
| 10 | extern "C" { | ||
| 11 | #endif | ||
| 12 | |||
| 13 | enum drm_lima_param_gpu_id { | ||
| 14 | DRM_LIMA_PARAM_GPU_ID_UNKNOWN, | ||
| 15 | DRM_LIMA_PARAM_GPU_ID_MALI400, | ||
| 16 | DRM_LIMA_PARAM_GPU_ID_MALI450, | ||
| 17 | }; | ||
| 18 | |||
| 19 | enum drm_lima_param { | ||
| 20 | DRM_LIMA_PARAM_GPU_ID, | ||
| 21 | DRM_LIMA_PARAM_NUM_PP, | ||
| 22 | DRM_LIMA_PARAM_GP_VERSION, | ||
| 23 | DRM_LIMA_PARAM_PP_VERSION, | ||
| 24 | }; | ||
| 25 | |||
| 26 | /** | ||
| 27 | * get various information of the GPU | ||
| 28 | */ | ||
| 29 | struct drm_lima_get_param { | ||
| 30 | __u32 param; /* in, value in enum drm_lima_param */ | ||
| 31 | __u32 pad; /* pad, must be zero */ | ||
| 32 | __u64 value; /* out, parameter value */ | ||
| 33 | }; | ||
| 34 | |||
| 35 | /** | ||
| 36 | * create a buffer for used by GPU | ||
| 37 | */ | ||
| 38 | struct drm_lima_gem_create { | ||
| 39 | __u32 size; /* in, buffer size */ | ||
| 40 | __u32 flags; /* in, currently no flags, must be zero */ | ||
| 41 | __u32 handle; /* out, GEM buffer handle */ | ||
| 42 | __u32 pad; /* pad, must be zero */ | ||
| 43 | }; | ||
| 44 | |||
| 45 | /** | ||
| 46 | * get information of a buffer | ||
| 47 | */ | ||
| 48 | struct drm_lima_gem_info { | ||
| 49 | __u32 handle; /* in, GEM buffer handle */ | ||
| 50 | __u32 va; /* out, virtual address mapped into GPU MMU */ | ||
| 51 | __u64 offset; /* out, used to mmap this buffer to CPU */ | ||
| 52 | }; | ||
| 53 | |||
| 54 | #define LIMA_SUBMIT_BO_READ 0x01 | ||
| 55 | #define LIMA_SUBMIT_BO_WRITE 0x02 | ||
| 56 | |||
| 57 | /* buffer information used by one task */ | ||
| 58 | struct drm_lima_gem_submit_bo { | ||
| 59 | __u32 handle; /* in, GEM buffer handle */ | ||
| 60 | __u32 flags; /* in, buffer read/write by GPU */ | ||
| 61 | }; | ||
| 62 | |||
| 63 | #define LIMA_GP_FRAME_REG_NUM 6 | ||
| 64 | |||
| 65 | /* frame used to setup GP for each task */ | ||
| 66 | struct drm_lima_gp_frame { | ||
| 67 | __u32 frame[LIMA_GP_FRAME_REG_NUM]; | ||
| 68 | }; | ||
| 69 | |||
| 70 | #define LIMA_PP_FRAME_REG_NUM 23 | ||
| 71 | #define LIMA_PP_WB_REG_NUM 12 | ||
| 72 | |||
| 73 | /* frame used to setup mali400 GPU PP for each task */ | ||
| 74 | struct drm_lima_m400_pp_frame { | ||
| 75 | __u32 frame[LIMA_PP_FRAME_REG_NUM]; | ||
| 76 | __u32 num_pp; | ||
| 77 | __u32 wb[3 * LIMA_PP_WB_REG_NUM]; | ||
| 78 | __u32 plbu_array_address[4]; | ||
| 79 | __u32 fragment_stack_address[4]; | ||
| 80 | }; | ||
| 81 | |||
| 82 | /* frame used to setup mali450 GPU PP for each task */ | ||
| 83 | struct drm_lima_m450_pp_frame { | ||
| 84 | __u32 frame[LIMA_PP_FRAME_REG_NUM]; | ||
| 85 | __u32 num_pp; | ||
| 86 | __u32 wb[3 * LIMA_PP_WB_REG_NUM]; | ||
| 87 | __u32 use_dlbu; | ||
| 88 | __u32 _pad; | ||
| 89 | union { | ||
| 90 | __u32 plbu_array_address[8]; | ||
| 91 | __u32 dlbu_regs[4]; | ||
| 92 | }; | ||
| 93 | __u32 fragment_stack_address[8]; | ||
| 94 | }; | ||
| 95 | |||
| 96 | #define LIMA_PIPE_GP 0x00 | ||
| 97 | #define LIMA_PIPE_PP 0x01 | ||
| 98 | |||
| 99 | #define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0) | ||
| 100 | |||
| 101 | /** | ||
| 102 | * submit a task to GPU | ||
| 103 | * | ||
| 104 | * User can always merge multi sync_file and drm_syncobj | ||
| 105 | * into one drm_syncobj as in_sync[0], but we reserve | ||
| 106 | * in_sync[1] for another task's out_sync to avoid the | ||
| 107 | * export/import/merge pass when explicit sync. | ||
| 108 | */ | ||
| 109 | struct drm_lima_gem_submit { | ||
| 110 | __u32 ctx; /* in, context handle task is submitted to */ | ||
| 111 | __u32 pipe; /* in, which pipe to use, GP/PP */ | ||
| 112 | __u32 nr_bos; /* in, array length of bos field */ | ||
| 113 | __u32 frame_size; /* in, size of frame field */ | ||
| 114 | __u64 bos; /* in, array of drm_lima_gem_submit_bo */ | ||
| 115 | __u64 frame; /* in, GP/PP frame */ | ||
| 116 | __u32 flags; /* in, submit flags */ | ||
| 117 | __u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */ | ||
| 118 | __u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */ | ||
| 119 | }; | ||
| 120 | |||
| 121 | #define LIMA_GEM_WAIT_READ 0x01 | ||
| 122 | #define LIMA_GEM_WAIT_WRITE 0x02 | ||
| 123 | |||
| 124 | /** | ||
| 125 | * wait pending GPU task finish of a buffer | ||
| 126 | */ | ||
| 127 | struct drm_lima_gem_wait { | ||
| 128 | __u32 handle; /* in, GEM buffer handle */ | ||
| 129 | __u32 op; /* in, CPU want to read/write this buffer */ | ||
| 130 | __s64 timeout_ns; /* in, wait timeout in absulute time */ | ||
| 131 | }; | ||
| 132 | |||
| 133 | /** | ||
| 134 | * create a context | ||
| 135 | */ | ||
| 136 | struct drm_lima_ctx_create { | ||
| 137 | __u32 id; /* out, context handle */ | ||
| 138 | __u32 _pad; /* pad, must be zero */ | ||
| 139 | }; | ||
| 140 | |||
| 141 | /** | ||
| 142 | * free a context | ||
| 143 | */ | ||
| 144 | struct drm_lima_ctx_free { | ||
| 145 | __u32 id; /* in, context handle */ | ||
| 146 | __u32 _pad; /* pad, must be zero */ | ||
| 147 | }; | ||
| 148 | |||
| 149 | #define DRM_LIMA_GET_PARAM 0x00 | ||
| 150 | #define DRM_LIMA_GEM_CREATE 0x01 | ||
| 151 | #define DRM_LIMA_GEM_INFO 0x02 | ||
| 152 | #define DRM_LIMA_GEM_SUBMIT 0x03 | ||
| 153 | #define DRM_LIMA_GEM_WAIT 0x04 | ||
| 154 | #define DRM_LIMA_CTX_CREATE 0x05 | ||
| 155 | #define DRM_LIMA_CTX_FREE 0x06 | ||
| 156 | |||
| 157 | #define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param) | ||
| 158 | #define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create) | ||
| 159 | #define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info) | ||
| 160 | #define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit) | ||
| 161 | #define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait) | ||
| 162 | #define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create) | ||
| 163 | #define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free) | ||
| 164 | |||
| 165 | #if defined(__cplusplus) | ||
| 166 | } | ||
| 167 | #endif | ||
| 168 | |||
| 169 | #endif /* __LIMA_DRM_H__ */ | ||