History

Merge tag 'drm-intel-next-2019-05-24' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Features: - Engine discovery query (Tvrtko) - Support for DP YCbCr4:2:0 outputs (Gwan-gyeong) - HDCP revocation support, refactoring (Ramalingam) - Remove DRM_AUTH from IOCTLs which also have DRM_RENDER_ALLOW (Christian König) - Asynchronous display power disabling (Imre) - Perma-pin uC firmware and re-enable global reset (Fernando) - GTT remapping for display, for bigger fb size and stride (Ville) - Enable pipe HDR mode on ICL if only HDR planes are used (Ville) - Kconfig to tweak the busyspin durations for i915_wait_request (Chris) - Allow multiple user handles to the same VM (Chris) - GT/GEM runtime pm improvements using wakerefs (Chris) - Gen 4&5 render context support (Chris) - Allow userspace to clone contexts on creation (Chris) - SINGLE_TIMELINE flags for context creation (Chris) - Allow specification of parallel execbuf (Chris) Refactoring: - Header refactoring (Jani) - Move GraphicsTechnology files under gt/ (Chris) - Sideband code refactoring (Chris) Fixes: - ICL DSI state readout and checker fixes (Vandita) - GLK DSI picture corruption fix (Stanislav) - HDMI deep color fixes (Clinton, Aditya) - Fix driver unbinding from a device in use (Janusz) - Fix clock gating with pipe scaling (Radhakrishna) - Disable broken FBC on GLK (Daniel Drake) - Miscellaneous GuC fixes (Michal) - Fix MG PHY DP register programming (Imre) - Add missing combo PHY lane power setup (Imre) - Workarounds for early ICL VBT issues (Imre) - Fix fastset vs. pfit on/off on HSW EDP transcoder (Ville) - Add readout and state check for pch_pfit.force_thru (Ville) - Miscellaneous display fixes and refactoring (Ville) - Display workaround fixes (Ville) - Enable audio even if ELD is bogus (Ville) - Fix use-after-free in reporting create.size (Chris) - Sideband fixes to avoid BYT hard lockups (Chris) - Workaround fixes and improvements (Chris) Maintainer shortcomings: - Failure to adequately describe and give credit for all changes (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 7 years ago

Commit 14ee6422 parents 88cd7a2 c0a74c7218 files · +11483 −5022Browse files

Showing the changes to include/uapi (1 of 218 files). Show all

Unified · Split

include/uapi/drm/i915_drm.h+206−3
@@ -136,6 +136,8 @@ enum drm_i915_gem_engine_class { · 135 unmodified lines
136struct i915_engine_class_instance {136struct i915_engine_class_instance {
137 __u16 engine_class; /* see enum drm_i915_gem_engine_class */137 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
138 __u16 engine_instance;138 __u16 engine_instance;
139#define I915_ENGINE_CLASS_INVALID_NONE -1
140#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
139};141};
140 142
141/**143/**
@@ -355,6 +357,8 @@ typedef struct _drm_i915_sarea { · 213 unmodified lines
355#define DRM_I915_PERF_ADD_CONFIG 0x37357#define DRM_I915_PERF_ADD_CONFIG 0x37
356#define DRM_I915_PERF_REMOVE_CONFIG 0x38358#define DRM_I915_PERF_REMOVE_CONFIG 0x38
357#define DRM_I915_QUERY 0x39359#define DRM_I915_QUERY 0x39
360#define DRM_I915_GEM_VM_CREATE 0x3a
361#define DRM_I915_GEM_VM_DESTROY 0x3b
358/* Must be kept compact -- no holes */362/* Must be kept compact -- no holes */
359 363
360#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)364#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -415,6 +419,8 @@ typedef struct _drm_i915_sarea { · 54 unmodified lines
415#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)419#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
416#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)420#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
417#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)421#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
422#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
423#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
418 424
419/* Allow drivers to submit batchbuffers directly to hardware, relying425/* Allow drivers to submit batchbuffers directly to hardware, relying
420 * on the security mechanisms provided by hardware.426 * on the security mechanisms provided by hardware.
@@ -598,6 +604,12 @@ typedef struct drm_i915_irq_wait { · 177 unmodified lines
598 */604 */
599#define I915_PARAM_MMAP_GTT_COHERENT 52605#define I915_PARAM_MMAP_GTT_COHERENT 52
600 606
607/*
608 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
609 * execution through use of explicit fence support.
610 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
611 */
612#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
601/* Must be kept compact -- no holes and well documented */613/* Must be kept compact -- no holes and well documented */
602 614
603typedef struct drm_i915_getparam {615typedef struct drm_i915_getparam {
@@ -1120,7 +1132,16 @@ struct drm_i915_gem_execbuffer2 { · 516 unmodified lines
1120 */1132 */
1121#define I915_EXEC_FENCE_ARRAY (1<<19)1133#define I915_EXEC_FENCE_ARRAY (1<<19)
1122 1134
1123#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))1135/*
1136 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1137 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1138 * the batch.
1139 *
1140 * Returns -EINVAL if the sync_file fd cannot be found.
1141 */
1142#define I915_EXEC_FENCE_SUBMIT (1 << 20)
1143
1144#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
1124 1145
1125#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)1146#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1126#define i915_execbuffer2_set_context_id(eb2, context) \1147#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1464,8 +1485,9 @@ struct drm_i915_gem_context_create_ext { · 337 unmodified lines
1464 __u32 ctx_id; /* output: id of new context*/1485 __u32 ctx_id; /* output: id of new context*/
1465 __u32 flags;1486 __u32 flags;
1466#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)1487#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1488#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1467#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \1489#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1468 (-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))1490 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1469 __u64 extensions;1491 __u64 extensions;
1470};1492};
1471 1493
@@ -1507,6 +1529,41 @@ struct drm_i915_gem_context_param { · 35 unmodified lines
1507 * On creation, all new contexts are marked as recoverable.1529 * On creation, all new contexts are marked as recoverable.
1508 */1530 */
1509#define I915_CONTEXT_PARAM_RECOVERABLE 0x81531#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1532
1533 /*
1534 * The id of the associated virtual memory address space (ppGTT) of
1535 * this context. Can be retrieved and passed to another context
1536 * (on the same fd) for both to use the same ppGTT and so share
1537 * address layouts, and avoid reloading the page tables on context
1538 * switches between themselves.
1539 *
1540 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1541 */
1542#define I915_CONTEXT_PARAM_VM 0x9
1543
1544/*
1545 * I915_CONTEXT_PARAM_ENGINES:
1546 *
1547 * Bind this context to operate on this subset of available engines. Henceforth,
1548 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1549 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1550 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1551 * Use
1552 * engine_class: I915_ENGINE_CLASS_INVALID,
1553 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1554 * to specify a gap in the array that can be filled in later, e.g. by a
1555 * virtual engine used for load balancing.
1556 *
1557 * Setting the number of engines bound to the context to 0, by passing a zero
1558 * sized argument, will revert back to default settings.
1559 *
1560 * See struct i915_context_param_engines.
1561 *
1562 * Extensions:
1563 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1564 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1565 */
1566#define I915_CONTEXT_PARAM_ENGINES 0xa
1510/* Must be kept compact -- no holes and well documented */1567/* Must be kept compact -- no holes and well documented */
1511 1568
1512 __u64 value;1569 __u64 value;
@@ -1540,9 +1597,10 @@ struct drm_i915_gem_context_param_sseu { · 27 unmodified lines
1540 struct i915_engine_class_instance engine;1597 struct i915_engine_class_instance engine;
1541 1598
1542 /*1599 /*
1543 * Unused for now. Must be cleared to zero.1600 * Unknown flags must be cleared to zero.
1544 */1601 */
1545 __u32 flags;1602 __u32 flags;
1603#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1546 1604
1547 /*1605 /*
1548 * Mask of slices to enable for the context. Valid values are a subset1606 * Mask of slices to enable for the context. Valid values are a subset
@@ -1570,12 +1628,115 @@ struct drm_i915_gem_context_param_sseu { · 21 unmodified lines
1570 __u32 rsvd;1628 __u32 rsvd;
1571};1629};
1572 1630
1631/*
1632 * i915_context_engines_load_balance:
1633 *
1634 * Enable load balancing across this set of engines.
1635 *
1636 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1637 * used will proxy the execbuffer request onto one of the set of engines
1638 * in such a way as to distribute the load evenly across the set.
1639 *
1640 * The set of engines must be compatible (e.g. the same HW class) as they
1641 * will share the same logical GPU context and ring.
1642 *
1643 * To intermix rendering with the virtual engine and direct rendering onto
1644 * the backing engines (bypassing the load balancing proxy), the context must
1645 * be defined to use a single timeline for all engines.
1646 */
1647struct i915_context_engines_load_balance {
1648 struct i915_user_extension base;
1649
1650 __u16 engine_index;
1651 __u16 num_siblings;
1652 __u32 flags; /* all undefined flags must be zero */
1653
1654 __u64 mbz64; /* reserved for future use; must be zero */
1655
1656 struct i915_engine_class_instance engines[0];
1657} __attribute__((packed));
1658
1659#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1660 struct i915_user_extension base; \
1661 __u16 engine_index; \
1662 __u16 num_siblings; \
1663 __u32 flags; \
1664 __u64 mbz64; \
1665 struct i915_engine_class_instance engines[N__]; \
1666} __attribute__((packed)) name__
1667
1668/*
1669 * i915_context_engines_bond:
1670 *
1671 * Constructed bonded pairs for execution within a virtual engine.
1672 *
1673 * All engines are equal, but some are more equal than others. Given
1674 * the distribution of resources in the HW, it may be preferable to run
1675 * a request on a given subset of engines in parallel to a request on a
1676 * specific engine. We enable this selection of engines within a virtual
1677 * engine by specifying bonding pairs, for any given master engine we will
1678 * only execute on one of the corresponding siblings within the virtual engine.
1679 *
1680 * To execute a request in parallel on the master engine and a sibling requires
1681 * coordination with a I915_EXEC_FENCE_SUBMIT.
1682 */
1683struct i915_context_engines_bond {
1684 struct i915_user_extension base;
1685
1686 struct i915_engine_class_instance master;
1687
1688 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
1689 __u16 num_bonds;
1690
1691 __u64 flags; /* all undefined flags must be zero */
1692 __u64 mbz64[4]; /* reserved for future use; must be zero */
1693
1694 struct i915_engine_class_instance engines[0];
1695} __attribute__((packed));
1696
1697#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1698 struct i915_user_extension base; \
1699 struct i915_engine_class_instance master; \
1700 __u16 virtual_index; \
1701 __u16 num_bonds; \
1702 __u64 flags; \
1703 __u64 mbz64[4]; \
1704 struct i915_engine_class_instance engines[N__]; \
1705} __attribute__((packed)) name__
1706
1707struct i915_context_param_engines {
1708 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
1709#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1710#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1711 struct i915_engine_class_instance engines[0];
1712} __attribute__((packed));
1713
1714#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1715 __u64 extensions; \
1716 struct i915_engine_class_instance engines[N__]; \
1717} __attribute__((packed)) name__
1718
1573struct drm_i915_gem_context_create_ext_setparam {1719struct drm_i915_gem_context_create_ext_setparam {
1574#define I915_CONTEXT_CREATE_EXT_SETPARAM 01720#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1575 struct i915_user_extension base;1721 struct i915_user_extension base;
1576 struct drm_i915_gem_context_param param;1722 struct drm_i915_gem_context_param param;
1577};1723};
1578 1724
1725struct drm_i915_gem_context_create_ext_clone {
1726#define I915_CONTEXT_CREATE_EXT_CLONE 1
1727 struct i915_user_extension base;
1728 __u32 clone_id;
1729 __u32 flags;
1730#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1731#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1732#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1733#define I915_CONTEXT_CLONE_SSEU (1u << 3)
1734#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1735#define I915_CONTEXT_CLONE_VM (1u << 5)
1736#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1737 __u64 rsvd;
1738};
1739
1579struct drm_i915_gem_context_destroy {1740struct drm_i915_gem_context_destroy {
1580 __u32 ctx_id;1741 __u32 ctx_id;
1581 __u32 pad;1742 __u32 pad;
@@ -1821,6 +1982,7 @@ struct drm_i915_perf_oa_config { · 239 unmodified lines
1821struct drm_i915_query_item {1982struct drm_i915_query_item {
1822 __u64 query_id;1983 __u64 query_id;
1823#define DRM_I915_QUERY_TOPOLOGY_INFO 11984#define DRM_I915_QUERY_TOPOLOGY_INFO 1
1985#define DRM_I915_QUERY_ENGINE_INFO 2
1824/* Must be kept compact -- no holes and well documented */1986/* Must be kept compact -- no holes and well documented */
1825 1987
1826 /*1988 /*
@@ -1919,6 +2081,47 @@ struct drm_i915_query_topology_info { · 92 unmodified lines
1919 __u8 data[];2081 __u8 data[];
1920};2082};
1921 2083
2084/**
2085 * struct drm_i915_engine_info
2086 *
2087 * Describes one engine and it's capabilities as known to the driver.
2088 */
2089struct drm_i915_engine_info {
2090 /** Engine class and instance. */
2091 struct i915_engine_class_instance engine;
2092
2093 /** Reserved field. */
2094 __u32 rsvd0;
2095
2096 /** Engine flags. */
2097 __u64 flags;
2098
2099 /** Capabilities of this engine. */
2100 __u64 capabilities;
2101#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2102#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2103
2104 /** Reserved fields. */
2105 __u64 rsvd1[4];
2106};
2107
2108/**
2109 * struct drm_i915_query_engine_info
2110 *
2111 * Engine info query enumerates all engines known to the driver by filling in
2112 * an array of struct drm_i915_engine_info structures.
2113 */
2114struct drm_i915_query_engine_info {
2115 /** Number of struct drm_i915_engine_info structs following. */
2116 __u32 num_engines;
2117
2118 /** MBZ */
2119 __u32 rsvd[3];
2120
2121 /** Marker for drm_i915_engine_info structures. */
2122 struct drm_i915_engine_info engines[];
2123};
2124
1922#if defined(__cplusplus)2125#if defined(__cplusplus)
1923}2126}
1924#endif2127#endif