The fix 5987feb38aa5 ("net: phy: marvell: logical vs bitwise OR typo") uncovered another bug in the Marvell PHY driver, which broke the Marvell OpenRD platform. It relies on the bootloader configuring the RGMII delays and does not specify a phy-mode in its device tree. The PHY driver should only configure RGMII delays if the phy mode indicates it is using RGMII. Without anything in device tree, the mv643xx Ethernet driver defaults to GMII.
Unified · Split
| @@ -681,9 +681,11 @@ static int m88e1116r_config_init(struct phy_device *phydev) · 680 unmodified lines | |||
| 681 | if (err < 0) | 681 | if (err < 0) |
| 682 | return err; | 682 | return err; |
| 683 | 683 | ||
| 684 | err = m88e1121_config_aneg_rgmii_delays(phydev); | 684 | if (phy_interface_is_rgmii(phydev)) { |
| 685 | if (err < 0) | 685 | err = m88e1121_config_aneg_rgmii_delays(phydev); |
| 686 | return err; | 686 | if (err < 0) |
| 687 | return err; | ||
| 688 | } | ||
| 687 | 689 | ||
| 688 | err = genphy_soft_reset(phydev); | 690 | err = genphy_soft_reset(phydev); |
| 689 | if (err < 0) | 691 | if (err < 0) |