History

drm/v3d: Add support for submitting jobs to the TFU.

The TFU can copy from raster, UIF, and SAND input images to UIF output images, with optional mipmap generation. This will certainly be useful for media EGL image input, but is also useful immediately for mipmap generation without bogging the V3D core down. For now we only run the queue 1 job deep, and don't have any hang recovery (though I don't think we should need it, with TFU). Queuing multiple jobs in the HW will require synchronizing the YUV coefficient regs updates since they don't get FIFOed with the job. v2: Change the ioctl to IOW instead of IOWR, always set COEF0, explain why TFU is AUTH, clarify the syncing docs, drop the unused TFU interrupt regs (you're expected to use the hub's), don't take &bo->base for NULL bos. v3: Fix a little whitespace alignment (noticed by checkpatch), rebase on drm_sched_job_cleanup() changes.

Eric Anholt committed 7 years ago

Commit 1584f161 parent 1d8224e8 files · +427 −51Browse files

Unified · Split

8 files
  1. drivers/gpu/drm/v3d/v3d_drv.c +11 −4
  2. drivers/gpu/drm/v3d/v3d_drv.h +27 −5
  3. drivers/gpu/drm/v3d/v3d_gem.c +158 −20
  4. drivers/gpu/drm/v3d/v3d_irq.c +9 −3
  5. drivers/gpu/drm/v3d/v3d_regs.h +49 −0
  6. drivers/gpu/drm/v3d/v3d_sched.c +128 −19
  7. drivers/gpu/drm/v3d/v3d_trace.h +20 −0
  8. include/uapi/drm/v3d_drm.h +25 −0
drivers/gpu/drm/v3d/v3d_drv.c+11−4
@@ -112,10 +112,15 @@ static int v3d_get_param_ioctl(struct drm_device *dev, void *data, · 111 unmodified lines
112 return 0;112 return 0;
113 }113 }
114 114
115 /* Any params that aren't just register reads would go here. */
116 115
117 DRM_DEBUG("Unknown parameter %d\n", args->param);116 switch (args->param) {
118 return -EINVAL;117 case DRM_V3D_PARAM_SUPPORTS_TFU:
118 args->value = 1;
119 return 0;
120 default:
121 DRM_DEBUG("Unknown parameter %d\n", args->param);
122 return -EINVAL;
123 }
119}124}
120 125
121static int126static int
@@ -170,7 +175,8 @@ static const struct file_operations v3d_drm_fops = { · 48 unmodified lines
170/* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP175/* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
171 * protection between clients. Note that render nodes would be be176 * protection between clients. Note that render nodes would be be
172 * able to submit CLs that could access BOs from clients authenticated177 * able to submit CLs that could access BOs from clients authenticated
173 * with the master node.178 * with the master node. The TFU doesn't use the GMP, so it would
179 * need to stay DRM_AUTH until we do buffer size/offset validation.
174 */180 */
175static const struct drm_ioctl_desc v3d_drm_ioctls[] = {181static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
176 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),182 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
@@ -179,6 +185,7 @@ static const struct drm_ioctl_desc v3d_drm_ioctls[] = { · 2 unmodified lines
179 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),185 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
180 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),186 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
181 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),187 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
188 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
182};189};
183 190
184static const struct vm_operations_struct v3d_vm_ops = {191static const struct vm_operations_struct v3d_vm_ops = {
drivers/gpu/drm/v3d/v3d_drv.h+27−5
@@ -7,19 +7,18 @@ · 6 unmodified lines
7#include <drm/drm_encoder.h>7#include <drm/drm_encoder.h>
8#include <drm/drm_gem.h>8#include <drm/drm_gem.h>
9#include <drm/gpu_scheduler.h>9#include <drm/gpu_scheduler.h>
10#include "uapi/drm/v3d_drm.h"
10 11
11#define GMP_GRANULARITY (128 * 1024)12#define GMP_GRANULARITY (128 * 1024)
12 13
13/* Enum for each of the V3D queues. We maintain various queue14/* Enum for each of the V3D queues. */
14 * tracking as an array because at some point we'll want to support
15 * the TFU (texture formatting unit) as another queue.
16 */
17enum v3d_queue {15enum v3d_queue {
18 V3D_BIN,16 V3D_BIN,
19 V3D_RENDER,17 V3D_RENDER,
18 V3D_TFU,
20};19};
21 20
22#define V3D_MAX_QUEUES (V3D_RENDER + 1)21#define V3D_MAX_QUEUES (V3D_TFU + 1)
23 22
24struct v3d_queue_state {23struct v3d_queue_state {
25 struct drm_gpu_scheduler sched;24 struct drm_gpu_scheduler sched;
@@ -68,6 +67,7 @@ struct v3d_dev { · 42 unmodified lines
68 67
69 struct v3d_exec_info *bin_job;68 struct v3d_exec_info *bin_job;
70 struct v3d_exec_info *render_job;69 struct v3d_exec_info *render_job;
70 struct v3d_tfu_job *tfu_job;
71 71
72 struct v3d_queue_state queue[V3D_MAX_QUEUES];72 struct v3d_queue_state queue[V3D_MAX_QUEUES];
73 73
@@ -218,6 +218,25 @@ struct v3d_exec_info { · 144 unmodified lines
218 u32 qma, qms, qts;218 u32 qma, qms, qts;
219};219};
220 220
221struct v3d_tfu_job {
222 struct drm_sched_job base;
223
224 struct drm_v3d_submit_tfu args;
225
226 /* An optional fence userspace can pass in for the job to depend on. */
227 struct dma_fence *in_fence;
228
229 /* v3d fence to be signaled by IRQ handler when the job is complete. */
230 struct dma_fence *done_fence;
231
232 struct v3d_dev *v3d;
233
234 struct kref refcount;
235
236 /* This is the array of BOs that were looked up at the start of exec. */
237 struct v3d_bo *bo[4];
238};
239
221/**240/**
222 * _wait_for - magic (register) wait macro241 * _wait_for - magic (register) wait macro
223 *242 *
@@ -281,9 +300,12 @@ int v3d_gem_init(struct drm_device *dev); · 57 unmodified lines
281void v3d_gem_destroy(struct drm_device *dev);300void v3d_gem_destroy(struct drm_device *dev);
282int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,301int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
283 struct drm_file *file_priv);302 struct drm_file *file_priv);
303int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
304 struct drm_file *file_priv);
284int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,305int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
285 struct drm_file *file_priv);306 struct drm_file *file_priv);
286void v3d_exec_put(struct v3d_exec_info *exec);307void v3d_exec_put(struct v3d_exec_info *exec);
308void v3d_tfu_job_put(struct v3d_tfu_job *exec);
287void v3d_reset(struct v3d_dev *v3d);309void v3d_reset(struct v3d_dev *v3d);
288void v3d_invalidate_caches(struct v3d_dev *v3d);310void v3d_invalidate_caches(struct v3d_dev *v3d);
289void v3d_flush_caches(struct v3d_dev *v3d);311void v3d_flush_caches(struct v3d_dev *v3d);
drivers/gpu/drm/v3d/v3d_gem.c+158−20
@@ -207,26 +207,27 @@ v3d_flush_caches(struct v3d_dev *v3d) · 206 unmodified lines
207}207}
208 208
209static void209static void
210v3d_attach_object_fences(struct v3d_exec_info *exec)210v3d_attach_object_fences(struct v3d_bo **bos, int bo_count,
211 struct dma_fence *fence)
211{212{
212 struct dma_fence *out_fence = exec->render_done_fence;
213 int i;213 int i;
214 214
215 for (i = 0; i < exec->bo_count; i++) {215 for (i = 0; i < bo_count; i++) {
216 /* XXX: Use shared fences for read-only objects. */216 /* XXX: Use shared fences for read-only objects. */
217 reservation_object_add_excl_fence(exec->bo[i]->resv, out_fence);217 reservation_object_add_excl_fence(bos[i]->resv, fence);
218 }218 }
219}219}
220 220
221static void221static void
222v3d_unlock_bo_reservations(struct drm_device *dev,222v3d_unlock_bo_reservations(struct drm_device *dev,
223 struct v3d_exec_info *exec,223 struct v3d_bo **bos,
224 int bo_count,
224 struct ww_acquire_ctx *acquire_ctx)225 struct ww_acquire_ctx *acquire_ctx)
225{226{
226 int i;227 int i;
227 228
228 for (i = 0; i < exec->bo_count; i++)229 for (i = 0; i < bo_count; i++)
229 ww_mutex_unlock(&exec->bo[i]->resv->lock);230 ww_mutex_unlock(&bos[i]->resv->lock);
230 231
231 ww_acquire_fini(acquire_ctx);232 ww_acquire_fini(acquire_ctx);
232}233}
@@ -240,7 +241,8 @@ v3d_unlock_bo_reservations(struct drm_device *dev, · 7 unmodified lines
240 */241 */
241static int242static int
242v3d_lock_bo_reservations(struct drm_device *dev,243v3d_lock_bo_reservations(struct drm_device *dev,
243 struct v3d_exec_info *exec,244 struct v3d_bo **bos,
245 int bo_count,
244 struct ww_acquire_ctx *acquire_ctx)246 struct ww_acquire_ctx *acquire_ctx)
245{247{
246 int contended_lock = -1;248 int contended_lock = -1;
@@ -250,7 +252,7 @@ v3d_lock_bo_reservations(struct drm_device *dev, · 3 unmodified lines
250 252
251retry:253retry:
252 if (contended_lock != -1) {254 if (contended_lock != -1) {
253 struct v3d_bo *bo = exec->bo[contended_lock];255 struct v3d_bo *bo = bos[contended_lock];
254 256
255 ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,257 ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,
256 acquire_ctx);258 acquire_ctx);
@@ -260,20 +262,20 @@ retry: · 3 unmodified lines
260 }262 }
261 }263 }
262 264
263 for (i = 0; i < exec->bo_count; i++) {265 for (i = 0; i < bo_count; i++) {
264 if (i == contended_lock)266 if (i == contended_lock)
265 continue;267 continue;
266 268
267 ret = ww_mutex_lock_interruptible(&exec->bo[i]->resv->lock,269 ret = ww_mutex_lock_interruptible(&bos[i]->resv->lock,
268 acquire_ctx);270 acquire_ctx);
269 if (ret) {271 if (ret) {
270 int j;272 int j;
271 273
272 for (j = 0; j < i; j++)274 for (j = 0; j < i; j++)
273 ww_mutex_unlock(&exec->bo[j]->resv->lock);275 ww_mutex_unlock(&bos[j]->resv->lock);
274 276
275 if (contended_lock != -1 && contended_lock >= i) {277 if (contended_lock != -1 && contended_lock >= i) {
276 struct v3d_bo *bo = exec->bo[contended_lock];278 struct v3d_bo *bo = bos[contended_lock];
277 279
278 ww_mutex_unlock(&bo->resv->lock);280 ww_mutex_unlock(&bo->resv->lock);
279 }281 }
@@ -293,10 +295,11 @@ retry: · 13 unmodified lines
293 /* Reserve space for our shared (read-only) fence references,295 /* Reserve space for our shared (read-only) fence references,
294 * before we commit the CL to the hardware.296 * before we commit the CL to the hardware.
295 */297 */
296 for (i = 0; i < exec->bo_count; i++) {298 for (i = 0; i < bo_count; i++) {
297 ret = reservation_object_reserve_shared(exec->bo[i]->resv, 1);299 ret = reservation_object_reserve_shared(bos[i]->resv, 1);
298 if (ret) {300 if (ret) {
299 v3d_unlock_bo_reservations(dev, exec, acquire_ctx);301 v3d_unlock_bo_reservations(dev, bos, bo_count,
302 acquire_ctx);
300 return ret;303 return ret;
301 }304 }
302 }305 }
@@ -419,6 +422,33 @@ void v3d_exec_put(struct v3d_exec_info *exec) · 116 unmodified lines
419 kref_put(&exec->refcount, v3d_exec_cleanup);422 kref_put(&exec->refcount, v3d_exec_cleanup);
420}423}
421 424
425static void
426v3d_tfu_job_cleanup(struct kref *ref)
427{
428 struct v3d_tfu_job *job = container_of(ref, struct v3d_tfu_job,
429 refcount);
430 struct v3d_dev *v3d = job->v3d;
431 unsigned int i;
432
433 dma_fence_put(job->in_fence);
434 dma_fence_put(job->done_fence);
435
436 for (i = 0; i < ARRAY_SIZE(job->bo); i++) {
437 if (job->bo[i])
438 drm_gem_object_put_unlocked(&job->bo[i]->base);
439 }
440
441 pm_runtime_mark_last_busy(v3d->dev);
442 pm_runtime_put_autosuspend(v3d->dev);
443
444 kfree(job);
445}
446
447void v3d_tfu_job_put(struct v3d_tfu_job *job)
448{
449 kref_put(&job->refcount, v3d_tfu_job_cleanup);
450}
451
422int452int
423v3d_wait_bo_ioctl(struct drm_device *dev, void *data,453v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
424 struct drm_file *file_priv)454 struct drm_file *file_priv)
@@ -536,7 +566,8 @@ v3d_submit_cl_ioctl(struct drm_device *dev, void *data, · 111 unmodified lines
536 if (ret)566 if (ret)
537 goto fail;567 goto fail;
538 568
539 ret = v3d_lock_bo_reservations(dev, exec, &acquire_ctx);569 ret = v3d_lock_bo_reservations(dev, exec->bo, exec->bo_count,
570 &acquire_ctx);
540 if (ret)571 if (ret)
541 goto fail;572 goto fail;
542 573
@@ -570,9 +601,10 @@ v3d_submit_cl_ioctl(struct drm_device *dev, void *data, · 27 unmodified lines
570 &v3d_priv->sched_entity[V3D_RENDER]);601 &v3d_priv->sched_entity[V3D_RENDER]);
571 mutex_unlock(&v3d->sched_lock);602 mutex_unlock(&v3d->sched_lock);
572 603
573 v3d_attach_object_fences(exec);604 v3d_attach_object_fences(exec->bo, exec->bo_count,
605 exec->render_done_fence);
574 606
575 v3d_unlock_bo_reservations(dev, exec, &acquire_ctx);607 v3d_unlock_bo_reservations(dev, exec->bo, exec->bo_count, &acquire_ctx);
576 608
577 /* Update the return sync object for the */609 /* Update the return sync object for the */
578 sync_out = drm_syncobj_find(file_priv, args->out_sync);610 sync_out = drm_syncobj_find(file_priv, args->out_sync);
@@ -588,13 +620,119 @@ v3d_submit_cl_ioctl(struct drm_device *dev, void *data, · 9 unmodified lines
588 620
589fail_unreserve:621fail_unreserve:
590 mutex_unlock(&v3d->sched_lock);622 mutex_unlock(&v3d->sched_lock);
591 v3d_unlock_bo_reservations(dev, exec, &acquire_ctx);623 v3d_unlock_bo_reservations(dev, exec->bo, exec->bo_count, &acquire_ctx);
592fail:624fail:
593 v3d_exec_put(exec);625 v3d_exec_put(exec);
594 626
595 return ret;627 return ret;
596}628}
597 629
630/**
631 * v3d_submit_tfu_ioctl() - Submits a TFU (texture formatting) job to the V3D.
632 * @dev: DRM device
633 * @data: ioctl argument
634 * @file_priv: DRM file for this fd
635 *
636 * Userspace provides the register setup for the TFU, which we don't
637 * need to validate since the TFU is behind the MMU.
638 */
639int
640v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
641 struct drm_file *file_priv)
642{
643 struct v3d_dev *v3d = to_v3d_dev(dev);
644 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
645 struct drm_v3d_submit_tfu *args = data;
646 struct v3d_tfu_job *job;
647 struct ww_acquire_ctx acquire_ctx;
648 struct drm_syncobj *sync_out;
649 struct dma_fence *sched_done_fence;
650 int ret = 0;
651 int bo_count;
652
653 job = kcalloc(1, sizeof(*job), GFP_KERNEL);
654 if (!job)
655 return -ENOMEM;
656
657 ret = pm_runtime_get_sync(v3d->dev);
658 if (ret < 0) {
659 kfree(job);
660 return ret;
661 }
662
663 kref_init(&job->refcount);
664
665 ret = drm_syncobj_find_fence(file_priv, args->in_sync,
666 0, 0, &job->in_fence);
667 if (ret == -EINVAL)
668 goto fail;
669
670 job->args = *args;
671 job->v3d = v3d;
672
673 spin_lock(&file_priv->table_lock);
674 for (bo_count = 0; bo_count < ARRAY_SIZE(job->bo); bo_count++) {
675 struct drm_gem_object *bo;
676
677 if (!args->bo_handles[bo_count])
678 break;
679
680 bo = idr_find(&file_priv->object_idr,
681 args->bo_handles[bo_count]);
682 if (!bo) {
683 DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
684 bo_count, args->bo_handles[bo_count]);
685 ret = -ENOENT;
686 spin_unlock(&file_priv->table_lock);
687 goto fail;
688 }
689 drm_gem_object_get(bo);
690 job->bo[bo_count] = to_v3d_bo(bo);
691 }
692 spin_unlock(&file_priv->table_lock);
693
694 ret = v3d_lock_bo_reservations(dev, job->bo, bo_count, &acquire_ctx);
695 if (ret)
696 goto fail;
697
698 mutex_lock(&v3d->sched_lock);
699 ret = drm_sched_job_init(&job->base,
700 &v3d_priv->sched_entity[V3D_TFU],
701 v3d_priv);
702 if (ret)
703 goto fail_unreserve;
704
705 sched_done_fence = dma_fence_get(&job->base.s_fence->finished);
706
707 kref_get(&job->refcount); /* put by scheduler job completion */
708 drm_sched_entity_push_job(&job->base, &v3d_priv->sched_entity[V3D_TFU]);
709 mutex_unlock(&v3d->sched_lock);
710
711 v3d_attach_object_fences(job->bo, bo_count, sched_done_fence);
712
713 v3d_unlock_bo_reservations(dev, job->bo, bo_count, &acquire_ctx);
714
715 /* Update the return sync object */
716 sync_out = drm_syncobj_find(file_priv, args->out_sync);
717 if (sync_out) {
718 drm_syncobj_replace_fence(sync_out, 0, sched_done_fence);
719 drm_syncobj_put(sync_out);
720 }
721 dma_fence_put(sched_done_fence);
722
723 v3d_tfu_job_put(job);
724
725 return 0;
726
727fail_unreserve:
728 mutex_unlock(&v3d->sched_lock);
729 v3d_unlock_bo_reservations(dev, job->bo, bo_count, &acquire_ctx);
730fail:
731 v3d_tfu_job_put(job);
732
733 return ret;
734}
735
598int736int
599v3d_gem_init(struct drm_device *dev)737v3d_gem_init(struct drm_device *dev)
600{738{
drivers/gpu/drm/v3d/v3d_irq.c+9−3
@@ -4,8 +4,8 @@ · 3 unmodified lines
4/**4/**
5 * DOC: Interrupt management for the V3D engine5 * DOC: Interrupt management for the V3D engine
6 *6 *
7 * When we take a binning or rendering flush done interrupt, we need7 * When we take a bin, render, or TFU done interrupt, we need to
8 * to signal the fence for that job so that the scheduler can queue up8 * signal the fence for that job so that the scheduler can queue up
9 * the next one and unblock any waiters.9 * the next one and unblock any waiters.
10 *10 *
11 * When we take the binner out of memory interrupt, we need to11 * When we take the binner out of memory interrupt, we need to
@@ -23,7 +23,8 @@ · 11 unmodified lines
23 23
24#define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \24#define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \
25 V3D_HUB_INT_MMU_PTI | \25 V3D_HUB_INT_MMU_PTI | \
26 V3D_HUB_INT_MMU_CAP))26 V3D_HUB_INT_MMU_CAP | \
27 V3D_HUB_INT_TFUC))
27 28
28static void29static void
29v3d_overflow_mem_work(struct work_struct *work)30v3d_overflow_mem_work(struct work_struct *work)
@@ -117,6 +118,11 @@ v3d_hub_irq(int irq, void *arg) · 87 unmodified lines
117 /* Acknowledge the interrupts we're handling here. */118 /* Acknowledge the interrupts we're handling here. */
118 V3D_WRITE(V3D_HUB_INT_CLR, intsts);119 V3D_WRITE(V3D_HUB_INT_CLR, intsts);
119 120
121 if (intsts & V3D_HUB_INT_TFUC) {
122 dma_fence_signal(v3d->tfu_job->done_fence);
123 status = IRQ_HANDLED;
124 }
125
120 if (intsts & (V3D_HUB_INT_MMU_WRV |126 if (intsts & (V3D_HUB_INT_MMU_WRV |
121 V3D_HUB_INT_MMU_PTI |127 V3D_HUB_INT_MMU_PTI |
122 V3D_HUB_INT_MMU_CAP)) {128 V3D_HUB_INT_MMU_CAP)) {
drivers/gpu/drm/v3d/v3d_regs.h+49−0
@@ -86,6 +86,55 @@ · 85 unmodified lines
86# define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c86# define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c
87# define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)87# define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
88 88
89#define V3D_TFU_CS 0x00400
90/* Stops current job, empties input fifo. */
91# define V3D_TFU_CS_TFURST BIT(31)
92# define V3D_TFU_CS_CVTCT_MASK V3D_MASK(23, 16)
93# define V3D_TFU_CS_CVTCT_SHIFT 16
94# define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8)
95# define V3D_TFU_CS_NFREE_SHIFT 8
96# define V3D_TFU_CS_BUSY BIT(0)
97
98#define V3D_TFU_SU 0x00404
99/* Interrupt when FINTTHR input slots are free (0 = disabled) */
100# define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8)
101# define V3D_TFU_SU_FINTTHR_SHIFT 8
102/* Skips resetting the CRC at the start of CRC generation. */
103# define V3D_TFU_SU_CRCCHAIN BIT(4)
104/* skips writes, computes CRC of the image. miplevels must be 0. */
105# define V3D_TFU_SU_CRC BIT(3)
106# define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0)
107# define V3D_TFU_SU_THROTTLE_SHIFT 0
108
109#define V3D_TFU_ICFG 0x00408
110/* Interrupt when the conversion is complete. */
111# define V3D_TFU_ICFG_IOC BIT(0)
112
113/* Input Image Address */
114#define V3D_TFU_IIA 0x0040c
115/* Input Chroma Address */
116#define V3D_TFU_ICA 0x00410
117/* Input Image Stride */
118#define V3D_TFU_IIS 0x00414
119/* Input Image U-Plane Address */
120#define V3D_TFU_IUA 0x00418
121/* Output Image Address */
122#define V3D_TFU_IOA 0x0041c
123/* Image Output Size */
124#define V3D_TFU_IOS 0x00420
125/* TFU YUV Coefficient 0 */
126#define V3D_TFU_COEF0 0x00424
127/* Use these regs instead of the defaults. */
128# define V3D_TFU_COEF0_USECOEF BIT(31)
129/* TFU YUV Coefficient 1 */
130#define V3D_TFU_COEF1 0x00428
131/* TFU YUV Coefficient 2 */
132#define V3D_TFU_COEF2 0x0042c
133/* TFU YUV Coefficient 3 */
134#define V3D_TFU_COEF3 0x00430
135
136#define V3D_TFU_CRC 0x00434
137
89/* Per-MMU registers. */138/* Per-MMU registers. */
90 139
91#define V3D_MMUC_CONTROL 0x01000140#define V3D_MMUC_CONTROL 0x01000
drivers/gpu/drm/v3d/v3d_sched.c+128−19
@@ -30,6 +30,12 @@ to_v3d_job(struct drm_sched_job *sched_job) · 29 unmodified lines
30 return container_of(sched_job, struct v3d_job, base);30 return container_of(sched_job, struct v3d_job, base);
31}31}
32 32
33static struct v3d_tfu_job *
34to_tfu_job(struct drm_sched_job *sched_job)
35{
36 return container_of(sched_job, struct v3d_tfu_job, base);
37}
38
33static void39static void
34v3d_job_free(struct drm_sched_job *sched_job)40v3d_job_free(struct drm_sched_job *sched_job)
35{41{
@@ -40,6 +46,16 @@ v3d_job_free(struct drm_sched_job *sched_job) · 4 unmodified lines
40 v3d_exec_put(job->exec);46 v3d_exec_put(job->exec);
41}47}
42 48
49static void
50v3d_tfu_job_free(struct drm_sched_job *sched_job)
51{
52 struct v3d_tfu_job *job = to_tfu_job(sched_job);
53
54 drm_sched_job_cleanup(sched_job);
55
56 v3d_tfu_job_put(job);
57}
58
43/**59/**
44 * Returns the fences that the bin or render job depends on, one by one.60 * Returns the fences that the bin or render job depends on, one by one.
45 * v3d_job_run() won't be called until all of them have been signaled.61 * v3d_job_run() won't be called until all of them have been signaled.
@@ -78,6 +94,27 @@ v3d_job_dependency(struct drm_sched_job *sched_job, · 32 unmodified lines
78 return fence;94 return fence;
79}95}
80 96
97/**
98 * Returns the fences that the TFU job depends on, one by one.
99 * v3d_tfu_job_run() won't be called until all of them have been
100 * signaled.
101 */
102static struct dma_fence *
103v3d_tfu_job_dependency(struct drm_sched_job *sched_job,
104 struct drm_sched_entity *s_entity)
105{
106 struct v3d_tfu_job *job = to_tfu_job(sched_job);
107 struct dma_fence *fence;
108
109 fence = job->in_fence;
110 if (fence) {
111 job->in_fence = NULL;
112 return fence;
113 }
114
115 return NULL;
116}
117
81static struct dma_fence *v3d_job_run(struct drm_sched_job *sched_job)118static struct dma_fence *v3d_job_run(struct drm_sched_job *sched_job)
82{119{
83 struct v3d_job *job = to_v3d_job(sched_job);120 struct v3d_job *job = to_v3d_job(sched_job);
@@ -149,28 +186,47 @@ static struct dma_fence *v3d_job_run(struct drm_sched_job *sched_job) · 65 unmodified lines
149 return fence;186 return fence;
150}187}
151 188
152static void189static struct dma_fence *
153v3d_job_timedout(struct drm_sched_job *sched_job)190v3d_tfu_job_run(struct drm_sched_job *sched_job)
154{191{
155 struct v3d_job *job = to_v3d_job(sched_job);192 struct v3d_tfu_job *job = to_tfu_job(sched_job);
156 struct v3d_exec_info *exec = job->exec;193 struct v3d_dev *v3d = job->v3d;
157 struct v3d_dev *v3d = exec->v3d;194 struct drm_device *dev = &v3d->drm;
158 enum v3d_queue job_q = job == &exec->bin ? V3D_BIN : V3D_RENDER;195 struct dma_fence *fence;
159 enum v3d_queue q;
160 u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
161 u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(job_q));
162 196
163 /* If the current address or return address have changed, then197 fence = v3d_fence_create(v3d, V3D_TFU);
164 * the GPU has probably made progress and we should delay the198 if (IS_ERR(fence))
165 * reset. This could fail if the GPU got in an infinite loop199 return NULL;
166 * in the CL, but that is pretty unlikely outside of an i-g-t200
167 * testcase.201 v3d->tfu_job = job;
168 */202 if (job->done_fence)
169 if (job->timedout_ctca != ctca || job->timedout_ctra != ctra) {203 dma_fence_put(job->done_fence);
170 job->timedout_ctca = ctca;204 job->done_fence = dma_fence_get(fence);
171 job->timedout_ctra = ctra;205
172 return;206 trace_v3d_submit_tfu(dev, to_v3d_fence(fence)->seqno);
207
208 V3D_WRITE(V3D_TFU_IIA, job->args.iia);
209 V3D_WRITE(V3D_TFU_IIS, job->args.iis);
210 V3D_WRITE(V3D_TFU_ICA, job->args.ica);
211 V3D_WRITE(V3D_TFU_IUA, job->args.iua);
212 V3D_WRITE(V3D_TFU_IOA, job->args.ioa);
213 V3D_WRITE(V3D_TFU_IOS, job->args.ios);
214 V3D_WRITE(V3D_TFU_COEF0, job->args.coef[0]);
215 if (job->args.coef[0] & V3D_TFU_COEF0_USECOEF) {
216 V3D_WRITE(V3D_TFU_COEF1, job->args.coef[1]);
217 V3D_WRITE(V3D_TFU_COEF2, job->args.coef[2]);
218 V3D_WRITE(V3D_TFU_COEF3, job->args.coef[3]);
173 }219 }
220 /* ICFG kicks off the job. */
221 V3D_WRITE(V3D_TFU_ICFG, job->args.icfg | V3D_TFU_ICFG_IOC);
222
223 return fence;
224}
225
226static void
227v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
228{
229 enum v3d_queue q;
174 230
175 mutex_lock(&v3d->reset_lock);231 mutex_lock(&v3d->reset_lock);
176 232
@@ -195,6 +251,39 @@ v3d_job_timedout(struct drm_sched_job *sched_job) · 18 unmodified lines
195 mutex_unlock(&v3d->reset_lock);251 mutex_unlock(&v3d->reset_lock);
196}252}
197 253
254static void
255v3d_job_timedout(struct drm_sched_job *sched_job)
256{
257 struct v3d_job *job = to_v3d_job(sched_job);
258 struct v3d_exec_info *exec = job->exec;
259 struct v3d_dev *v3d = exec->v3d;
260 enum v3d_queue job_q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
261 u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(job_q));
262 u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(job_q));
263
264 /* If the current address or return address have changed, then
265 * the GPU has probably made progress and we should delay the
266 * reset. This could fail if the GPU got in an infinite loop
267 * in the CL, but that is pretty unlikely outside of an i-g-t
268 * testcase.
269 */
270 if (job->timedout_ctca != ctca || job->timedout_ctra != ctra) {
271 job->timedout_ctca = ctca;
272 job->timedout_ctra = ctra;
273 return;
274 }
275
276 v3d_gpu_reset_for_timeout(v3d, sched_job);
277}
278
279static void
280v3d_tfu_job_timedout(struct drm_sched_job *sched_job)
281{
282 struct v3d_tfu_job *job = to_tfu_job(sched_job);
283
284 v3d_gpu_reset_for_timeout(job->v3d, sched_job);
285}
286
198static const struct drm_sched_backend_ops v3d_sched_ops = {287static const struct drm_sched_backend_ops v3d_sched_ops = {
199 .dependency = v3d_job_dependency,288 .dependency = v3d_job_dependency,
200 .run_job = v3d_job_run,289 .run_job = v3d_job_run,
@@ -202,6 +291,13 @@ static const struct drm_sched_backend_ops v3d_sched_ops = { · 1 unmodified line
202 .free_job = v3d_job_free291 .free_job = v3d_job_free
203};292};
204 293
294static const struct drm_sched_backend_ops v3d_tfu_sched_ops = {
295 .dependency = v3d_tfu_job_dependency,
296 .run_job = v3d_tfu_job_run,
297 .timedout_job = v3d_tfu_job_timedout,
298 .free_job = v3d_tfu_job_free
299};
300
205int301int
206v3d_sched_init(struct v3d_dev *v3d)302v3d_sched_init(struct v3d_dev *v3d)
207{303{
@@ -232,6 +328,19 @@ v3d_sched_init(struct v3d_dev *v3d) · 24 unmodified lines
232 return ret;328 return ret;
233 }329 }
234 330
331 ret = drm_sched_init(&v3d->queue[V3D_TFU].sched,
332 &v3d_tfu_sched_ops,
333 hw_jobs_limit, job_hang_limit,
334 msecs_to_jiffies(hang_limit_ms),
335 "v3d_tfu");
336 if (ret) {
337 dev_err(v3d->dev, "Failed to create TFU scheduler: %d.",
338 ret);
339 drm_sched_fini(&v3d->queue[V3D_RENDER].sched);
340 drm_sched_fini(&v3d->queue[V3D_BIN].sched);
341 return ret;
342 }
343
235 return 0;344 return 0;
236}345}
237 346
drivers/gpu/drm/v3d/v3d_trace.h+20−0
@@ -42,6 +42,26 @@ TRACE_EVENT(v3d_submit_cl, · 41 unmodified lines
42 __entry->ctnqea)42 __entry->ctnqea)
43);43);
44 44
45TRACE_EVENT(v3d_submit_tfu,
46 TP_PROTO(struct drm_device *dev,
47 uint64_t seqno),
48 TP_ARGS(dev, seqno),
49
50 TP_STRUCT__entry(
51 __field(u32, dev)
52 __field(u64, seqno)
53 ),
54
55 TP_fast_assign(
56 __entry->dev = dev->primary->index;
57 __entry->seqno = seqno;
58 ),
59
60 TP_printk("dev=%u, seqno=%llu",
61 __entry->dev,
62 __entry->seqno)
63);
64
45TRACE_EVENT(v3d_reset_begin,65TRACE_EVENT(v3d_reset_begin,
46 TP_PROTO(struct drm_device *dev),66 TP_PROTO(struct drm_device *dev),
47 TP_ARGS(dev),67 TP_ARGS(dev),
include/uapi/drm/v3d_drm.h+25−0
@@ -36,6 +36,7 @@ extern "C" { · 35 unmodified lines
36#define DRM_V3D_MMAP_BO 0x0336#define DRM_V3D_MMAP_BO 0x03
37#define DRM_V3D_GET_PARAM 0x0437#define DRM_V3D_GET_PARAM 0x04
38#define DRM_V3D_GET_BO_OFFSET 0x0538#define DRM_V3D_GET_BO_OFFSET 0x05
39#define DRM_V3D_SUBMIT_TFU 0x06
39 40
40#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)41#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
41#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)42#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -43,6 +44,7 @@ extern "C" { · 1 unmodified line
43#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)44#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
44#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)45#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
45#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)46#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
47#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
46 48
47/**49/**
48 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D50 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
@@ -179,6 +181,7 @@ enum drm_v3d_param { · 130 unmodified lines
179 DRM_V3D_PARAM_V3D_CORE0_IDENT0,181 DRM_V3D_PARAM_V3D_CORE0_IDENT0,
180 DRM_V3D_PARAM_V3D_CORE0_IDENT1,182 DRM_V3D_PARAM_V3D_CORE0_IDENT1,
181 DRM_V3D_PARAM_V3D_CORE0_IDENT2,183 DRM_V3D_PARAM_V3D_CORE0_IDENT2,
184 DRM_V3D_PARAM_SUPPORTS_TFU,
182};185};
183 186
184struct drm_v3d_get_param {187struct drm_v3d_get_param {
@@ -197,6 +200,28 @@ struct drm_v3d_get_bo_offset { · 12 unmodified lines
197 __u32 offset;200 __u32 offset;
198};201};
199 202
203struct drm_v3d_submit_tfu {
204 __u32 icfg;
205 __u32 iia;
206 __u32 iis;
207 __u32 ica;
208 __u32 iua;
209 __u32 ioa;
210 __u32 ios;
211 __u32 coef[4];
212 /* First handle is the output BO, following are other inputs.
213 * 0 for unused.
214 */
215 __u32 bo_handles[4];
216 /* sync object to block on before running the TFU job. Each TFU
217 * job will execute in the order submitted to its FD. Synchronization
218 * against rendering jobs requires using sync objects.
219 */
220 __u32 in_sync;
221 /* Sync object to signal when the TFU job is done. */
222 __u32 out_sync;
223};
224
200#if defined(__cplusplus)225#if defined(__cplusplus)
201}226}
202#endif227#endif

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