Problem: perf did not show branch predicted/mispredicted bit in brstack. Output of perf -F brstack for profile collected Before: 0x4fdbcd/0x4fdc03/-/-/-/0 0x45f4c1/0x4fdba0/-/-/-/0 0x45f544/0x45f4bb/-/-/-/0 0x45f555/0x45f53c/-/-/-/0 0x7f66901cc24b/0x45f555/-/-/-/0 0x7f66901cc22e/0x7f66901cc23d/-/-/-/0 0x7f66901cc1ff/0x7f66901cc20f/-/-/-/0 0x7f66901cc1e8/0x7f66901cc1fc/-/-/-/0 After: 0x4fdbcd/0x4fdc03/P/-/-/0 0x45f4c1/0x4fdba0/P/-/-/0 0x45f544/0x45f4bb/P/-/-/0 0x45f555/0x45f53c/P/-/-/0 0x7f66901cc24b/0x45f555/P/-/-/0 0x7f66901cc22e/0x7f66901cc23d/P/-/-/0 0x7f66901cc1ff/0x7f66901cc20f/P/-/-/0 0x7f66901cc1e8/0x7f66901cc1fc/P/-/-/0 Cause: As mentioned in Software Development Manual vol 3, 17.4.8.1, IA32_PERF_CAPABILITIES[5:0] indicates the format of the address that is stored in the LBR stack. Knights Landing reports 1 (LBR_FORMAT_LIP) as its format. Despite that, registers containing FROM address of the branch, do have MISPREDICT bit but because of the format indicated in IA32_PERF_CAPABILITIES[5:0], LBR did not read MISPREDICT bit. Solution: Teach LBR about above Knights Landing quirk and make it read MISPREDICT bit.
Unified · Split
| @@ -1272,4 +1272,8 @@ void intel_pmu_lbr_init_knl(void) · 1271 unmodified lines | ||
| 1272 | 1272 | |
| 1273 | 1273 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; |
| 1274 | 1274 | x86_pmu.lbr_sel_map = snb_lbr_sel_map; |
| 1275 | + | |
| 1276 | + /* Knights Landing does have MISPREDICT bit */ | |
| 1277 | + if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP) | |
| 1278 | + x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS; | |
| 1275 | 1279 | } |