Merge tag 'drm-fixes-2023-06-17' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "A bunch of misc fixes across the board. amdgpu is the usual bulk with a revert and other fixes, nouveau has a race fix that was causing a UAF that was hard hanging systems, otherwise some qaic, bridge and radeon. amdgpu: - GFX9 preemption fixes - Add missing radeon secondary PCI ID - vblflash fixes - SMU 13 fix - VCN 4.0 fix - Re-enable TOPDOWN flag for large BAR systems to fix regression - eDP fix - PSR hang fix - DPIA fix radeon: - fbdev client warning fix qaic: - leak fix - null ptr deref fix nouveau: - use-after-free caused by fence race fix - runtime pm fix - NULL ptr checks bridge: - ti-sn65dsi86: Avoid possible buffer overflow" * tag 'drm-fixes-2023-06-17' of git://anongit.freedesktop.org/drm/drm: (21 commits) nouveau: fix client work fence deletion race drm/amd/display: limit DPIA link rate to HBR3 drm/amd/display: fix the system hang while disable PSR drm/amd/display: edp do not add non-edid timings Revert "drm/amdgpu: remove TOPDOWN flags when allocating VRAM in large bar system" drm/amdgpu: vcn_4_0 set instance 0 init sched score to 1 drm/radeon: Disable outputs when releasing fbdev client drm/amd/pm: workaround for compute workload type on some skus drm/amd: Tighten permissions on VBIOS flashing attributes drm/amd: Make sure image is written to trigger VBIOS image update flow drm/amdgpu: add missing radeon secondary PCI ID drm/amdgpu: Implement gfx9 patch functions for resubmission drm/amdgpu: Modify indirect buffer packages for resubmission drm/amdgpu: Program gds backup address as zero if no gds allocated drm/nouveau: add nv_encoder pointer check for NULL drm/amdgpu: Reset CP_VMID_PREEMPT after trailing fence signaled drm/nouveau/dp: check for NULL nv_connector->native_mode drm/bridge: ti-sn65dsi86: Avoid possible buffer overflow drm/nouveau: don't detect DSM for non-NVIDIA device accel/qaic: Fix NULL pointer deref in qaic_destroy_drm_device() ...

Linus Torvalds committed 3 years ago

Commit 1639fae2 parents ba00b19 9930f5118 files · +281 −27Browse files

Unified · Split

18 files

drivers/accel/qaic/qaic_drv.c +4 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +5 −2
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +18 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +9 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c +60 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h +15 −0
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +92 −9
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +5 −1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +13 −5
drivers/gpu/drm/amd/display/dc/link/link_detection.c +5 −0
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +31 −2
drivers/gpu/drm/bridge/ti-sn65dsi86.c +4 −0
drivers/gpu/drm/nouveau/nouveau_acpi.c +3 −0
drivers/gpu/drm/nouveau/nouveau_connector.c +4 −3
drivers/gpu/drm/nouveau/nouveau_drm.c +10 −4
drivers/gpu/drm/radeon/radeon_fbdev.c +1 −0

drivers/accel/qaic/qaic_drv.c+4−0

@@ -97,6 +97,7 @@ static int qaic_open(struct drm_device dev, struct drm_file file) · 96 unmodified lines
97	97
98	98	cleanup_usr:
99	99	cleanup_srcu_struct(&usr->qddev_lock);
	100	+ ida_free(&qaic_usrs, usr->handle);
100	101	free_usr:
101	102	kfree(usr);
102	103	dev_unlock:
@@ -224,6 +225,9 @@ static void qaic_destroy_drm_device(struct qaic_device *qdev, s32 partition_id) · 121 unmodified lines
224	225	struct qaic_user *usr;
225	226
226	227	qddev = qdev->qddev;
	228	+ qdev->qddev = NULL;
	229	+ if (!qddev)
	230	+ return;
227	231
228	232	/*
229	233	* Existing users get unresolvable errors till they close FDs.

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+1−0

@@ -1615,6 +1615,7 @@ static const u16 amdgpu_unsupported_pciidlist[] = { · 1614 unmodified lines
1615	1615	0x5874,
1616	1616	0x5940,
1617	1617	0x5941,
	1618	+ 0x5b70,
1618	1619	0x5b72,
1619	1620	0x5b73,
1620	1621	0x5b74,

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+1−1

@@ -140,7 +140,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) · 139 unmodified lines
140	140
141	141	if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
142	142	places[c].lpfn = visible_pfn;
143		− else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size)
	143	+ else
144	144	places[c].flags \|= TTM_PL_FLAG_TOPDOWN;
145	145
146	146	if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+5−2

@@ -3548,6 +3548,9 @@ static ssize_t amdgpu_psp_vbflash_read(struct file filp, struct kobject kobj, · 3547 unmodified lines
3548	3548	void *fw_pri_cpu_addr;
3549	3549	int ret;
3550	3550
	3551	+ if (adev->psp.vbflash_image_size == 0)
	3552	+ return -EINVAL;
	3553	+
3551	3554	dev_info(adev->dev, "VBIOS flash to PSP started");
3552	3555
3553	3556	ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
@@ -3599,13 +3602,13 @@ static ssize_t amdgpu_psp_vbflash_status(struct device *dev, · 45 unmodified lines
3599	3602	}
3600	3603
3601	3604	static const struct bin_attribute psp_vbflash_bin_attr = {
3602		− .attr = {.name = "psp_vbflash", .mode = 0664},
	3605	+ .attr = {.name = "psp_vbflash", .mode = 0660},
3603	3606	.size = 0,
3604	3607	.write = amdgpu_psp_vbflash_write,
3605	3608	.read = amdgpu_psp_vbflash_read,
3606	3609	};
3607	3610
3608		−static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
	3611	+static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3609	3612
3610	3613	int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3611	3614	{

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+18−0

@@ -581,3 +581,21 @@ void amdgpu_ring_ib_end(struct amdgpu_ring *ring) · 580 unmodified lines
581	581	if (ring->is_sw_ring)
582	582	amdgpu_sw_ring_ib_end(ring);
583	583	}
	584	+
	585	+void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring)
	586	+{
	587	+ if (ring->is_sw_ring)
	588	+ amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL);
	589	+}
	590	+
	591	+void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring)
	592	+{
	593	+ if (ring->is_sw_ring)
	594	+ amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE);
	595	+}
	596	+
	597	+void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring)
	598	+{
	599	+ if (ring->is_sw_ring)
	600	+ amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE);
	601	+}

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+9−0

@@ -227,6 +227,9 @@ struct amdgpu_ring_funcs { · 226 unmodified lines
227	227	int (preempt_ib)(struct amdgpu_ring ring);
228	228	void (emit_mem_sync)(struct amdgpu_ring ring);
229	229	void (emit_wave_limit)(struct amdgpu_ring ring, bool enable);
	230	+ void (patch_cntl)(struct amdgpu_ring ring, unsigned offset);
	231	+ void (patch_ce)(struct amdgpu_ring ring, unsigned offset);
	232	+ void (patch_de)(struct amdgpu_ring ring, unsigned offset);
230	233	};
231	234
232	235	struct amdgpu_ring {
@@ -318,10 +321,16 @@ struct amdgpu_ring { · 85 unmodified lines
318	321	#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
319	322	#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
320	323	#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
	324	+#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
	325	+#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
	326	+#define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
321	327
322	328	int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
323	329	void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
324	330	void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
	331	+void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
	332	+void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
	333	+void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
325	334
326	335	void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
327	336	void amdgpu_ring_generic_pad_ib(struct amdgpu_ring ring, struct amdgpu_ib ib);

drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c+60−0

@@ -105,6 +105,16 @@ static void amdgpu_mux_resubmit_chunks(struct amdgpu_ring_mux *mux) · 104 unmodified lines
105	105	amdgpu_fence_update_start_timestamp(e->ring,
106	106	chunk->sync_seq,
107	107	ktime_get());
	108	+ if (chunk->sync_seq ==
	109	+ le32_to_cpu(*(e->ring->fence_drv.cpu_addr + 2))) {
	110	+ if (chunk->cntl_offset <= e->ring->buf_mask)
	111	+ amdgpu_ring_patch_cntl(e->ring,
	112	+ chunk->cntl_offset);
	113	+ if (chunk->ce_offset <= e->ring->buf_mask)
	114	+ amdgpu_ring_patch_ce(e->ring, chunk->ce_offset);
	115	+ if (chunk->de_offset <= e->ring->buf_mask)
	116	+ amdgpu_ring_patch_de(e->ring, chunk->de_offset);
	117	+ }
108	118	amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, e->ring,
109	119	chunk->start,
110	120	chunk->end);
@@ -407,6 +417,17 @@ void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring) · 296 unmodified lines
407	417	amdgpu_ring_mux_end_ib(mux, ring);
408	418	}
409	419
	420	+void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type)
	421	+{
	422	+ struct amdgpu_device *adev = ring->adev;
	423	+ struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
	424	+ unsigned offset;
	425	+
	426	+ offset = ring->wptr & ring->buf_mask;
	427	+
	428	+ amdgpu_ring_mux_ib_mark_offset(mux, ring, offset, type);
	429	+}
	430	+
410	431	void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux mux, struct amdgpu_ring ring)
411	432	{
412	433	struct amdgpu_mux_entry *e;
@@ -429,6 +450,10 @@ void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux mux, struct amdgpu_ring r · 16 unmodified lines
429	450	}
430	451
431	452	chunk->start = ring->wptr;
	453	+ /* the initialized value used to check if they are set by the ib submission*/
	454	+ chunk->cntl_offset = ring->buf_mask + 1;
	455	+ chunk->de_offset = ring->buf_mask + 1;
	456	+ chunk->ce_offset = ring->buf_mask + 1;
432	457	list_add_tail(&chunk->entry, &e->list);
433	458	}
434	459
@@ -454,6 +479,41 @@ static void scan_and_remove_signaled_chunk(struct amdgpu_ring_mux *mux, struct a · 19 unmodified lines
454	479	}
455	480	}
456	481
	482	+void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux *mux,
	483	+ struct amdgpu_ring *ring, u64 offset,
	484	+ enum amdgpu_ring_mux_offset_type type)
	485	+{
	486	+ struct amdgpu_mux_entry *e;
	487	+ struct amdgpu_mux_chunk *chunk;
	488	+
	489	+ e = amdgpu_ring_mux_sw_entry(mux, ring);
	490	+ if (!e) {
	491	+ DRM_ERROR("cannot find entry!\n");
	492	+ return;
	493	+ }
	494	+
	495	+ chunk = list_last_entry(&e->list, struct amdgpu_mux_chunk, entry);
	496	+ if (!chunk) {
	497	+ DRM_ERROR("cannot find chunk!\n");
	498	+ return;
	499	+ }
	500	+
	501	+ switch (type) {
	502	+ case AMDGPU_MUX_OFFSET_TYPE_CONTROL:
	503	+ chunk->cntl_offset = offset;
	504	+ break;
	505	+ case AMDGPU_MUX_OFFSET_TYPE_DE:
	506	+ chunk->de_offset = offset;
	507	+ break;
	508	+ case AMDGPU_MUX_OFFSET_TYPE_CE:
	509	+ chunk->ce_offset = offset;
	510	+ break;
	511	+ default:
	512	+ DRM_ERROR("invalid type (%d)\n", type);
	513	+ break;
	514	+ }
	515	+}
	516	+
457	517	void amdgpu_ring_mux_end_ib(struct amdgpu_ring_mux mux, struct amdgpu_ring ring)
458	518	{
459	519	struct amdgpu_mux_entry *e;

drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h+15−0

@@ -50,6 +50,12 @@ struct amdgpu_mux_entry { · 49 unmodified lines
50	50	struct list_head list;
51	51	};
52	52
	53	+enum amdgpu_ring_mux_offset_type {
	54	+ AMDGPU_MUX_OFFSET_TYPE_CONTROL,
	55	+ AMDGPU_MUX_OFFSET_TYPE_DE,
	56	+ AMDGPU_MUX_OFFSET_TYPE_CE,
	57	+};
	58	+
53	59	struct amdgpu_ring_mux {
54	60	struct amdgpu_ring *real_ring;
55	61
@@ -72,12 +78,18 @@ struct amdgpu_ring_mux { · 16 unmodified lines
72	78	* @sync_seq: the fence seqno related with the saved IB.
73	79	* @start:- start location on the software ring.
74	80	* @end:- end location on the software ring.
	81	+ * @control_offset:- the PRE_RESUME bit position used for resubmission.
	82	+ * @de_offset:- the anchor in write_data for de meta of resubmission.
	83	+ * @ce_offset:- the anchor in write_data for ce meta of resubmission.
75	84	*/
76	85	struct amdgpu_mux_chunk {
77	86	struct list_head entry;
78	87	uint32_t sync_seq;
79	88	u64 start;
80	89	u64 end;
	90	+ u64 cntl_offset;
	91	+ u64 de_offset;
	92	+ u64 ce_offset;
81	93	};
82	94
83	95	int amdgpu_ring_mux_init(struct amdgpu_ring_mux mux, struct amdgpu_ring ring,
@@ -89,6 +101,8 @@ u64 amdgpu_ring_mux_get_wptr(struct amdgpu_ring_mux mux, struct amdgpu_ring ri · 5 unmodified lines
89	101	u64 amdgpu_ring_mux_get_rptr(struct amdgpu_ring_mux mux, struct amdgpu_ring ring);
90	102	void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux mux, struct amdgpu_ring ring);
91	103	void amdgpu_ring_mux_end_ib(struct amdgpu_ring_mux mux, struct amdgpu_ring ring);
	104	+void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux mux, struct amdgpu_ring ring,
	105	+ u64 offset, enum amdgpu_ring_mux_offset_type type);
92	106	bool amdgpu_mcbp_handle_trailing_fence_irq(struct amdgpu_ring_mux *mux);
93	107
94	108	u64 amdgpu_sw_ring_get_rptr_gfx(struct amdgpu_ring *ring);
@@ -97,6 +111,7 @@ void amdgpu_sw_ring_set_wptr_gfx(struct amdgpu_ring *ring); · 2 unmodified lines
97	111	void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
98	112	void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);
99	113	void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring);
	114	+void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type);
100	115	const char *amdgpu_sw_ring_name(int idx);
101	116	unsigned int amdgpu_sw_ring_priority(int idx);
102	117

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+92−9

@@ -755,7 +755,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); · 754 unmodified lines
755	755	static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
756	756	struct amdgpu_cu_info *cu_info);
757	757	static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
758		−static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
	758	+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds);
759	759	static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
760	760	static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
761	761	void *ras_error_status);
@@ -5127,7 +5127,8 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, · 4365 unmodified lines
5127	5127	gfx_v9_0_ring_emit_de_meta(ring,
5128	5128	(!amdgpu_sriov_vf(ring->adev) &&
5129	5129	flags & AMDGPU_IB_PREEMPTED) ?
5130		− true : false);
	5130	+ true : false,
	5131	+ job->gds_size > 0 && job->gds_base != 0);
5131	5132	}
5132	5133
5133	5134	amdgpu_ring_write(ring, header);
@@ -5138,9 +5139,83 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, · 4 unmodified lines
5138	5139	#endif
5139	5140	lower_32_bits(ib->gpu_addr));
5140	5141	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
	5142	+ amdgpu_ring_ib_on_emit_cntl(ring);
5141	5143	amdgpu_ring_write(ring, control);
5142	5144	}
5143	5145
	5146	+static void gfx_v9_0_ring_patch_cntl(struct amdgpu_ring *ring,
	5147	+ unsigned offset)
	5148	+{
	5149	+ u32 control = ring->ring[offset];
	5150	+
	5151	+ control \|= INDIRECT_BUFFER_PRE_RESUME(1);
	5152	+ ring->ring[offset] = control;
	5153	+}
	5154	+
	5155	+static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring,
	5156	+ unsigned offset)
	5157	+{
	5158	+ struct amdgpu_device *adev = ring->adev;
	5159	+ void *ce_payload_cpu_addr;
	5160	+ uint64_t payload_offset, payload_size;
	5161	+
	5162	+ payload_size = sizeof(struct v9_ce_ib_state);
	5163	+
	5164	+ if (ring->is_mes_queue) {
	5165	+ payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
	5166	+ gfx[0].gfx_meta_data) +
	5167	+ offsetof(struct v9_gfx_meta_data, ce_payload);
	5168	+ ce_payload_cpu_addr =
	5169	+ amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
	5170	+ } else {
	5171	+ payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload);
	5172	+ ce_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
	5173	+ }
	5174	+
	5175	+ if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
	5176	+ memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, payload_size);
	5177	+ } else {
	5178	+ memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr,
	5179	+ (ring->buf_mask + 1 - offset) << 2);
	5180	+ payload_size -= (ring->buf_mask + 1 - offset) << 2;
	5181	+ memcpy((void *)&ring->ring[0],
	5182	+ ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
	5183	+ payload_size);
	5184	+ }
	5185	+}
	5186	+
	5187	+static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring,
	5188	+ unsigned offset)
	5189	+{
	5190	+ struct amdgpu_device *adev = ring->adev;
	5191	+ void *de_payload_cpu_addr;
	5192	+ uint64_t payload_offset, payload_size;
	5193	+
	5194	+ payload_size = sizeof(struct v9_de_ib_state);
	5195	+
	5196	+ if (ring->is_mes_queue) {
	5197	+ payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
	5198	+ gfx[0].gfx_meta_data) +
	5199	+ offsetof(struct v9_gfx_meta_data, de_payload);
	5200	+ de_payload_cpu_addr =
	5201	+ amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
	5202	+ } else {
	5203	+ payload_offset = offsetof(struct v9_gfx_meta_data, de_payload);
	5204	+ de_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
	5205	+ }
	5206	+
	5207	+ if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
	5208	+ memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, payload_size);
	5209	+ } else {
	5210	+ memcpy((void *)&ring->ring[offset], de_payload_cpu_addr,
	5211	+ (ring->buf_mask + 1 - offset) << 2);
	5212	+ payload_size -= (ring->buf_mask + 1 - offset) << 2;
	5213	+ memcpy((void *)&ring->ring[0],
	5214	+ de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
	5215	+ payload_size);
	5216	+ }
	5217	+}
	5218	+
5144	5219	static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5145	5220	struct amdgpu_job *job,
5146	5221	struct amdgpu_ib *ib,
@@ -5336,6 +5411,8 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) · 189 unmodified lines
5336	5411	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
5337	5412	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
5338	5413
	5414	+ amdgpu_ring_ib_on_emit_ce(ring);
	5415	+
5339	5416	if (resume)
5340	5417	amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
5341	5418	sizeof(ce_payload) >> 2);
@@ -5369,10 +5446,6 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) · 27 unmodified lines
5369	5446	amdgpu_ring_alloc(ring, 13);
5370	5447	gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
5371	5448	ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC \| AMDGPU_FENCE_FLAG_INT);
5372		− /reset the CP_VMID_PREEMPT after trailing fence/
5373		− amdgpu_ring_emit_wreg(ring,
5374		− SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
5375		− 0x0);
5376	5449
5377	5450	/* assert IB preemption, emit the trailing fence */
5378	5451	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
@@ -5395,6 +5468,10 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) · 16 unmodified lines
5395	5468	DRM_WARN("ring %d timeout to preempt ib\n", ring->idx);
5396	5469	}
5397	5470
	5471	+ /reset the CP_VMID_PREEMPT after trailing fence/
	5472	+ amdgpu_ring_emit_wreg(ring,
	5473	+ SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
	5474	+ 0x0);
5398	5475	amdgpu_ring_commit(ring);
5399	5476
5400	5477	/* deassert preemption condition */
@@ -5402,7 +5479,7 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) · 1 unmodified line
5402	5479	return r;
5403	5480	}
5404	5481
5405		−static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
	5482	+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds)
5406	5483	{
5407	5484	struct amdgpu_device *adev = ring->adev;
5408	5485	struct v9_de_ib_state de_payload = {0};
@@ -5433,8 +5510,10 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) · 24 unmodified lines
5433	5510	PAGE_SIZE);
5434	5511	}
5435	5512
5436		− de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5437		− de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
	5513	+ if (usegds) {
	5514	+ de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
	5515	+ de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
	5516	+ }
5438	5517
5439	5518	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5440	5519	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
@@ -5445,6 +5524,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) · 4 unmodified lines
5445	5524	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5446	5525	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5447	5526
	5527	+ amdgpu_ring_ib_on_emit_de(ring);
5448	5528	if (resume)
5449	5529	amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5450	5530	sizeof(de_payload) >> 2);
@@ -6855,6 +6935,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { · 1404 unmodified lines
6855	6935	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6856	6936	.soft_recovery = gfx_v9_0_ring_soft_recovery,
6857	6937	.emit_mem_sync = gfx_v9_0_emit_mem_sync,
	6938	+ .patch_cntl = gfx_v9_0_ring_patch_cntl,
	6939	+ .patch_de = gfx_v9_0_ring_patch_de_meta,
	6940	+ .patch_ce = gfx_v9_0_ring_patch_ce_meta,
6858	6941	};
6859	6942
6860	6943	static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c+5−1

@@ -129,7 +129,11 @@ static int vcn_v4_0_sw_init(void *handle) · 128 unmodified lines
129	129	if (adev->vcn.harvest_config & (1 << i))
130	130	continue;
131	131
132		− atomic_set(&adev->vcn.inst[i].sched_score, 0);
	132	+ /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
	133	+ if (i == 0)
	134	+ atomic_set(&adev->vcn.inst[i].sched_score, 1);
	135	+ else
	136	+ atomic_set(&adev->vcn.inst[i].sched_score, 0);
133	137
134	138	/* VCN UNIFIED TRAP */
135	139	r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+13−5

@@ -7196,7 +7196,13 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) · 7195 unmodified lines
7196	7196	drm_add_modes_noedid(connector, 1920, 1080);
7197	7197	} else {
7198	7198	amdgpu_dm_connector_ddc_get_modes(connector, edid);
7199		− amdgpu_dm_connector_add_common_modes(encoder, connector);
	7199	+ /* most eDP supports only timings from its edid,
	7200	+ * usually only detailed timings are available
	7201	+ * from eDP edid. timings which are not from edid
	7202	+ * may damage eDP
	7203	+ */
	7204	+ if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
	7205	+ amdgpu_dm_connector_add_common_modes(encoder, connector);
7200	7206	amdgpu_dm_connector_add_freesync_modes(connector, edid);
7201	7207	}
7202	7208	amdgpu_dm_fbc_init(connector);
@@ -8198,6 +8204,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 995 unmodified lines
8198	8204	if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8199	8205	bundle->stream_update.abm_level = &acrtc_state->abm_level;
8200	8206
	8207	+ mutex_lock(&dm->dc_lock);
	8208	+ if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
	8209	+ acrtc_state->stream->link->psr_settings.psr_allow_active)
	8210	+ amdgpu_dm_psr_disable(acrtc_state->stream);
	8211	+ mutex_unlock(&dm->dc_lock);
	8212	+
8201	8213	/*
8202	8214	* If FreeSync state on the stream has changed then we need to
8203	8215	* re-adjust the min/max bounds now that DC doesn't handle this
@@ -8211,10 +8223,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 7 unmodified lines
8211	8223	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8212	8224	}
8213	8225	mutex_lock(&dm->dc_lock);
8214		− if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8215		− acrtc_state->stream->link->psr_settings.psr_allow_active)
8216		− amdgpu_dm_psr_disable(acrtc_state->stream);
8217		−
8218	8226	update_planes_and_stream_adapter(dm->dc,
8219	8227	acrtc_state->update_type,
8220	8228	planes_count,

drivers/gpu/drm/amd/display/dc/link/link_detection.c+5−0

@@ -980,6 +980,11 @@ static bool detect_link_and_local_sink(struct dc_link *link, · 979 unmodified lines
980	980	(link->dpcd_caps.dongle_type !=
981	981	DISPLAY_DONGLE_DP_HDMI_CONVERTER))
982	982	converter_disable_audio = true;
	983	+
	984	+ /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
	985	+ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
	986	+ link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
	987	+ link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
983	988	break;
984	989	}
985	990

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c+31−2

@@ -1696,10 +1696,39 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, · 1695 unmodified lines
1696	1696	}
1697	1697	}
1698	1698
1699		− /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB__BIT /
1700		− workload_type = smu_cmn_to_asic_specific_index(smu,
	1699	+ if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &&
	1700	+ (((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xC8)) \|\|
	1701	+ ((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xCC)))) {
	1702	+ ret = smu_cmn_update_table(smu,
	1703	+ SMU_TABLE_ACTIVITY_MONITOR_COEFF,
	1704	+ WORKLOAD_PPLIB_COMPUTE_BIT,
	1705	+ (void *)(&activity_monitor_external),
	1706	+ false);
	1707	+ if (ret) {
	1708	+ dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
	1709	+ return ret;
	1710	+ }
	1711	+
	1712	+ ret = smu_cmn_update_table(smu,
	1713	+ SMU_TABLE_ACTIVITY_MONITOR_COEFF,
	1714	+ WORKLOAD_PPLIB_CUSTOM_BIT,
	1715	+ (void *)(&activity_monitor_external),
	1716	+ true);
	1717	+ if (ret) {
	1718	+ dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
	1719	+ return ret;
	1720	+ }
	1721	+
	1722	+ workload_type = smu_cmn_to_asic_specific_index(smu,
	1723	+ CMN2ASIC_MAPPING_WORKLOAD,
	1724	+ PP_SMC_POWER_PROFILE_CUSTOM);
	1725	+ } else {
	1726	+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB__BIT /
	1727	+ workload_type = smu_cmn_to_asic_specific_index(smu,
1701	1728	CMN2ASIC_MAPPING_WORKLOAD,
1702	1729	smu->power_profile_mode);
	1730	+ }
	1731	+
1703	1732	if (workload_type < 0)
1704	1733	return -EINVAL;
1705	1734

drivers/gpu/drm/bridge/ti-sn65dsi86.c+4−0

@@ -298,6 +298,10 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata) · 297 unmodified lines
298	298	if (refclk_lut[i] == refclk_rate)
299	299	break;
300	300
	301	+ /* avoid buffer overflow and "1" is the default rate in the datasheet. */
	302	+ if (i >= refclk_lut_size)
	303	+ i = 1;
	304	+
301	305	regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
302	306	REFCLK_FREQ(i));
303	307

drivers/gpu/drm/nouveau/nouveau_acpi.c+3−0

@@ -220,6 +220,9 @@ static void nouveau_dsm_pci_probe(struct pci_dev pdev, acpi_handle dhandle_out · 219 unmodified lines
220	220	int optimus_funcs;
221	221	struct pci_dev *parent_pdev;
222	222
	223	+ if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
	224	+ return;
	225	+
223	226	*has_pr3 = false;
224	227	parent_pdev = pci_upstream_bridge(pdev);
225	228	if (parent_pdev) {

drivers/gpu/drm/nouveau/nouveau_connector.c+4−3

@@ -730,7 +730,8 @@ out: · 729 unmodified lines
730	730	#endif
731	731
732	732	nouveau_connector_set_edid(nv_connector, edid);
733		− nouveau_connector_set_encoder(connector, nv_encoder);
	733	+ if (nv_encoder)
	734	+ nouveau_connector_set_encoder(connector, nv_encoder);
734	735	return status;
735	736	}
736	737
@@ -966,7 +967,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) · 229 unmodified lines
966	967	/* Determine display colour depth for everything except LVDS now,
967	968	* DP requires this before mode_valid() is called.
968	969	*/
969		− if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
	970	+ if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode)
970	971	nouveau_connector_detect_depth(connector);
971	972
972	973	/* Find the native mode if this is a digital panel, if we didn't
@@ -987,7 +988,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) · 14 unmodified lines
987	988	* "native" mode as some VBIOS tables require us to use the
988	989	* pixel clock as part of the lookup...
989	990	*/
990		− if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
	991	+ if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode)
991	992	nouveau_connector_detect_depth(connector);
992	993
993	994	if (nv_encoder->dcb->type == DCB_OUTPUT_TV)

drivers/gpu/drm/nouveau/nouveau_drm.c+10−4

@@ -137,10 +137,16 @@ nouveau_name(struct drm_device *dev) · 136 unmodified lines
137	137	static inline bool
138	138	nouveau_cli_work_ready(struct dma_fence *fence)
139	139	{
140		− if (!dma_fence_is_signaled(fence))
141		− return false;
142		− dma_fence_put(fence);
143		− return true;
	140	+ bool ret = true;
	141	+
	142	+ spin_lock_irq(fence->lock);
	143	+ if (!dma_fence_is_signaled_locked(fence))
	144	+ ret = false;
	145	+ spin_unlock_irq(fence->lock);
	146	+
	147	+ if (ret == true)
	148	+ dma_fence_put(fence);
	149	+ return ret;
144	150	}
145	151
146	152	static void

drivers/gpu/drm/radeon/radeon_fbdev.c+1−0

@@ -307,6 +307,7 @@ static void radeon_fbdev_client_unregister(struct drm_client_dev *client) · 306 unmodified lines
307	307
308	308	if (fb_helper->info) {
309	309	vga_switcheroo_client_fb_set(rdev->pdev, NULL);
	310	+ drm_helper_force_disable_all(dev);
310	311	drm_fb_helper_unregister_info(fb_helper);
311	312	} else {
312	313	drm_client_release(&fb_helper->client);

Merge tag 'drm-fixes-2023-06-17' of git://anongit.freedesktop.org/drm/drm

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