History

Merge tag 'microblaze-v6.2' of git://git.monstr.eu/linux-2.6-microblaze

Pull microblaze updates from Michal Simek: "Clean up PCI support which was pretty much copied and pasted from PowerPC long time ago for one custom platform which is not available for years. Also, the Xilinx/AMD PCIe team tested Microblaze with IP cores also used on ARM SOCs and clean up Microblaze code" * tag 'microblaze-v6.2' of git://git.monstr.eu/linux-2.6-microblaze: microblaze/PCI: Moving PCI iounmap and dependent code microblaze/PCI: Remove support for Xilinx PCI host bridge microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al declaration microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU address to I/O port microblaze/PCI: Remove unused PCI Indirect ops microblaze/PCI: Remove unused PCI BIOS resource allocation microblaze/PCI: Remove unused allocation & free of PCI host bridge structure microblaze/PCI: Remove unused device tree parsing for a host bridge resources microblaze/PCI: Remove unused PCI legacy IO's access on a bus microblaze/PCI: Remove unused PCI bus scan if configured as a host microblaze/PCI: Remove Null PCI config access unused functions microblaze/PCI: Remove unused early_read_config_byte() et al declarations

Linus Torvalds committed 3 years ago

Commit 164f5902 parents 7d62159 5cfe4699 files · +37 −1527Browse files

Unified · Split

9 files
  1. arch/microblaze/Kconfig +0 −8
  2. arch/microblaze/configs/mmu_defconfig +0 −1
  3. arch/microblaze/include/asm/pci-bridge.h +0 −92
  4. arch/microblaze/include/asm/pci.h +0 −29
  5. arch/microblaze/pci/Makefile +1 −2
  6. arch/microblaze/pci/indirect_pci.c +0 −158
  7. arch/microblaze/pci/iomap.c +36 −0
  8. arch/microblaze/pci/pci-common.c +0 −1067
  9. arch/microblaze/pci/xilinx_pci.c +0 −170
arch/microblaze/Kconfig+0−8
@@ -215,11 +215,3 @@ config MB_MANAGER · 214 unmodified lines
215 Say N here unless you know what you are doing.215 Say N here unless you know what you are doing.
216 216
217endmenu217endmenu
218
219menu "Bus Options"
220
221config PCI_XILINX
222 bool "Xilinx PCI host bridge support"
223 depends on PCI
224
225endmenu
arch/microblaze/configs/mmu_defconfig+0−1
@@ -19,7 +19,6 @@ CONFIG_HZ_100=y · 18 unmodified lines
19CONFIG_CMDLINE_BOOL=y19CONFIG_CMDLINE_BOOL=y
20CONFIG_CMDLINE_FORCE=y20CONFIG_CMDLINE_FORCE=y
21CONFIG_HIGHMEM=y21CONFIG_HIGHMEM=y
22CONFIG_PCI_XILINX=y
23CONFIG_MODULES=y22CONFIG_MODULES=y
24CONFIG_MODULE_UNLOAD=y23CONFIG_MODULE_UNLOAD=y
25# CONFIG_BLK_DEV_BSG is not set24# CONFIG_BLK_DEV_BSG is not set
arch/microblaze/include/asm/pci-bridge.h+0−92
@@ -25,75 +25,17 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address) · 24 unmodified lines
25 */25 */
26struct pci_controller {26struct pci_controller {
27 struct pci_bus *bus;27 struct pci_bus *bus;
28 char is_dynamic;
29 struct device_node *dn;
30 struct list_head list_node;28 struct list_head list_node;
31 struct device *parent;
32
33 int first_busno;
34 int last_busno;
35
36 int self_busno;
37 29
38 void __iomem *io_base_virt;30 void __iomem *io_base_virt;
39 resource_size_t io_base_phys;
40
41 resource_size_t pci_io_size;
42
43 /* Some machines (PReP) have a non 1:1 mapping of
44 * the PCI memory space in the CPU bus space
45 */
46 resource_size_t pci_mem_offset;
47
48 /* Some machines have a special region to forward the ISA
49 * "memory" cycles such as VGA memory regions. Left to 0
50 * if unsupported
51 */
52 resource_size_t isa_mem_phys;
53 resource_size_t isa_mem_size;
54
55 struct pci_ops *ops;
56 unsigned int __iomem *cfg_addr;
57 void __iomem *cfg_data;
58
59 /*
60 * Used for variants of PCI indirect handling and possible quirks:
61 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
62 * EXT_REG - provides access to PCI-e extended registers
63 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
64 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
65 * to determine which bus number to match on when generating type0
66 * config cycles
67 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
68 * hanging if we don't have link and try to do config cycles to
69 * anything but the PHB. Only allow talking to the PHB if this is
70 * set.
71 * BIG_ENDIAN - cfg_addr is a big endian register
72 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
73 * on the PLB4. Effectively disable MRM commands by setting this.
74 */
75#define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
76#define INDIRECT_TYPE_EXT_REG 0x00000002
77#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
78#define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
79#define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
80#define INDIRECT_TYPE_BROKEN_MRM 0x00000020
81 u32 indirect_type;
82 31
83 /* Currently, we limit ourselves to 1 IO range and 3 mem32 /* Currently, we limit ourselves to 1 IO range and 3 mem
84 * ranges since the common pci_bus structure can't handle more33 * ranges since the common pci_bus structure can't handle more
85 */34 */
86 struct resource io_resource;35 struct resource io_resource;
87 struct resource mem_resources[3];
88 int global_number; /* PCI domain number */
89};36};
90 37
91#ifdef CONFIG_PCI38#ifdef CONFIG_PCI
92static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
93{
94 return bus->sysdata;
95}
96
97static inline int isa_vaddr_is_ioport(void __iomem *address)39static inline int isa_vaddr_is_ioport(void __iomem *address)
98{40{
99 /* No specific ISA handling on ppc32 at this stage, it41 /* No specific ISA handling on ppc32 at this stage, it
@@ -103,39 +45,5 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) · 3 unmodified lines
103}45}
104#endif /* CONFIG_PCI */46#endif /* CONFIG_PCI */
105 47
106/* These are used for config access before all the PCI probing
107 has been done. */
108extern int early_read_config_byte(struct pci_controller *hose, int bus,
109 int dev_fn, int where, u8 *val);
110extern int early_read_config_word(struct pci_controller *hose, int bus,
111 int dev_fn, int where, u16 *val);
112extern int early_read_config_dword(struct pci_controller *hose, int bus,
113 int dev_fn, int where, u32 *val);
114extern int early_write_config_byte(struct pci_controller *hose, int bus,
115 int dev_fn, int where, u8 val);
116extern int early_write_config_word(struct pci_controller *hose, int bus,
117 int dev_fn, int where, u16 val);
118extern int early_write_config_dword(struct pci_controller *hose, int bus,
119 int dev_fn, int where, u32 val);
120
121extern int early_find_capability(struct pci_controller *hose, int bus,
122 int dev_fn, int cap);
123
124extern void setup_indirect_pci(struct pci_controller *hose,
125 resource_size_t cfg_addr,
126 resource_size_t cfg_data, u32 flags);
127
128/* Get the PCI host controller for an OF device */
129extern struct pci_controller *pci_find_hose_for_OF_device(
130 struct device_node *node);
131
132/* Fill up host controller resources from the OF node */
133extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
134 struct device_node *dev, int primary);
135
136/* Allocate & free a PCI host bridge structure */
137extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
138extern void pcibios_free_controller(struct pci_controller *phb);
139
140#endif /* __KERNEL__ */48#endif /* __KERNEL__ */
141#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */49#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
arch/microblaze/include/asm/pci.h+0−29
@@ -21,15 +21,6 @@ · 20 unmodified lines
21#define PCIBIOS_MIN_IO 0x100021#define PCIBIOS_MIN_IO 0x1000
22#define PCIBIOS_MIN_MEM 0x1000000022#define PCIBIOS_MIN_MEM 0x10000000
23 23
24/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
25#define IOBASE_BRIDGE_NUMBER 0
26#define IOBASE_MEMORY 1
27#define IOBASE_IO 2
28#define IOBASE_ISA_IO 3
29#define IOBASE_ISA_MEM 4
30
31#define pcibios_scan_all_fns(a, b) 0
32
33/*24/*
34 * Set this to 1 if you want the kernel to re-assign all PCI25 * Set this to 1 if you want the kernel to re-assign all PCI
35 * bus numbers (don't do that on ppc64 yet !)26 * bus numbers (don't do that on ppc64 yet !)
@@ -41,33 +32,13 @@ extern int pci_domain_nr(struct pci_bus *bus); · 5 unmodified lines
41/* Decide whether to display the domain number in /proc */32/* Decide whether to display the domain number in /proc */
42extern int pci_proc_domain(struct pci_bus *bus);33extern int pci_proc_domain(struct pci_bus *bus);
43 34
44struct vm_area_struct;
45
46/* Tell PCI code what kind of PCI resource mappings we support */35/* Tell PCI code what kind of PCI resource mappings we support */
47#define HAVE_PCI_MMAP 136#define HAVE_PCI_MMAP 1
48#define ARCH_GENERIC_PCI_MMAP_RESOURCE 137#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
49#define arch_can_pci_mmap_io() 1
50
51extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
52 size_t count);
53extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
54 size_t count);
55extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
56 struct vm_area_struct *vma,
57 enum pci_mmap_state mmap_state);
58
59#define HAVE_PCI_LEGACY 1
60
61extern void pcibios_resource_survey(void);
62 38
63struct file;39struct file;
64 40
65/* This part of code was originally in xilinx-pci.h */
66#ifdef CONFIG_PCI_XILINX
67extern void __init xilinx_pci_init(void);
68#else
69static inline void __init xilinx_pci_init(void) { return; }41static inline void __init xilinx_pci_init(void) { return; }
70#endif
71 42
72#endif /* __KERNEL__ */43#endif /* __KERNEL__ */
73#endif /* __ASM_MICROBLAZE_PCI_H */44#endif /* __ASM_MICROBLAZE_PCI_H */
arch/microblaze/pci/Makefile+1−2
@@ -3,5 +3,4 @@ · 2 unmodified lines
3# Makefile3# Makefile
4#4#
5 5
6obj-$(CONFIG_PCI) += pci-common.o indirect_pci.o iomap.o6obj-$(CONFIG_PCI) += iomap.o
7obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o
arch/microblaze/pci/indirect_pci.c+0−158
@@ -1,158 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Support for indirect PCI bridges.
4 *
5 * Copyright (C) 1998 Gabriel Paubert.
6 */
7
8#include <linux/kernel.h>
9#include <linux/pci.h>
10#include <linux/delay.h>
11#include <linux/string.h>
12#include <linux/init.h>
13
14#include <linux/io.h>
15#include <asm/pci-bridge.h>
16
17static int
18indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
19 int len, u32 *val)
20{
21 struct pci_controller *hose = pci_bus_to_host(bus);
22 volatile void __iomem *cfg_data;
23 u8 cfg_type = 0;
24 u32 bus_no, reg;
25
26 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
27 if (bus->number != hose->first_busno)
28 return PCIBIOS_DEVICE_NOT_FOUND;
29 if (devfn != 0)
30 return PCIBIOS_DEVICE_NOT_FOUND;
31 }
32
33 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
34 if (bus->number != hose->first_busno)
35 cfg_type = 1;
36
37 bus_no = (bus->number == hose->first_busno) ?
38 hose->self_busno : bus->number;
39
40 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
41 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
42 else
43 reg = offset & 0xfc; /* Only 3 bits for function */
44
45 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
46 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
47 (devfn << 8) | reg | cfg_type));
48 else
49 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
50 (devfn << 8) | reg | cfg_type));
51
52 /*
53 * Note: the caller has already checked that offset is
54 * suitably aligned and that len is 1, 2 or 4.
55 */
56 cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */
57 switch (len) {
58 case 1:
59 *val = in_8(cfg_data);
60 break;
61 case 2:
62 *val = in_le16(cfg_data);
63 break;
64 default:
65 *val = in_le32(cfg_data);
66 break;
67 }
68 return PCIBIOS_SUCCESSFUL;
69}
70
71static int
72indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
73 int len, u32 val)
74{
75 struct pci_controller *hose = pci_bus_to_host(bus);
76 volatile void __iomem *cfg_data;
77 u8 cfg_type = 0;
78 u32 bus_no, reg;
79
80 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
81 if (bus->number != hose->first_busno)
82 return PCIBIOS_DEVICE_NOT_FOUND;
83 if (devfn != 0)
84 return PCIBIOS_DEVICE_NOT_FOUND;
85 }
86
87 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
88 if (bus->number != hose->first_busno)
89 cfg_type = 1;
90
91 bus_no = (bus->number == hose->first_busno) ?
92 hose->self_busno : bus->number;
93
94 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
95 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
96 else
97 reg = offset & 0xfc;
98
99 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
100 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
101 (devfn << 8) | reg | cfg_type));
102 else
103 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
104 (devfn << 8) | reg | cfg_type));
105
106 /* suppress setting of PCI_PRIMARY_BUS */
107 if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
108 if ((offset == PCI_PRIMARY_BUS) &&
109 (bus->number == hose->first_busno))
110 val &= 0xffffff00;
111
112 /* Workaround for PCI_28 Errata in 440EPx/GRx */
113 if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&
114 offset == PCI_CACHE_LINE_SIZE) {
115 val = 0;
116 }
117
118 /*
119 * Note: the caller has already checked that offset is
120 * suitably aligned and that len is 1, 2 or 4.
121 */
122 cfg_data = hose->cfg_data + (offset & 3);
123 switch (len) {
124 case 1:
125 out_8(cfg_data, val);
126 break;
127 case 2:
128 out_le16(cfg_data, val);
129 break;
130 default:
131 out_le32(cfg_data, val);
132 break;
133 }
134
135 return PCIBIOS_SUCCESSFUL;
136}
137
138static struct pci_ops indirect_pci_ops = {
139 .read = indirect_read_config,
140 .write = indirect_write_config,
141};
142
143void __init
144setup_indirect_pci(struct pci_controller *hose,
145 resource_size_t cfg_addr,
146 resource_size_t cfg_data, u32 flags)
147{
148 resource_size_t base = cfg_addr & PAGE_MASK;
149 void __iomem *mbase;
150
151 mbase = ioremap(base, PAGE_SIZE);
152 hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
153 if ((cfg_data & PAGE_MASK) != base)
154 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
155 hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
156 hose->ops = &indirect_pci_ops;
157 hose->indirect_type = flags;
158}
arch/microblaze/pci/iomap.c+36−0
@@ -11,6 +11,42 @@ · 10 unmodified lines
11#include <linux/io.h>11#include <linux/io.h>
12#include <asm/pci-bridge.h>12#include <asm/pci-bridge.h>
13 13
14static DEFINE_SPINLOCK(hose_spinlock);
15LIST_HEAD(hose_list);
16
17unsigned long isa_io_base;
18EXPORT_SYMBOL(isa_io_base);
19
20static resource_size_t pcibios_io_size(const struct pci_controller *hose)
21{
22 return resource_size(&hose->io_resource);
23}
24
25int pcibios_vaddr_is_ioport(void __iomem *address)
26{
27 int ret = 0;
28 struct pci_controller *hose;
29 resource_size_t size;
30
31 spin_lock(&hose_spinlock);
32 list_for_each_entry(hose, &hose_list, list_node) {
33 size = pcibios_io_size(hose);
34 if (address >= hose->io_base_virt &&
35 address < (hose->io_base_virt + size)) {
36 ret = 1;
37 break;
38 }
39 }
40 spin_unlock(&hose_spinlock);
41 return ret;
42}
43
44/* Display the domain number in /proc */
45int pci_proc_domain(struct pci_bus *bus)
46{
47 return pci_domain_nr(bus);
48}
49
14void pci_iounmap(struct pci_dev *dev, void __iomem *addr)50void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
15{51{
16 if (isa_vaddr_is_ioport(addr))52 if (isa_vaddr_is_ioport(addr))
arch/microblaze/pci/pci-common.c+0−1067
@@ -1,1067 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
5 *
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 *
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
11 *
12 * Common pmac/prep/chrp pci routines. -- Cort
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/memblock.h>
20#include <linux/mm.h>
21#include <linux/shmem_fs.h>
22#include <linux/list.h>
23#include <linux/syscalls.h>
24#include <linux/irq.h>
25#include <linux/vmalloc.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/of_pci.h>
31#include <linux/export.h>
32
33#include <asm/processor.h>
34#include <linux/io.h>
35#include <asm/pci-bridge.h>
36#include <asm/byteorder.h>
37
38static DEFINE_SPINLOCK(hose_spinlock);
39LIST_HEAD(hose_list);
40
41/* XXX kill that some day ... */
42static int global_phb_number; /* Global phb counter */
43
44/* ISA Memory physical address */
45resource_size_t isa_mem_base;
46
47unsigned long isa_io_base;
48EXPORT_SYMBOL(isa_io_base);
49
50static int pci_bus_count;
51
52struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
53{
54 struct pci_controller *phb;
55
56 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
57 if (!phb)
58 return NULL;
59 spin_lock(&hose_spinlock);
60 phb->global_number = global_phb_number++;
61 list_add_tail(&phb->list_node, &hose_list);
62 spin_unlock(&hose_spinlock);
63 phb->dn = dev;
64 phb->is_dynamic = mem_init_done;
65 return phb;
66}
67
68void pcibios_free_controller(struct pci_controller *phb)
69{
70 spin_lock(&hose_spinlock);
71 list_del(&phb->list_node);
72 spin_unlock(&hose_spinlock);
73
74 if (phb->is_dynamic)
75 kfree(phb);
76}
77
78static resource_size_t pcibios_io_size(const struct pci_controller *hose)
79{
80 return resource_size(&hose->io_resource);
81}
82
83int pcibios_vaddr_is_ioport(void __iomem *address)
84{
85 int ret = 0;
86 struct pci_controller *hose;
87 resource_size_t size;
88
89 spin_lock(&hose_spinlock);
90 list_for_each_entry(hose, &hose_list, list_node) {
91 size = pcibios_io_size(hose);
92 if (address >= hose->io_base_virt &&
93 address < (hose->io_base_virt + size)) {
94 ret = 1;
95 break;
96 }
97 }
98 spin_unlock(&hose_spinlock);
99 return ret;
100}
101
102unsigned long pci_address_to_pio(phys_addr_t address)
103{
104 struct pci_controller *hose;
105 resource_size_t size;
106 unsigned long ret = ~0;
107
108 spin_lock(&hose_spinlock);
109 list_for_each_entry(hose, &hose_list, list_node) {
110 size = pcibios_io_size(hose);
111 if (address >= hose->io_base_phys &&
112 address < (hose->io_base_phys + size)) {
113 unsigned long base =
114 (unsigned long)hose->io_base_virt - _IO_BASE;
115 ret = base + (address - hose->io_base_phys);
116 break;
117 }
118 }
119 spin_unlock(&hose_spinlock);
120
121 return ret;
122}
123EXPORT_SYMBOL_GPL(pci_address_to_pio);
124
125/* This routine is meant to be used early during boot, when the
126 * PCI bus numbers have not yet been assigned, and you need to
127 * issue PCI config cycles to an OF device.
128 * It could also be used to "fix" RTAS config cycles if you want
129 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
130 * config cycles.
131 */
132struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
133{
134 while (node) {
135 struct pci_controller *hose, *tmp;
136 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
137 if (hose->dn == node)
138 return hose;
139 node = node->parent;
140 }
141 return NULL;
142}
143
144void pcibios_set_master(struct pci_dev *dev)
145{
146 /* No special bus mastering setup handling */
147}
148
149/*
150 * Platform support for /proc/bus/pci/X/Y mmap()s.
151 */
152
153int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
154{
155 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
156 resource_size_t ioaddr = pci_resource_start(pdev, bar);
157
158 if (!hose)
159 return -EINVAL; /* should never happen */
160
161 /* Convert to an offset within this PCI controller */
162 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
163
164 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
165 return 0;
166}
167
168/* This provides legacy IO read access on a bus */
169int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
170{
171 unsigned long offset;
172 struct pci_controller *hose = pci_bus_to_host(bus);
173 struct resource *rp = &hose->io_resource;
174 void __iomem *addr;
175
176 /* Check if port can be supported by that bus. We only check
177 * the ranges of the PHB though, not the bus itself as the rules
178 * for forwarding legacy cycles down bridges are not our problem
179 * here. So if the host bridge supports it, we do it.
180 */
181 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
182 offset += port;
183
184 if (!(rp->flags & IORESOURCE_IO))
185 return -ENXIO;
186 if (offset < rp->start || (offset + size) > rp->end)
187 return -ENXIO;
188 addr = hose->io_base_virt + port;
189
190 switch (size) {
191 case 1:
192 *((u8 *)val) = in_8(addr);
193 return 1;
194 case 2:
195 if (port & 1)
196 return -EINVAL;
197 *((u16 *)val) = in_le16(addr);
198 return 2;
199 case 4:
200 if (port & 3)
201 return -EINVAL;
202 *((u32 *)val) = in_le32(addr);
203 return 4;
204 }
205 return -EINVAL;
206}
207
208/* This provides legacy IO write access on a bus */
209int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
210{
211 unsigned long offset;
212 struct pci_controller *hose = pci_bus_to_host(bus);
213 struct resource *rp = &hose->io_resource;
214 void __iomem *addr;
215
216 /* Check if port can be supported by that bus. We only check
217 * the ranges of the PHB though, not the bus itself as the rules
218 * for forwarding legacy cycles down bridges are not our problem
219 * here. So if the host bridge supports it, we do it.
220 */
221 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
222 offset += port;
223
224 if (!(rp->flags & IORESOURCE_IO))
225 return -ENXIO;
226 if (offset < rp->start || (offset + size) > rp->end)
227 return -ENXIO;
228 addr = hose->io_base_virt + port;
229
230 /* WARNING: The generic code is idiotic. It gets passed a pointer
231 * to what can be a 1, 2 or 4 byte quantity and always reads that
232 * as a u32, which means that we have to correct the location of
233 * the data read within those 32 bits for size 1 and 2
234 */
235 switch (size) {
236 case 1:
237 out_8(addr, val >> 24);
238 return 1;
239 case 2:
240 if (port & 1)
241 return -EINVAL;
242 out_le16(addr, val >> 16);
243 return 2;
244 case 4:
245 if (port & 3)
246 return -EINVAL;
247 out_le32(addr, val);
248 return 4;
249 }
250 return -EINVAL;
251}
252
253/* This provides legacy IO or memory mmap access on a bus */
254int pci_mmap_legacy_page_range(struct pci_bus *bus,
255 struct vm_area_struct *vma,
256 enum pci_mmap_state mmap_state)
257{
258 struct pci_controller *hose = pci_bus_to_host(bus);
259 resource_size_t offset =
260 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
261 resource_size_t size = vma->vm_end - vma->vm_start;
262 struct resource *rp;
263
264 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
265 pci_domain_nr(bus), bus->number,
266 mmap_state == pci_mmap_mem ? "MEM" : "IO",
267 (unsigned long long)offset,
268 (unsigned long long)(offset + size - 1));
269
270 if (mmap_state == pci_mmap_mem) {
271 /* Hack alert !
272 *
273 * Because X is lame and can fail starting if it gets an error
274 * trying to mmap legacy_mem (instead of just moving on without
275 * legacy memory access) we fake it here by giving it anonymous
276 * memory, effectively behaving just like /dev/zero
277 */
278 if ((offset + size) > hose->isa_mem_size) {
279 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
280 current->comm, current->pid);
281 pr_debug("legacy memory for 0%04x:%02x\n",
282 pci_domain_nr(bus), bus->number);
283 if (vma->vm_flags & VM_SHARED)
284 return shmem_zero_setup(vma);
285 return 0;
286 }
287 offset += hose->isa_mem_phys;
288 } else {
289 unsigned long io_offset = (unsigned long)hose->io_base_virt -
290 _IO_BASE;
291 unsigned long roffset = offset + io_offset;
292 rp = &hose->io_resource;
293 if (!(rp->flags & IORESOURCE_IO))
294 return -ENXIO;
295 if (roffset < rp->start || (roffset + size) > rp->end)
296 return -ENXIO;
297 offset += hose->io_base_phys;
298 }
299 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
300
301 vma->vm_pgoff = offset >> PAGE_SHIFT;
302 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
303 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
304 vma->vm_end - vma->vm_start,
305 vma->vm_page_prot);
306}
307
308void pci_resource_to_user(const struct pci_dev *dev, int bar,
309 const struct resource *rsrc,
310 resource_size_t *start, resource_size_t *end)
311{
312 struct pci_bus_region region;
313
314 if (rsrc->flags & IORESOURCE_IO) {
315 pcibios_resource_to_bus(dev->bus, &region,
316 (struct resource *) rsrc);
317 *start = region.start;
318 *end = region.end;
319 return;
320 }
321
322 /* We pass a CPU physical address to userland for MMIO instead of a
323 * BAR value because X is lame and expects to be able to use that
324 * to pass to /dev/mem!
325 *
326 * That means we may have 64-bit values where some apps only expect
327 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
328 */
329 *start = rsrc->start;
330 *end = rsrc->end;
331}
332
333/**
334 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
335 * @hose: newly allocated pci_controller to be setup
336 * @dev: device node of the host bridge
337 * @primary: set if primary bus (32 bits only, soon to be deprecated)
338 *
339 * This function will parse the "ranges" property of a PCI host bridge device
340 * node and setup the resource mapping of a pci controller based on its
341 * content.
342 *
343 * Life would be boring if it wasn't for a few issues that we have to deal
344 * with here:
345 *
346 * - We can only cope with one IO space range and up to 3 Memory space
347 * ranges. However, some machines (thanks Apple !) tend to split their
348 * space into lots of small contiguous ranges. So we have to coalesce.
349 *
350 * - We can only cope with all memory ranges having the same offset
351 * between CPU addresses and PCI addresses. Unfortunately, some bridges
352 * are setup for a large 1:1 mapping along with a small "window" which
353 * maps PCI address 0 to some arbitrary high address of the CPU space in
354 * order to give access to the ISA memory hole.
355 * The way out of here that I've chosen for now is to always set the
356 * offset based on the first resource found, then override it if we
357 * have a different offset and the previous was set by an ISA hole.
358 *
359 * - Some busses have IO space not starting at 0, which causes trouble with
360 * the way we do our IO resource renumbering. The code somewhat deals with
361 * it for 64 bits but I would expect problems on 32 bits.
362 *
363 * - Some 32 bits platforms such as 4xx can have physical space larger than
364 * 32 bits so we need to use 64 bits values for the parsing
365 */
366void pci_process_bridge_OF_ranges(struct pci_controller *hose,
367 struct device_node *dev, int primary)
368{
369 int memno = 0, isa_hole = -1;
370 unsigned long long isa_mb = 0;
371 struct resource *res;
372 struct of_pci_range range;
373 struct of_pci_range_parser parser;
374
375 pr_info("PCI host bridge %pOF %s ranges:\n",
376 dev, primary ? "(primary)" : "");
377
378 /* Check for ranges property */
379 if (of_pci_range_parser_init(&parser, dev))
380 return;
381
382 pr_debug("Parsing ranges property...\n");
383 for_each_of_pci_range(&parser, &range) {
384 /* Read next ranges element */
385
386 /* If we failed translation or got a zero-sized region
387 * (some FW try to feed us with non sensical zero sized regions
388 * such as power3 which look like some kind of attempt
389 * at exposing the VGA memory hole)
390 */
391 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
392 continue;
393
394 /* Act based on address space type */
395 res = NULL;
396 switch (range.flags & IORESOURCE_TYPE_BITS) {
397 case IORESOURCE_IO:
398 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
399 range.cpu_addr, range.cpu_addr + range.size - 1,
400 range.pci_addr);
401
402 /* We support only one IO range */
403 if (hose->pci_io_size) {
404 pr_info(" \\--> Skipped (too many) !\n");
405 continue;
406 }
407 /* On 32 bits, limit I/O space to 16MB */
408 if (range.size > 0x01000000)
409 range.size = 0x01000000;
410
411 /* 32 bits needs to map IOs here */
412 hose->io_base_virt = ioremap(range.cpu_addr,
413 range.size);
414
415 /* Expect trouble if pci_addr is not 0 */
416 if (primary)
417 isa_io_base =
418 (unsigned long)hose->io_base_virt;
419 /* pci_io_size and io_base_phys always represent IO
420 * space starting at 0 so we factor in pci_addr
421 */
422 hose->pci_io_size = range.pci_addr + range.size;
423 hose->io_base_phys = range.cpu_addr - range.pci_addr;
424
425 /* Build resource */
426 res = &hose->io_resource;
427 range.cpu_addr = range.pci_addr;
428
429 break;
430 case IORESOURCE_MEM:
431 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
432 range.cpu_addr, range.cpu_addr + range.size - 1,
433 range.pci_addr,
434 (range.flags & IORESOURCE_PREFETCH) ?
435 "Prefetch" : "");
436
437 /* We support only 3 memory ranges */
438 if (memno >= 3) {
439 pr_info(" \\--> Skipped (too many) !\n");
440 continue;
441 }
442 /* Handles ISA memory hole space here */
443 if (range.pci_addr == 0) {
444 isa_mb = range.cpu_addr;
445 isa_hole = memno;
446 if (primary || isa_mem_base == 0)
447 isa_mem_base = range.cpu_addr;
448 hose->isa_mem_phys = range.cpu_addr;
449 hose->isa_mem_size = range.size;
450 }
451
452 /* We get the PCI/Mem offset from the first range or
453 * the, current one if the offset came from an ISA
454 * hole. If they don't match, bugger.
455 */
456 if (memno == 0 ||
457 (isa_hole >= 0 && range.pci_addr != 0 &&
458 hose->pci_mem_offset == isa_mb))
459 hose->pci_mem_offset = range.cpu_addr -
460 range.pci_addr;
461 else if (range.pci_addr != 0 &&
462 hose->pci_mem_offset != range.cpu_addr -
463 range.pci_addr) {
464 pr_info(" \\--> Skipped (offset mismatch) !\n");
465 continue;
466 }
467
468 /* Build resource */
469 res = &hose->mem_resources[memno++];
470 break;
471 }
472 if (res != NULL) {
473 res->name = dev->full_name;
474 res->flags = range.flags;
475 res->start = range.cpu_addr;
476 res->end = range.cpu_addr + range.size - 1;
477 res->parent = res->child = res->sibling = NULL;
478 }
479 }
480
481 /* If there's an ISA hole and the pci_mem_offset is -not- matching
482 * the ISA hole offset, then we need to remove the ISA hole from
483 * the resource list for that brige
484 */
485 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
486 unsigned int next = isa_hole + 1;
487 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
488 if (next < memno)
489 memmove(&hose->mem_resources[isa_hole],
490 &hose->mem_resources[next],
491 sizeof(struct resource) * (memno - next));
492 hose->mem_resources[--memno].flags = 0;
493 }
494}
495
496/* Display the domain number in /proc */
497int pci_proc_domain(struct pci_bus *bus)
498{
499 return pci_domain_nr(bus);
500}
501
502/* This header fixup will do the resource fixup for all devices as they are
503 * probed, but not for bridge ranges
504 */
505static void pcibios_fixup_resources(struct pci_dev *dev)
506{
507 struct pci_controller *hose = pci_bus_to_host(dev->bus);
508 int i;
509
510 if (!hose) {
511 pr_err("No host bridge for PCI dev %s !\n",
512 pci_name(dev));
513 return;
514 }
515 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
516 struct resource *res = dev->resource + i;
517 if (!res->flags)
518 continue;
519 if (res->start == 0) {
520 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
521 pci_name(dev), i,
522 (unsigned long long)res->start,
523 (unsigned long long)res->end,
524 (unsigned int)res->flags);
525 pr_debug("is unassigned\n");
526 res->end -= res->start;
527 res->start = 0;
528 res->flags |= IORESOURCE_UNSET;
529 continue;
530 }
531
532 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
533 pci_name(dev), i,
534 (unsigned long long)res->start,
535 (unsigned long long)res->end,
536 (unsigned int)res->flags);
537 }
538}
539DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
540
541int pcibios_device_add(struct pci_dev *dev)
542{
543 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
544
545 return 0;
546}
547
548/*
549 * Reparent resource children of pr that conflict with res
550 * under res, and make res replace those children.
551 */
552static int __init reparent_resources(struct resource *parent,
553 struct resource *res)
554{
555 struct resource *p, **pp;
556 struct resource **firstpp = NULL;
557
558 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
559 if (p->end < res->start)
560 continue;
561 if (res->end < p->start)
562 break;
563 if (p->start < res->start || p->end > res->end)
564 return -1; /* not completely contained */
565 if (firstpp == NULL)
566 firstpp = pp;
567 }
568 if (firstpp == NULL)
569 return -1; /* didn't find any conflicting entries? */
570 res->parent = parent;
571 res->child = *firstpp;
572 res->sibling = *pp;
573 *firstpp = res;
574 *pp = NULL;
575 for (p = res->child; p != NULL; p = p->sibling) {
576 p->parent = res;
577 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
578 p->name,
579 (unsigned long long)p->start,
580 (unsigned long long)p->end, res->name);
581 }
582 return 0;
583}
584
585/*
586 * Handle resources of PCI devices. If the world were perfect, we could
587 * just allocate all the resource regions and do nothing more. It isn't.
588 * On the other hand, we cannot just re-allocate all devices, as it would
589 * require us to know lots of host bridge internals. So we attempt to
590 * keep as much of the original configuration as possible, but tweak it
591 * when it's found to be wrong.
592 *
593 * Known BIOS problems we have to work around:
594 * - I/O or memory regions not configured
595 * - regions configured, but not enabled in the command register
596 * - bogus I/O addresses above 64K used
597 * - expansion ROMs left enabled (this may sound harmless, but given
598 * the fact the PCI specs explicitly allow address decoders to be
599 * shared between expansion ROMs and other resource regions, it's
600 * at least dangerous)
601 *
602 * Our solution:
603 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
604 * This gives us fixed barriers on where we can allocate.
605 * (2) Allocate resources for all enabled devices. If there is
606 * a collision, just mark the resource as unallocated. Also
607 * disable expansion ROMs during this step.
608 * (3) Try to allocate resources for disabled devices. If the
609 * resources were assigned correctly, everything goes well,
610 * if they weren't, they won't disturb allocation of other
611 * resources.
612 * (4) Assign new addresses to resources which were either
613 * not configured at all or misconfigured. If explicitly
614 * requested by the user, configure expansion ROM address
615 * as well.
616 */
617
618static void pcibios_allocate_bus_resources(struct pci_bus *bus)
619{
620 struct pci_bus *b;
621 int i;
622 struct resource *res, *pr;
623
624 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
625 pci_domain_nr(bus), bus->number);
626
627 pci_bus_for_each_resource(bus, res, i) {
628 if (!res || !res->flags
629 || res->start > res->end || res->parent)
630 continue;
631 if (bus->parent == NULL)
632 pr = (res->flags & IORESOURCE_IO) ?
633 &ioport_resource : &iomem_resource;
634 else {
635 /* Don't bother with non-root busses when
636 * re-assigning all resources. We clear the
637 * resource flags as if they were colliding
638 * and as such ensure proper re-allocation
639 * later.
640 */
641 pr = pci_find_parent_resource(bus->self, res);
642 if (pr == res) {
643 /* this happens when the generic PCI
644 * code (wrongly) decides that this
645 * bridge is transparent -- paulus
646 */
647 continue;
648 }
649 }
650
651 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
652 bus->self ? pci_name(bus->self) : "PHB",
653 bus->number, i,
654 (unsigned long long)res->start,
655 (unsigned long long)res->end);
656 pr_debug("[0x%x], parent %p (%s)\n",
657 (unsigned int)res->flags,
658 pr, (pr && pr->name) ? pr->name : "nil");
659
660 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
661 struct pci_dev *dev = bus->self;
662
663 if (request_resource(pr, res) == 0)
664 continue;
665 /*
666 * Must be a conflict with an existing entry.
667 * Move that entry (or entries) under the
668 * bridge resource and try again.
669 */
670 if (reparent_resources(pr, res) == 0)
671 continue;
672
673 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
674 pci_claim_bridge_resource(dev,
675 i + PCI_BRIDGE_RESOURCES) == 0)
676 continue;
677
678 }
679 pr_warn("PCI: Cannot allocate resource region ");
680 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
681 res->start = res->end = 0;
682 res->flags = 0;
683 }
684
685 list_for_each_entry(b, &bus->children, node)
686 pcibios_allocate_bus_resources(b);
687}
688
689static inline void alloc_resource(struct pci_dev *dev, int idx)
690{
691 struct resource *pr, *r = &dev->resource[idx];
692
693 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
694 pci_name(dev), idx,
695 (unsigned long long)r->start,
696 (unsigned long long)r->end,
697 (unsigned int)r->flags);
698
699 pr = pci_find_parent_resource(dev, r);
700 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
701 request_resource(pr, r) < 0) {
702 pr_warn("PCI: Cannot allocate resource region %d ", idx);
703 pr_cont("of device %s, will remap\n", pci_name(dev));
704 if (pr)
705 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
706 pr,
707 (unsigned long long)pr->start,
708 (unsigned long long)pr->end,
709 (unsigned int)pr->flags);
710 /* We'll assign a new address later */
711 r->flags |= IORESOURCE_UNSET;
712 r->end -= r->start;
713 r->start = 0;
714 }
715}
716
717static void __init pcibios_allocate_resources(int pass)
718{
719 struct pci_dev *dev = NULL;
720 int idx, disabled;
721 u16 command;
722 struct resource *r;
723
724 for_each_pci_dev(dev) {
725 pci_read_config_word(dev, PCI_COMMAND, &command);
726 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
727 r = &dev->resource[idx];
728 if (r->parent) /* Already allocated */
729 continue;
730 if (!r->flags || (r->flags & IORESOURCE_UNSET))
731 continue; /* Not assigned at all */
732 /* We only allocate ROMs on pass 1 just in case they
733 * have been screwed up by firmware
734 */
735 if (idx == PCI_ROM_RESOURCE)
736 disabled = 1;
737 if (r->flags & IORESOURCE_IO)
738 disabled = !(command & PCI_COMMAND_IO);
739 else
740 disabled = !(command & PCI_COMMAND_MEMORY);
741 if (pass == disabled)
742 alloc_resource(dev, idx);
743 }
744 if (pass)
745 continue;
746 r = &dev->resource[PCI_ROM_RESOURCE];
747 if (r->flags) {
748 /* Turn the ROM off, leave the resource region,
749 * but keep it unregistered.
750 */
751 u32 reg;
752 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
753 if (reg & PCI_ROM_ADDRESS_ENABLE) {
754 pr_debug("PCI: Switching off ROM of %s\n",
755 pci_name(dev));
756 r->flags &= ~IORESOURCE_ROM_ENABLE;
757 pci_write_config_dword(dev, dev->rom_base_reg,
758 reg & ~PCI_ROM_ADDRESS_ENABLE);
759 }
760 }
761 }
762}
763
764static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
765{
766 struct pci_controller *hose = pci_bus_to_host(bus);
767 resource_size_t offset;
768 struct resource *res, *pres;
769 int i;
770
771 pr_debug("Reserving legacy ranges for domain %04x\n",
772 pci_domain_nr(bus));
773
774 /* Check for IO */
775 if (!(hose->io_resource.flags & IORESOURCE_IO))
776 goto no_io;
777 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
778 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
779 BUG_ON(res == NULL);
780 res->name = "Legacy IO";
781 res->flags = IORESOURCE_IO;
782 res->start = offset;
783 res->end = (offset + 0xfff) & 0xfffffffful;
784 pr_debug("Candidate legacy IO: %pR\n", res);
785 if (request_resource(&hose->io_resource, res)) {
786 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
787 pci_domain_nr(bus), bus->number, res);
788 kfree(res);
789 }
790
791 no_io:
792 /* Check for memory */
793 offset = hose->pci_mem_offset;
794 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
795 for (i = 0; i < 3; i++) {
796 pres = &hose->mem_resources[i];
797 if (!(pres->flags & IORESOURCE_MEM))
798 continue;
799 pr_debug("hose mem res: %pR\n", pres);
800 if ((pres->start - offset) <= 0xa0000 &&
801 (pres->end - offset) >= 0xbffff)
802 break;
803 }
804 if (i >= 3)
805 return;
806 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
807 BUG_ON(res == NULL);
808 res->name = "Legacy VGA memory";
809 res->flags = IORESOURCE_MEM;
810 res->start = 0xa0000 + offset;
811 res->end = 0xbffff + offset;
812 pr_debug("Candidate VGA memory: %pR\n", res);
813 if (request_resource(pres, res)) {
814 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
815 pci_domain_nr(bus), bus->number, res);
816 kfree(res);
817 }
818}
819
820void __init pcibios_resource_survey(void)
821{
822 struct pci_bus *b;
823
824 /* Allocate and assign resources. If we re-assign everything, then
825 * we skip the allocate phase
826 */
827 list_for_each_entry(b, &pci_root_buses, node)
828 pcibios_allocate_bus_resources(b);
829
830 pcibios_allocate_resources(0);
831 pcibios_allocate_resources(1);
832
833 /* Before we start assigning unassigned resource, we try to reserve
834 * the low IO area and the VGA memory area if they intersect the
835 * bus available resources to avoid allocating things on top of them
836 */
837 list_for_each_entry(b, &pci_root_buses, node)
838 pcibios_reserve_legacy_regions(b);
839
840 /* Now proceed to assigning things that were left unassigned */
841 pr_debug("PCI: Assigning unassigned resources...\n");
842 pci_assign_unassigned_resources();
843}
844
845static void pcibios_setup_phb_resources(struct pci_controller *hose,
846 struct list_head *resources)
847{
848 unsigned long io_offset;
849 struct resource *res;
850 int i;
851
852 /* Hookup PHB IO resource */
853 res = &hose->io_resource;
854
855 /* Fixup IO space offset */
856 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
857 res->start = (res->start + io_offset) & 0xffffffffu;
858 res->end = (res->end + io_offset) & 0xffffffffu;
859
860 if (!res->flags) {
861 pr_warn("PCI: I/O resource not set for host ");
862 pr_cont("bridge %pOF (domain %d)\n",
863 hose->dn, hose->global_number);
864 /* Workaround for lack of IO resource only on 32-bit */
865 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
866 res->end = res->start + IO_SPACE_LIMIT;
867 res->flags = IORESOURCE_IO;
868 }
869 pci_add_resource_offset(resources, res,
870 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
871
872 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
873 (unsigned long long)res->start,
874 (unsigned long long)res->end,
875 (unsigned long)res->flags);
876
877 /* Hookup PHB Memory resources */
878 for (i = 0; i < 3; ++i) {
879 res = &hose->mem_resources[i];
880 if (!res->flags) {
881 if (i > 0)
882 continue;
883 pr_err("PCI: Memory resource 0 not set for ");
884 pr_cont("host bridge %pOF (domain %d)\n",
885 hose->dn, hose->global_number);
886
887 /* Workaround for lack of MEM resource only on 32-bit */
888 res->start = hose->pci_mem_offset;
889 res->end = (resource_size_t)-1LL;
890 res->flags = IORESOURCE_MEM;
891
892 }
893 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
894
895 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
896 i, (unsigned long long)res->start,
897 (unsigned long long)res->end,
898 (unsigned long)res->flags);
899 }
900
901 pr_debug("PCI: PHB MEM offset = %016llx\n",
902 (unsigned long long)hose->pci_mem_offset);
903 pr_debug("PCI: PHB IO offset = %08lx\n",
904 (unsigned long)hose->io_base_virt - _IO_BASE);
905}
906
907static void pcibios_scan_phb(struct pci_controller *hose)
908{
909 LIST_HEAD(resources);
910 struct pci_bus *bus;
911 struct device_node *node = hose->dn;
912
913 pr_debug("PCI: Scanning PHB %pOF\n", node);
914
915 pcibios_setup_phb_resources(hose, &resources);
916
917 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
918 hose->ops, hose, &resources);
919 if (bus == NULL) {
920 pr_err("Failed to create bus for PCI domain %04x\n",
921 hose->global_number);
922 pci_free_resource_list(&resources);
923 return;
924 }
925 bus->busn_res.start = hose->first_busno;
926 hose->bus = bus;
927
928 hose->last_busno = bus->busn_res.end;
929}
930
931static int __init pcibios_init(void)
932{
933 struct pci_controller *hose, *tmp;
934 int next_busno = 0;
935
936 pr_info("PCI: Probing PCI hardware\n");
937
938 /* Scan all of the recorded PCI controllers. */
939 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
940 hose->last_busno = 0xff;
941 pcibios_scan_phb(hose);
942 if (next_busno <= hose->last_busno)
943 next_busno = hose->last_busno + 1;
944 }
945 pci_bus_count = next_busno;
946
947 /* Call common code to handle resource allocation */
948 pcibios_resource_survey();
949 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
950 if (hose->bus)
951 pci_bus_add_devices(hose->bus);
952 }
953
954 return 0;
955}
956
957subsys_initcall(pcibios_init);
958
959static struct pci_controller *pci_bus_to_hose(int bus)
960{
961 struct pci_controller *hose, *tmp;
962
963 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
964 if (bus >= hose->first_busno && bus <= hose->last_busno)
965 return hose;
966 return NULL;
967}
968
969/* Provide information on locations of various I/O regions in physical
970 * memory. Do this on a per-card basis so that we choose the right
971 * root bridge.
972 * Note that the returned IO or memory base is a physical address
973 */
974
975long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
976{
977 struct pci_controller *hose;
978 long result = -EOPNOTSUPP;
979
980 hose = pci_bus_to_hose(bus);
981 if (!hose)
982 return -ENODEV;
983
984 switch (which) {
985 case IOBASE_BRIDGE_NUMBER:
986 return (long)hose->first_busno;
987 case IOBASE_MEMORY:
988 return (long)hose->pci_mem_offset;
989 case IOBASE_IO:
990 return (long)hose->io_base_phys;
991 case IOBASE_ISA_IO:
992 return (long)isa_io_base;
993 case IOBASE_ISA_MEM:
994 return (long)isa_mem_base;
995 }
996
997 return result;
998}
999
1000/*
1001 * Null PCI config access functions, for the case when we can't
1002 * find a hose.
1003 */
1004#define NULL_PCI_OP(rw, size, type) \
1005static int \
1006null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1007{ \
1008 return PCIBIOS_DEVICE_NOT_FOUND; \
1009}
1010
1011static int
1012null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1013 int len, u32 *val)
1014{
1015 return PCIBIOS_DEVICE_NOT_FOUND;
1016}
1017
1018static int
1019null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1020 int len, u32 val)
1021{
1022 return PCIBIOS_DEVICE_NOT_FOUND;
1023}
1024
1025static struct pci_ops null_pci_ops = {
1026 .read = null_read_config,
1027 .write = null_write_config,
1028};
1029
1030/*
1031 * These functions are used early on before PCI scanning is done
1032 * and all of the pci_dev and pci_bus structures have been created.
1033 */
1034static struct pci_bus *
1035fake_pci_bus(struct pci_controller *hose, int busnr)
1036{
1037 static struct pci_bus bus;
1038
1039 if (!hose)
1040 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1041
1042 bus.number = busnr;
1043 bus.sysdata = hose;
1044 bus.ops = hose ? hose->ops : &null_pci_ops;
1045 return &bus;
1046}
1047
1048#define EARLY_PCI_OP(rw, size, type) \
1049int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1050 int devfn, int offset, type value) \
1051{ \
1052 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1053 devfn, offset, value); \
1054}
1055
1056EARLY_PCI_OP(read, byte, u8 *)
1057EARLY_PCI_OP(read, word, u16 *)
1058EARLY_PCI_OP(read, dword, u32 *)
1059EARLY_PCI_OP(write, byte, u8)
1060EARLY_PCI_OP(write, word, u16)
1061EARLY_PCI_OP(write, dword, u32)
1062
1063int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1064 int cap)
1065{
1066 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1067}
arch/microblaze/pci/xilinx_pci.c+0−170
@@ -1,170 +0,0 @@
1/*
2 * PCI support for Xilinx plbv46_pci soft-core which can be used on
3 * Xilinx Virtex ML410 / ML510 boards.
4 *
5 * Copyright 2009 Roderick Colenbrander
6 * Copyright 2009 Secret Lab Technologies Ltd.
7 *
8 * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
9 * by Benjamin Herrenschmidt.
10 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17#include <linux/ioport.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/pci.h>
21#include <linux/io.h>
22
23#define XPLB_PCI_ADDR 0x10c
24#define XPLB_PCI_DATA 0x110
25#define XPLB_PCI_BUS 0x114
26
27#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
28 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
29
30static const struct of_device_id xilinx_pci_match[] = {
31 { .compatible = "xlnx,plbv46-pci-1.03.a", },
32 {}
33};
34
35/**
36 * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
37 */
38static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
39{
40 struct pci_controller *hose;
41 int i;
42
43 if (dev->devfn || dev->bus->self)
44 return;
45
46 hose = pci_bus_to_host(dev->bus);
47 if (!hose)
48 return;
49
50 if (!of_match_node(xilinx_pci_match, hose->dn))
51 return;
52
53 /* Hide the PCI host BARs from the kernel as their content doesn't
54 * fit well in the resource management
55 */
56 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
57 dev->resource[i].start = 0;
58 dev->resource[i].end = 0;
59 dev->resource[i].flags = 0;
60 }
61
62 dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
63 pci_name(dev));
64}
65DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
66
67#ifdef DEBUG
68/**
69 * xilinx_pci_exclude_device - Don't do config access for non-root bus
70 *
71 * This is a hack. Config access to any bus other than bus 0 does not
72 * currently work on the ML510 so we prevent it here.
73 */
74static int
75xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
76{
77 return (bus != 0);
78}
79
80/**
81 * xilinx_early_pci_scan - List pci config space for available devices
82 *
83 * List pci devices in very early phase.
84 */
85static void __init xilinx_early_pci_scan(struct pci_controller *hose)
86{
87 u32 bus = 0;
88 u32 val, dev, func, offset;
89
90 /* Currently we have only 2 device connected - up-to 32 devices */
91 for (dev = 0; dev < 2; dev++) {
92 /* List only first function number - up-to 8 functions */
93 for (func = 0; func < 1; func++) {
94 pr_info("%02x:%02x:%02x", bus, dev, func);
95 /* read the first 64 standardized bytes */
96 /* Up-to 192 bytes can be list of capabilities */
97 for (offset = 0; offset < 64; offset += 4) {
98 early_read_config_dword(hose, bus,
99 PCI_DEVFN(dev, func), offset, &val);
100 if (offset == 0 && val == 0xFFFFFFFF) {
101 pr_cont("\nABSENT");
102 break;
103 }
104 if (!(offset % 0x10))
105 pr_cont("\n%04x: ", offset);
106
107 pr_cont("%08x ", val);
108 }
109 pr_info("\n");
110 }
111 }
112}
113#else
114static void __init xilinx_early_pci_scan(struct pci_controller *hose)
115{
116}
117#endif
118
119/**
120 * xilinx_pci_init - Find and register a Xilinx PCI host bridge
121 */
122void __init xilinx_pci_init(void)
123{
124 struct pci_controller *hose;
125 struct resource r;
126 void __iomem *pci_reg;
127 struct device_node *pci_node;
128
129 pci_node = of_find_matching_node(NULL, xilinx_pci_match);
130 if (!pci_node)
131 return;
132
133 if (of_address_to_resource(pci_node, 0, &r)) {
134 pr_err("xilinx-pci: cannot resolve base address\n");
135 return;
136 }
137
138 hose = pcibios_alloc_controller(pci_node);
139 if (!hose) {
140 pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
141 return;
142 }
143
144 /* Setup config space */
145 setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
146 r.start + XPLB_PCI_DATA,
147 INDIRECT_TYPE_SET_CFG_TYPE);
148
149 /* According to the xilinx plbv46_pci documentation the soft-core starts
150 * a self-init when the bus master enable bit is set. Without this bit
151 * set the pci bus can't be scanned.
152 */
153 early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
154
155 /* Set the max latency timer to 255 */
156 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
157
158 /* Set the max bus number to 255, and bus/subbus no's to 0 */
159 pci_reg = of_iomap(pci_node, 0);
160 WARN_ON(!pci_reg);
161 out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
162 iounmap(pci_reg);
163
164 /* Register the host bridge with the linux kernel! */
165 pci_process_bridge_OF_ranges(hose, pci_node,
166 INDIRECT_TYPE_SET_CFG_TYPE);
167
168 pr_info("xilinx-pci: Registered PCI host bridge\n");
169 xilinx_early_pci_scan(hose);
170}