History

MIPS: uasm: Add mflo uasm instruction

It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.]

Markos Chandras committed 12 years ago

Commit 16d21a81 parent a8e897a5 files · +11 −5Browse files

Unified · Split

5 files
  1. arch/mips/include/asm/uasm.h +1 −0
  2. arch/mips/include/uapi/asm/inst.h +1 −0
  3. arch/mips/mm/uasm-micromips.c +1 −0
  4. arch/mips/mm/uasm-mips.c +1 −0
  5. arch/mips/mm/uasm.c +7 −5
arch/mips/include/asm/uasm.h+1−0
@@ -133,6 +133,7 @@ Ip_u2s3u1(_lw); · 132 unmodified lines
133Ip_u3u1u2(_lwx);133Ip_u3u1u2(_lwx);
134Ip_u1u2u3(_mfc0);134Ip_u1u2u3(_mfc0);
135Ip_u1(_mfhi);135Ip_u1(_mfhi);
136Ip_u1(_mflo);
136Ip_u1u2u3(_mtc0);137Ip_u1u2u3(_mtc0);
137Ip_u3u1u2(_mul);138Ip_u3u1u2(_mul);
138Ip_u3u1u2(_or);139Ip_u3u1u2(_or);
arch/mips/include/uapi/asm/inst.h+1−0
@@ -316,6 +316,7 @@ enum mm_32axf_minor_op { · 315 unmodified lines
316 mm_mfhi32_op = 0x035,316 mm_mfhi32_op = 0x035,
317 mm_jalr_op = 0x03c,317 mm_jalr_op = 0x03c,
318 mm_tlbr_op = 0x04d,318 mm_tlbr_op = 0x04d,
319 mm_mflo32_op = 0x075,
319 mm_jalrhb_op = 0x07c,320 mm_jalrhb_op = 0x07c,
320 mm_tlbwi_op = 0x08d,321 mm_tlbwi_op = 0x08d,
321 mm_tlbwr_op = 0x0cd,322 mm_tlbwr_op = 0x0cd,
arch/mips/mm/uasm-micromips.c+1−0
@@ -89,6 +89,7 @@ static struct insn insn_table_MM[] = { · 88 unmodified lines
89 { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },89 { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
90 { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },90 { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
91 { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },91 { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },
92 { insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },
92 { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },93 { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
93 { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },94 { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },
94 { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },95 { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
arch/mips/mm/uasm-mips.c+1−0
@@ -96,6 +96,7 @@ static struct insn insn_table[] = { · 95 unmodified lines
96 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },96 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
97 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},97 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
98 { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD },98 { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
99 { insn_mflo, M(spec_op, 0, 0, 0, 0, mflo_op), RD },
99 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},100 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
100 { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},101 { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
101 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },102 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
arch/mips/mm/uasm.c+7−5
@@ -51,11 +51,12 @@ enum opcode { · 50 unmodified lines
51 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,51 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
52 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,52 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
53 insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx,53 insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx,
54 insn_mfc0, insn_mfhi, insn_mtc0, insn_mul, insn_or, insn_ori, insn_pref,54 insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul, insn_or,
55 insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv,55 insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd,
56 insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu,56 insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra, insn_srl,
57 insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi,57 insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
58 insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield,58 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
59 insn_xori, insn_yield,
59};60};
60 61
61struct insn {62struct insn {
@@ -276,6 +277,7 @@ I_u1s2(_lui) · 214 unmodified lines
276I_u2s3u1(_lw)277I_u2s3u1(_lw)
277I_u1u2u3(_mfc0)278I_u1u2u3(_mfc0)
278I_u1(_mfhi)279I_u1(_mfhi)
280I_u1(_mflo)
279I_u1u2u3(_mtc0)281I_u1u2u3(_mtc0)
280I_u3u1u2(_mul)282I_u3u1u2(_mul)
281I_u2u1u3(_ori)283I_u2u1u3(_ori)

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