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Merge airlied/drm-next into drm-intel-next-queued

Catchup with upstream.

Rodrigo Vivi committed 9 years ago

Commit 176d5322 parents 70a84f3 f1508911590 files · +41846 −27555Browse files

Showing the changes to include/uapi (13 of 1590 files). Show all

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13 files
  1. include/uapi/drm/amdgpu_drm.h +31 −1
  2. include/uapi/drm/drm.h +41 −0
  3. include/uapi/drm/drm_mode.h +66 −0
  4. include/uapi/drm/msm_drm.h +24 −0
  5. include/uapi/drm/vc4_drm.h +19 −0
  6. include/uapi/linux/bpf.h +4 −4
  7. include/uapi/linux/dm-ioctl.h +2 −2
  8. include/uapi/linux/kfd_ioctl.h +1 −1
  9. include/uapi/linux/membarrier.h +16 −7
  10. include/uapi/linux/netfilter/xt_bpf.h +1 −0
  11. include/uapi/linux/sctp.h +1 −1
  12. include/uapi/linux/spi/spidev.h +1 −0
  13. include/uapi/linux/usb/ch9.h +1 −0
include/uapi/drm/amdgpu_drm.h+31−1
@@ -53,6 +53,7 @@ extern "C" { · 52 unmodified lines
53#define DRM_AMDGPU_WAIT_FENCES 0x1253#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x1354#define DRM_AMDGPU_VM 0x13
55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x1455#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56#define DRM_AMDGPU_SCHED 0x15
56 57
57#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)58#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
58#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)59#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -69,6 +70,7 @@ extern "C" { · 10 unmodified lines
69#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)70#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
70#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)71#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
71#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)72#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
72 74
73#define AMDGPU_GEM_DOMAIN_CPU 0x175#define AMDGPU_GEM_DOMAIN_CPU 0x1
74#define AMDGPU_GEM_DOMAIN_GTT 0x276#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -91,6 +93,8 @@ extern "C" { · 16 unmodified lines
91#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)93#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
92/* Flag that BO is always valid in this VM */94/* Flag that BO is always valid in this VM */
93#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)95#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
96/* Flag that BO sharing will be explicitly synchronized */
97#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
94 98
95struct drm_amdgpu_gem_create_in {99struct drm_amdgpu_gem_create_in {
96 /** the requested memory size */100 /** the requested memory size */
@@ -166,13 +170,22 @@ union drm_amdgpu_bo_list { · 69 unmodified lines
166/* unknown cause */170/* unknown cause */
167#define AMDGPU_CTX_UNKNOWN_RESET 3171#define AMDGPU_CTX_UNKNOWN_RESET 3
168 172
173/* Context priority level */
174#define AMDGPU_CTX_PRIORITY_UNSET -2048
175#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
176#define AMDGPU_CTX_PRIORITY_LOW -512
177#define AMDGPU_CTX_PRIORITY_NORMAL 0
178/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
179#define AMDGPU_CTX_PRIORITY_HIGH 512
180#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
181
169struct drm_amdgpu_ctx_in {182struct drm_amdgpu_ctx_in {
170 /** AMDGPU_CTX_OP_* */183 /** AMDGPU_CTX_OP_* */
171 __u32 op;184 __u32 op;
172 /** For future use, no flags defined so far */185 /** For future use, no flags defined so far */
173 __u32 flags;186 __u32 flags;
174 __u32 ctx_id;187 __u32 ctx_id;
175 __u32 _pad;188 __s32 priority;
176};189};
177 190
178union drm_amdgpu_ctx_out {191union drm_amdgpu_ctx_out {
@@ -216,6 +229,21 @@ union drm_amdgpu_vm { · 37 unmodified lines
216 struct drm_amdgpu_vm_out out;229 struct drm_amdgpu_vm_out out;
217};230};
218 231
232/* sched ioctl */
233#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
234
235struct drm_amdgpu_sched_in {
236 /* AMDGPU_SCHED_OP_* */
237 __u32 op;
238 __u32 fd;
239 __s32 priority;
240 __u32 flags;
241};
242
243union drm_amdgpu_sched {
244 struct drm_amdgpu_sched_in in;
245};
246
219/*247/*
220 * This is not a reliable API and you should expect it to fail for any248 * This is not a reliable API and you should expect it to fail for any
221 * number of reasons and have fallback path that do not use userptr to249 * number of reasons and have fallback path that do not use userptr to
@@ -525,6 +553,7 @@ union drm_amdgpu_fence_to_handle { · 303 unmodified lines
525 struct {553 struct {
526 struct drm_amdgpu_fence fence;554 struct drm_amdgpu_fence fence;
527 __u32 what;555 __u32 what;
556 __u32 pad;
528 } in;557 } in;
529 struct {558 struct {
530 __u32 handle;559 __u32 handle;
@@ -629,6 +658,7 @@ struct drm_amdgpu_cs_chunk_data { · 98 unmodified lines
629 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7658 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
630/* Number of VRAM page faults on CPU access. */659/* Number of VRAM page faults on CPU access. */
631#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E660#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
661#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
632 662
633#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0663#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
634#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff664#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
include/uapi/drm/drm.h+41−0
@@ -737,6 +737,28 @@ struct drm_syncobj_array { · 736 unmodified lines
737 __u32 pad;737 __u32 pad;
738};738};
739 739
740/* Query current scanout sequence number */
741struct drm_crtc_get_sequence {
742 __u32 crtc_id; /* requested crtc_id */
743 __u32 active; /* return: crtc output is active */
744 __u64 sequence; /* return: most recent vblank sequence */
745 __s64 sequence_ns; /* return: most recent time of first pixel out */
746};
747
748/* Queue event to be delivered at specified sequence. Time stamp marks
749 * when the first pixel of the refresh cycle leaves the display engine
750 * for the display
751 */
752#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */
753#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */
754
755struct drm_crtc_queue_sequence {
756 __u32 crtc_id;
757 __u32 flags;
758 __u64 sequence; /* on input, target sequence. on output, actual sequence */
759 __u64 user_data; /* user data passed to event */
760};
761
740#if defined(__cplusplus)762#if defined(__cplusplus)
741}763}
742#endif764#endif
@@ -819,6 +841,9 @@ extern "C" { · 76 unmodified lines
819 841
820#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)842#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
821 843
844#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
845#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
846
822#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)847#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
823 848
824#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)849#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
@@ -863,6 +888,11 @@ extern "C" { · 38 unmodified lines
863#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)888#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
864#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)889#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
865 890
891#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)
892#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)
893#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
894#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
895
866/**896/**
867 * Device specific ioctls should only be in their respective headers897 * Device specific ioctls should only be in their respective headers
868 * The device specific ioctl range is from 0x40 to 0x9f.898 * The device specific ioctl range is from 0x40 to 0x9f.
@@ -893,6 +923,7 @@ struct drm_event { · 24 unmodified lines
893 923
894#define DRM_EVENT_VBLANK 0x01924#define DRM_EVENT_VBLANK 0x01
895#define DRM_EVENT_FLIP_COMPLETE 0x02925#define DRM_EVENT_FLIP_COMPLETE 0x02
926#define DRM_EVENT_CRTC_SEQUENCE 0x03
896 927
897struct drm_event_vblank {928struct drm_event_vblank {
898 struct drm_event base;929 struct drm_event base;
@@ -903,6 +934,16 @@ struct drm_event_vblank { · 4 unmodified lines
903 __u32 crtc_id; /* 0 on older kernels that do not support this */934 __u32 crtc_id; /* 0 on older kernels that do not support this */
904};935};
905 936
937/* Event delivered at sequence. Time stamp marks when the first pixel
938 * of the refresh cycle leaves the display engine for the display
939 */
940struct drm_event_crtc_sequence {
941 struct drm_event base;
942 __u64 user_data;
943 __s64 time_ns;
944 __u64 sequence;
945};
946
906/* typedef area */947/* typedef area */
907#ifndef __KERNEL__948#ifndef __KERNEL__
908typedef struct drm_clip_rect drm_clip_rect_t;949typedef struct drm_clip_rect drm_clip_rect_t;
include/uapi/drm/drm_mode.h+66−0
@@ -782,6 +782,72 @@ struct drm_mode_destroy_blob { · 781 unmodified lines
782 __u32 blob_id;782 __u32 blob_id;
783};783};
784 784
785/**
786 * Lease mode resources, creating another drm_master.
787 */
788struct drm_mode_create_lease {
789 /** Pointer to array of object ids (__u32) */
790 __u64 object_ids;
791 /** Number of object ids */
792 __u32 object_count;
793 /** flags for new FD (O_CLOEXEC, etc) */
794 __u32 flags;
795
796 /** Return: unique identifier for lessee. */
797 __u32 lessee_id;
798 /** Return: file descriptor to new drm_master file */
799 __u32 fd;
800};
801
802/**
803 * List lesses from a drm_master
804 */
805struct drm_mode_list_lessees {
806 /** Number of lessees.
807 * On input, provides length of the array.
808 * On output, provides total number. No
809 * more than the input number will be written
810 * back, so two calls can be used to get
811 * the size and then the data.
812 */
813 __u32 count_lessees;
814 __u32 pad;
815
816 /** Pointer to lessees.
817 * pointer to __u64 array of lessee ids
818 */
819 __u64 lessees_ptr;
820};
821
822/**
823 * Get leased objects
824 */
825struct drm_mode_get_lease {
826 /** Number of leased objects.
827 * On input, provides length of the array.
828 * On output, provides total number. No
829 * more than the input number will be written
830 * back, so two calls can be used to get
831 * the size and then the data.
832 */
833 __u32 count_objects;
834 __u32 pad;
835
836 /** Pointer to objects.
837 * pointer to __u32 array of object ids
838 */
839 __u64 objects_ptr;
840};
841
842/**
843 * Revoke lease
844 */
845struct drm_mode_revoke_lease {
846 /** Unique ID of lessee
847 */
848 __u32 lessee_id;
849};
850
785#if defined(__cplusplus)851#if defined(__cplusplus)
786}852}
787#endif853#endif
include/uapi/drm/msm_drm.h+24−0
@@ -73,6 +73,7 @@ struct drm_msm_timespec { · 72 unmodified lines
73#define MSM_PARAM_MAX_FREQ 0x0473#define MSM_PARAM_MAX_FREQ 0x04
74#define MSM_PARAM_TIMESTAMP 0x0574#define MSM_PARAM_TIMESTAMP 0x05
75#define MSM_PARAM_GMEM_BASE 0x0675#define MSM_PARAM_GMEM_BASE 0x06
76#define MSM_PARAM_NR_RINGS 0x07
76 77
77struct drm_msm_param {78struct drm_msm_param {
78 __u32 pipe; /* in, MSM_PIPE_x */79 __u32 pipe; /* in, MSM_PIPE_x */
@@ -218,6 +219,7 @@ struct drm_msm_gem_submit { · 139 unmodified lines
218 __u64 bos; /* in, ptr to array of submit_bo's */219 __u64 bos; /* in, ptr to array of submit_bo's */
219 __u64 cmds; /* in, ptr to array of submit_cmd's */220 __u64 cmds; /* in, ptr to array of submit_cmd's */
220 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */221 __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
222 __u32 queueid; /* in, submitqueue id */
221};223};
222 224
223/* The normal way to synchronize with the GPU is just to CPU_PREP on225/* The normal way to synchronize with the GPU is just to CPU_PREP on
@@ -231,6 +233,7 @@ struct drm_msm_wait_fence { · 7 unmodified lines
231 __u32 fence; /* in */233 __u32 fence; /* in */
232 __u32 pad;234 __u32 pad;
233 struct drm_msm_timespec timeout; /* in */235 struct drm_msm_timespec timeout; /* in */
236 __u32 queueid; /* in, submitqueue id */
234};237};
235 238
236/* madvise provides a way to tell the kernel in case a buffers contents239/* madvise provides a way to tell the kernel in case a buffers contents
@@ -254,6 +257,20 @@ struct drm_msm_gem_madvise { · 17 unmodified lines
254 __u32 retained; /* out, whether backing store still exists */257 __u32 retained; /* out, whether backing store still exists */
255};258};
256 259
260/*
261 * Draw queues allow the user to set specific submission parameter. Command
262 * submissions specify a specific submitqueue to use. ID 0 is reserved for
263 * backwards compatibility as a "default" submitqueue
264 */
265
266#define MSM_SUBMITQUEUE_FLAGS (0)
267
268struct drm_msm_submitqueue {
269 __u32 flags; /* in, MSM_SUBMITQUEUE_x */
270 __u32 prio; /* in, Priority level */
271 __u32 id; /* out, identifier */
272};
273
257#define DRM_MSM_GET_PARAM 0x00274#define DRM_MSM_GET_PARAM 0x00
258/* placeholder:275/* placeholder:
259#define DRM_MSM_SET_PARAM 0x01276#define DRM_MSM_SET_PARAM 0x01
@@ -265,6 +282,11 @@ struct drm_msm_gem_madvise { · 5 unmodified lines
265#define DRM_MSM_GEM_SUBMIT 0x06282#define DRM_MSM_GEM_SUBMIT 0x06
266#define DRM_MSM_WAIT_FENCE 0x07283#define DRM_MSM_WAIT_FENCE 0x07
267#define DRM_MSM_GEM_MADVISE 0x08284#define DRM_MSM_GEM_MADVISE 0x08
285/* placeholder:
286#define DRM_MSM_GEM_SVM_NEW 0x09
287 */
288#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
289#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
268 290
269#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)291#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
270#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)292#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
@@ -274,6 +296,8 @@ struct drm_msm_gem_madvise { · 3 unmodified lines
274#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)296#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
275#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)297#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
276#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)298#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
299#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
300#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
277 301
278#if defined(__cplusplus)302#if defined(__cplusplus)
279}303}
include/uapi/drm/vc4_drm.h+19−0
@@ -41,6 +41,7 @@ extern "C" { · 40 unmodified lines
41#define DRM_VC4_SET_TILING 0x0841#define DRM_VC4_SET_TILING 0x08
42#define DRM_VC4_GET_TILING 0x0942#define DRM_VC4_GET_TILING 0x09
43#define DRM_VC4_LABEL_BO 0x0a43#define DRM_VC4_LABEL_BO 0x0a
44#define DRM_VC4_GEM_MADVISE 0x0b
44 45
45#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)46#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
46#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)47#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
@@ -53,6 +54,7 @@ extern "C" { · 6 unmodified lines
53#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)54#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
54#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)55#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
55#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)56#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
57#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
56 58
57struct drm_vc4_submit_rcl_surface {59struct drm_vc4_submit_rcl_surface {
58 __u32 hindex; /* Handle index, or ~0 if not present. */60 __u32 hindex; /* Handle index, or ~0 if not present. */
@@ -305,6 +307,7 @@ struct drm_vc4_get_hang_state { · 246 unmodified lines
305#define DRM_VC4_PARAM_SUPPORTS_ETC1 4307#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
306#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5308#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
307#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6309#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
310#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7
308 311
309struct drm_vc4_get_param {312struct drm_vc4_get_param {
310 __u32 param;313 __u32 param;
@@ -333,6 +336,22 @@ struct drm_vc4_label_bo { · 22 unmodified lines
333 __u64 name;336 __u64 name;
334};337};
335 338
339/*
340 * States prefixed with '__' are internal states and cannot be passed to the
341 * DRM_IOCTL_VC4_GEM_MADVISE ioctl.
342 */
343#define VC4_MADV_WILLNEED 0
344#define VC4_MADV_DONTNEED 1
345#define __VC4_MADV_PURGED 2
346#define __VC4_MADV_NOTSUPP 3
347
348struct drm_vc4_gem_madvise {
349 __u32 handle;
350 __u32 madv;
351 __u32 retained;
352 __u32 pad;
353};
354
336#if defined(__cplusplus)355#if defined(__cplusplus)
337}356}
338#endif357#endif
include/uapi/linux/bpf.h+4−4
@@ -312,7 +312,7 @@ union bpf_attr { · 311 unmodified lines
312 * jump into another BPF program312 * jump into another BPF program
313 * @ctx: context pointer passed to next program313 * @ctx: context pointer passed to next program
314 * @prog_array_map: pointer to map which type is BPF_MAP_TYPE_PROG_ARRAY314 * @prog_array_map: pointer to map which type is BPF_MAP_TYPE_PROG_ARRAY
315 * @index: index inside array that selects specific program to run315 * @index: 32-bit index inside array that selects specific program to run
316 * Return: 0 on success or negative error316 * Return: 0 on success or negative error
317 *317 *
318 * int bpf_clone_redirect(skb, ifindex, flags)318 * int bpf_clone_redirect(skb, ifindex, flags)
@@ -575,7 +575,7 @@ union bpf_attr { · 256 unmodified lines
575 * @map: pointer to sockmap575 * @map: pointer to sockmap
576 * @key: key to lookup sock in map576 * @key: key to lookup sock in map
577 * @flags: reserved for future use577 * @flags: reserved for future use
578 * Return: SK_REDIRECT578 * Return: SK_PASS
579 *579 *
580 * int bpf_sock_map_update(skops, map, key, flags)580 * int bpf_sock_map_update(skops, map, key, flags)
581 * @skops: pointer to bpf_sock_ops581 * @skops: pointer to bpf_sock_ops
@@ -786,8 +786,8 @@ struct xdp_md { · 204 unmodified lines
786};786};
787 787
788enum sk_action {788enum sk_action {
789 SK_ABORTED = 0,789 SK_DROP = 0,
790 SK_DROP,790 SK_PASS,
791 SK_REDIRECT,791 SK_REDIRECT,
792};792};
793 793
include/uapi/linux/dm-ioctl.h+2−2
@@ -269,9 +269,9 @@ enum { · 268 unmodified lines
269#define DM_DEV_SET_GEOMETRY _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl)269#define DM_DEV_SET_GEOMETRY _IOWR(DM_IOCTL, DM_DEV_SET_GEOMETRY_CMD, struct dm_ioctl)
270 270
271#define DM_VERSION_MAJOR 4271#define DM_VERSION_MAJOR 4
272#define DM_VERSION_MINOR 36272#define DM_VERSION_MINOR 37
273#define DM_VERSION_PATCHLEVEL 0273#define DM_VERSION_PATCHLEVEL 0
274#define DM_VERSION_EXTRA "-ioctl (2017-06-09)"274#define DM_VERSION_EXTRA "-ioctl (2017-09-20)"
275 275
276/* Status bits */276/* Status bits */
277#define DM_READONLY_FLAG (1 << 0) /* In/Out */277#define DM_READONLY_FLAG (1 << 0) /* In/Out */
include/uapi/linux/kfd_ioctl.h+1−1
@@ -169,7 +169,7 @@ struct kfd_ioctl_dbg_wave_control_args { · 168 unmodified lines
169#define KFD_IOC_WAIT_RESULT_TIMEOUT 1169#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
170#define KFD_IOC_WAIT_RESULT_FAIL 2170#define KFD_IOC_WAIT_RESULT_FAIL 2
171 171
172#define KFD_SIGNAL_EVENT_LIMIT 256172#define KFD_SIGNAL_EVENT_LIMIT 4096
173 173
174struct kfd_ioctl_create_event_args {174struct kfd_ioctl_create_event_args {
175 __u64 event_page_offset; /* from KFD */175 __u64 event_page_offset; /* from KFD */
include/uapi/linux/membarrier.h+16−7
@@ -52,21 +52,30 @@ · 51 unmodified lines
52 * (non-running threads are de facto in such a52 * (non-running threads are de facto in such a
53 * state). This only covers threads from the53 * state). This only covers threads from the
54 * same processes as the caller thread. This54 * same processes as the caller thread. This
55 * command returns 0. The "expedited" commands55 * command returns 0 on success. The
56 * complete faster than the non-expedited ones,56 * "expedited" commands complete faster than
57 * they never block, but have the downside of57 * the non-expedited ones, they never block,
58 * causing extra overhead.58 * but have the downside of causing extra
59 * overhead. A process needs to register its
60 * intent to use the private expedited command
61 * prior to using it, otherwise this command
62 * returns -EPERM.
63 * @MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED:
64 * Register the process intent to use
65 * MEMBARRIER_CMD_PRIVATE_EXPEDITED. Always
66 * returns 0.
59 *67 *
60 * Command to be passed to the membarrier system call. The commands need to68 * Command to be passed to the membarrier system call. The commands need to
61 * be a single bit each, except for MEMBARRIER_CMD_QUERY which is assigned to69 * be a single bit each, except for MEMBARRIER_CMD_QUERY which is assigned to
62 * the value 0.70 * the value 0.
63 */71 */
64enum membarrier_cmd {72enum membarrier_cmd {
65 MEMBARRIER_CMD_QUERY = 0,73 MEMBARRIER_CMD_QUERY = 0,
66 MEMBARRIER_CMD_SHARED = (1 << 0),74 MEMBARRIER_CMD_SHARED = (1 << 0),
67 /* reserved for MEMBARRIER_CMD_SHARED_EXPEDITED (1 << 1) */75 /* reserved for MEMBARRIER_CMD_SHARED_EXPEDITED (1 << 1) */
68 /* reserved for MEMBARRIER_CMD_PRIVATE (1 << 2) */76 /* reserved for MEMBARRIER_CMD_PRIVATE (1 << 2) */
69 MEMBARRIER_CMD_PRIVATE_EXPEDITED = (1 << 3),77 MEMBARRIER_CMD_PRIVATE_EXPEDITED = (1 << 3),
78 MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED = (1 << 4),
70};79};
71 80
72#endif /* _UAPI_LINUX_MEMBARRIER_H */81#endif /* _UAPI_LINUX_MEMBARRIER_H */
include/uapi/linux/netfilter/xt_bpf.h+1−0
@@ -23,6 +23,7 @@ enum xt_bpf_modes { · 22 unmodified lines
23 XT_BPF_MODE_FD_PINNED,23 XT_BPF_MODE_FD_PINNED,
24 XT_BPF_MODE_FD_ELF,24 XT_BPF_MODE_FD_ELF,
25};25};
26#define XT_BPF_MODE_PATH_PINNED XT_BPF_MODE_FD_PINNED
26 27
27struct xt_bpf_info_v1 {28struct xt_bpf_info_v1 {
28 __u16 mode;29 __u16 mode;
include/uapi/linux/sctp.h+1−1
@@ -376,7 +376,7 @@ struct sctp_remote_error { · 375 unmodified lines
376 __u16 sre_type;376 __u16 sre_type;
377 __u16 sre_flags;377 __u16 sre_flags;
378 __u32 sre_length;378 __u32 sre_length;
379 __u16 sre_error;379 __be16 sre_error;
380 sctp_assoc_t sre_assoc_id;380 sctp_assoc_t sre_assoc_id;
381 __u8 sre_data[0];381 __u8 sre_data[0];
382};382};
include/uapi/linux/spi/spidev.h+1−0
@@ -23,6 +23,7 @@ · 22 unmodified lines
23#define SPIDEV_H23#define SPIDEV_H
24 24
25#include <linux/types.h>25#include <linux/types.h>
26#include <linux/ioctl.h>
26 27
27/* User space versions of kernel symbols for SPI clocking modes,28/* User space versions of kernel symbols for SPI clocking modes,
28 * matching <linux/spi/spi.h>29 * matching <linux/spi/spi.h>
include/uapi/linux/usb/ch9.h+1−0
@@ -780,6 +780,7 @@ struct usb_interface_assoc_descriptor { · 779 unmodified lines
780 __u8 iFunction;780 __u8 iFunction;
781} __attribute__ ((packed));781} __attribute__ ((packed));
782 782
783#define USB_DT_INTERFACE_ASSOCIATION_SIZE 8
783 784
784/*-------------------------------------------------------------------------*/785/*-------------------------------------------------------------------------*/
785 786

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