As per PCIe spec 6.0.1, add PCIe lane equalization register offset for data rates 8.0 GT/s, 32.0 GT/s and 64.0 GT/s. Also add a macro for defining data rate 64.0 GT/s physical layer capability ID.
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| @@ -750,7 +750,8 @@ · 749 unmodified lines | |||
| 750 | #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ | 750 | #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ |
| 751 | #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ | 751 | #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ |
| 752 | #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ | 752 | #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ |
| 753 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE | 753 | #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ |
| 754 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT | ||
| 754 | 755 | ||
| 755 | #define PCI_EXT_CAP_DSN_SIZEOF 12 | 756 | #define PCI_EXT_CAP_DSN_SIZEOF 12 |
| 756 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 | 757 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 |
| @@ -1144,12 +1145,21 @@ · 387 unmodified lines | |||
| 1144 | #define PCI_DLF_CAP 0x04 /* Capabilities Register */ | 1145 | #define PCI_DLF_CAP 0x04 /* Capabilities Register */ |
| 1145 | #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ | 1146 | #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ |
| 1146 | 1147 | ||
| 1148 | /* Secondary PCIe Capability 8.0 GT/s */ | ||
| 1149 | #define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ | ||
| 1150 | |||
| 1147 | /* Physical Layer 16.0 GT/s */ | 1151 | /* Physical Layer 16.0 GT/s */ |
| 1148 | #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ | 1152 | #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ |
| 1149 | #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F | 1153 | #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F |
| 1150 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 | 1154 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 |
| 1151 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 | 1155 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 |
| 1152 | 1156 | ||
| 1157 | /* Physical Layer 32.0 GT/s */ | ||
| 1158 | #define PCI_PL_32GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ | ||
| 1159 | |||
| 1160 | /* Physical Layer 64.0 GT/s */ | ||
| 1161 | #define PCI_PL_64GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ | ||
| 1162 | |||
| 1153 | /* Native PCIe Enclosure Management */ | 1163 | /* Native PCIe Enclosure Management */ |
| 1154 | #define PCI_NPEM_CAP 0x04 /* NPEM capability register */ | 1164 | #define PCI_NPEM_CAP 0x04 /* NPEM capability register */ |
| 1155 | #define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ | 1165 | #define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ |