* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (47 commits) mfd: Rename twl5031 sih modules mfd: Storage class for timberdale should be before const qualifier mfd: Remove unneeded and dangerous clearing of clientdata mfd: New AB8500 driver gpio: Fix inverted rdc321x gpio data out registers mfd: Change rdc321x resources flags to IORESOURCE_IO mfd: Move pcf50633 irq related functions to its own file. mfd: Use threaded irq for pcf50633 mfd: pcf50633-adc: Fix potential race in pcf50633_adc_sync_read mfd: Fix pcf50633 bitfield logic in interrupt handler gpio: rdc321x needs to select MFD_CORE mfd: Use menuconfig for quicker config editing ARM: AB3550 board configuration and irq for U300 mfd: AB3550 core driver mfd: AB3100 register access change to abx500 API mfd: Renamed ab3100.h to abx500.h gpio: Add TC35892 GPIO driver mfd: Add Toshiba's TC35892 MFD core mfd: Delay to mask tsc irq in max8925 mfd: Remove incorrect wm8350 kfree ...
Unified · Split
| @@ -17,6 +17,7 @@ · 16 unmodified lines | ||
| 17 | 17 | #include <linux/i2c.h> |
| 18 | 18 | #include <linux/i2c/at24.h> |
| 19 | 19 | #include <linux/i2c/pca953x.h> |
| 20 | +#include <linux/mfd/tps6507x.h> | |
| 20 | 21 | #include <linux/gpio.h> |
| 21 | 22 | #include <linux/platform_device.h> |
| 22 | 23 | #include <linux/mtd/mtd.h> |
| @@ -24,6 +25,8 @@ · 1 unmodified line | ||
| 24 | 25 | #include <linux/mtd/partitions.h> |
| 25 | 26 | #include <linux/mtd/physmap.h> |
| 26 | 27 | #include <linux/regulator/machine.h> |
| 28 | +#include <linux/mfd/tps6507x.h> | |
| 29 | +#include <linux/input/tps6507x-ts.h> | |
| 27 | 30 | |
| 28 | 31 | #include <asm/mach-types.h> |
| 29 | 32 | #include <asm/mach/arch.h> |
| @@ -533,10 +536,24 @@ struct regulator_init_data tps65070_regulator_data[] = { · 503 unmodified lines | ||
| 533 | 536 | }, |
| 534 | 537 | }; |
| 535 | 538 | |
| 539 | +static struct touchscreen_init_data tps6507x_touchscreen_data = { | |
| 540 | + .poll_period = 30, /* ms between touch samples */ | |
| 541 | + .min_pressure = 0x30, /* minimum pressure to trigger touch */ | |
| 542 | + .vref = 0, /* turn off vref when not using A/D */ | |
| 543 | + .vendor = 0, /* /sys/class/input/input?/id/vendor */ | |
| 544 | + .product = 65070, /* /sys/class/input/input?/id/product */ | |
| 545 | + .version = 0x100, /* /sys/class/input/input?/id/version */ | |
| 546 | +}; | |
| 547 | + | |
| 548 | +static struct tps6507x_board tps_board = { | |
| 549 | + .tps6507x_pmic_init_data = &tps65070_regulator_data[0], | |
| 550 | + .tps6507x_ts_init_data = &tps6507x_touchscreen_data, | |
| 551 | +}; | |
| 552 | + | |
| 536 | 553 | static struct i2c_board_info __initdata da850evm_tps65070_info[] = { |
| 537 | 554 | { |
| 538 | 555 | I2C_BOARD_INFO("tps6507x", 0x48), |
| 539 | − .platform_data = &tps65070_regulator_data[0], | |
| 556 | + .platform_data = &tps_board, | |
| 540 | 557 | }, |
| 541 | 558 | }; |
| 542 | 559 | |
| @@ -9,7 +9,7 @@ · 8 unmodified lines | ||
| 9 | 9 | */ |
| 10 | 10 | #include <linux/kernel.h> |
| 11 | 11 | #include <linux/i2c.h> |
| 12 | −#include <linux/mfd/ab3100.h> | |
| 12 | +#include <linux/mfd/abx500.h> | |
| 13 | 13 | #include <linux/regulator/machine.h> |
| 14 | 14 | #include <linux/amba/bus.h> |
| 15 | 15 | #include <mach/irqs.h> |
| @@ -46,6 +46,7 @@ · 30 unmodified lines | ||
| 46 | 46 | /* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */ |
| 47 | 47 | #define BUCK_SLEEP_SETTING 0xAC |
| 48 | 48 | |
| 49 | +#ifdef CONFIG_AB3100_CORE | |
| 49 | 50 | static struct regulator_consumer_supply supply_ldo_c[] = { |
| 50 | 51 | { |
| 51 | 52 | .dev_name = "ab3100-codec", |
| @@ -253,14 +254,68 @@ static struct ab3100_platform_data ab3100_plf_data = { · 201 unmodified lines | ||
| 253 | 254 | LDO_D_SETTING, |
| 254 | 255 | }, |
| 255 | 256 | }; |
| 257 | +#endif | |
| 258 | + | |
| 259 | +#ifdef CONFIG_AB3550_CORE | |
| 260 | +static struct abx500_init_settings ab3550_init_settings[] = { | |
| 261 | + { | |
| 262 | + .bank = 0, | |
| 263 | + .reg = AB3550_IMR1, | |
| 264 | + .setting = 0xff | |
| 265 | + }, | |
| 266 | + { | |
| 267 | + .bank = 0, | |
| 268 | + .reg = AB3550_IMR2, | |
| 269 | + .setting = 0xff | |
| 270 | + }, | |
| 271 | + { | |
| 272 | + .bank = 0, | |
| 273 | + .reg = AB3550_IMR3, | |
| 274 | + .setting = 0xff | |
| 275 | + }, | |
| 276 | + { | |
| 277 | + .bank = 0, | |
| 278 | + .reg = AB3550_IMR4, | |
| 279 | + .setting = 0xff | |
| 280 | + }, | |
| 281 | + { | |
| 282 | + .bank = 0, | |
| 283 | + .reg = AB3550_IMR5, | |
| 284 | + /* The two most significant bits are not used */ | |
| 285 | + .setting = 0x3f | |
| 286 | + }, | |
| 287 | +}; | |
| 288 | + | |
| 289 | +static struct ab3550_platform_data ab3550_plf_data = { | |
| 290 | + .irq = { | |
| 291 | + .base = IRQ_AB3550_BASE, | |
| 292 | + .count = (IRQ_AB3550_END - IRQ_AB3550_BASE + 1), | |
| 293 | + }, | |
| 294 | + .dev_data = { | |
| 295 | + }, | |
| 296 | + .init_settings = ab3550_init_settings, | |
| 297 | + .init_settings_sz = ARRAY_SIZE(ab3550_init_settings), | |
| 298 | +}; | |
| 299 | +#endif | |
| 256 | 300 | |
| 257 | 301 | static struct i2c_board_info __initdata bus0_i2c_board_info[] = { |
| 302 | +#if defined(CONFIG_AB3550_CORE) | |
| 303 | + { | |
| 304 | + .type = "ab3550", | |
| 305 | + .addr = 0x4A, | |
| 306 | + .irq = IRQ_U300_IRQ0_EXT, | |
| 307 | + .platform_data = &ab3550_plf_data, | |
| 308 | + }, | |
| 309 | +#elif defined(CONFIG_AB3100_CORE) | |
| 258 | 310 | { |
| 259 | 311 | .type = "ab3100", |
| 260 | 312 | .addr = 0x48, |
| 261 | 313 | .irq = IRQ_U300_IRQ0_EXT, |
| 262 | 314 | .platform_data = &ab3100_plf_data, |
| 263 | 315 | }, |
| 316 | +#else | |
| 317 | + { }, | |
| 318 | +#endif | |
| 264 | 319 | }; |
| 265 | 320 | |
| 266 | 321 | static struct i2c_board_info __initdata bus1_i2c_board_info[] = { |
| @@ -109,6 +109,13 @@ · 108 unmodified lines | ||
| 109 | 109 | #define U300_NR_IRQS 48 |
| 110 | 110 | #endif |
| 111 | 111 | |
| 112 | +#ifdef CONFIG_AB3550_CORE | |
| 113 | +#define IRQ_AB3550_BASE (U300_NR_IRQS) | |
| 114 | +#define IRQ_AB3550_END (IRQ_AB3550_BASE + 37) | |
| 115 | + | |
| 116 | +#define NR_IRQS (IRQ_AB3550_END + 1) | |
| 117 | +#else | |
| 112 | 118 | #define NR_IRQS U300_NR_IRQS |
| 119 | +#endif | |
| 113 | 120 | |
| 114 | 121 | #endif |
| @@ -50,7 +50,7 @@ struct pl022_config_chip ab4500_chip_info = { · 49 unmodified lines | ||
| 50 | 50 | |
| 51 | 51 | static struct spi_board_info u8500_spi_devices[] = { |
| 52 | 52 | { |
| 53 | − .modalias = "ab4500", | |
| 53 | + .modalias = "ab8500", | |
| 54 | 54 | .controller_data = &ab4500_chip_info, |
| 55 | 55 | .max_speed_hz = 12000000, |
| 56 | 56 | .bus_num = 0, |
| @@ -1,12 +0,0 @@ | ||
| 1 | −#define PFX "rdc321x: " | |
| 2 | − | |
| 3 | −/* General purpose configuration and data registers */ | |
| 4 | −#define RDC3210_CFGREG_ADDR 0x0CF8 | |
| 5 | −#define RDC3210_CFGREG_DATA 0x0CFC | |
| 6 | − | |
| 7 | −#define RDC321X_GPIO_CTRL_REG1 0x48 | |
| 8 | −#define RDC321X_GPIO_CTRL_REG2 0x84 | |
| 9 | −#define RDC321X_GPIO_DATA_REG1 0x4c | |
| 10 | −#define RDC321X_GPIO_DATA_REG2 0x88 | |
| 11 | − | |
| 12 | −#define RDC321X_MAX_GPIO 58 | |
| @@ -195,6 +195,13 @@ config GPIO_PCF857X · 194 unmodified lines | ||
| 195 | 195 | This driver provides an in-kernel interface to those GPIOs using |
| 196 | 196 | platform-neutral GPIO calls. |
| 197 | 197 | |
| 198 | +config GPIO_TC35892 | |
| 199 | + bool "TC35892 GPIOs" | |
| 200 | + depends on MFD_TC35892 | |
| 201 | + help | |
| 202 | + This enables support for the GPIOs found on the TC35892 | |
| 203 | + I/O Expander. | |
| 204 | + | |
| 198 | 205 | config GPIO_TWL4030 |
| 199 | 206 | tristate "TWL4030, TWL5030, and TPS659x0 GPIOs" |
| 200 | 207 | depends on TWL4030_CORE |
| @@ -282,6 +289,15 @@ config GPIO_TIMBERDALE · 81 unmodified lines | ||
| 282 | 289 | ---help--- |
| 283 | 290 | Add support for the GPIO IP in the timberdale FPGA. |
| 284 | 291 | |
| 292 | +config GPIO_RDC321X | |
| 293 | + tristate "RDC R-321x GPIO support" | |
| 294 | + depends on PCI && GPIOLIB | |
| 295 | + select MFD_CORE | |
| 296 | + select MFD_RDC321X | |
| 297 | + help | |
| 298 | + Support for the RDC R321x SoC GPIOs over southbridge | |
| 299 | + PCI configuration space. | |
| 300 | + | |
| 285 | 301 | comment "SPI GPIO expanders:" |
| 286 | 302 | |
| 287 | 303 | config GPIO_MAX7301 |
| @@ -317,4 +333,14 @@ config GPIO_UCB1400 · 29 unmodified lines | ||
| 317 | 333 | To compile this driver as a module, choose M here: the |
| 318 | 334 | module will be called ucb1400_gpio. |
| 319 | 335 | |
| 336 | +comment "MODULbus GPIO expanders:" | |
| 337 | + | |
| 338 | +config GPIO_JANZ_TTL | |
| 339 | + tristate "Janz VMOD-TTL Digital IO Module" | |
| 340 | + depends on MFD_JANZ_CMODIO | |
| 341 | + help | |
| 342 | + This enables support for the Janz VMOD-TTL Digital IO module. | |
| 343 | + This driver provides support for driving the pins in output | |
| 344 | + mode only. Input mode is not supported. | |
| 345 | + | |
| 320 | 346 | endif |
| @@ -16,6 +16,7 @@ obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o · 15 unmodified lines | ||
| 16 | 16 | obj-$(CONFIG_GPIO_PCA953X) += pca953x.o |
| 17 | 17 | obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o |
| 18 | 18 | obj-$(CONFIG_GPIO_PL061) += pl061.o |
| 19 | +obj-$(CONFIG_GPIO_TC35892) += tc35892-gpio.o | |
| 19 | 20 | obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o |
| 20 | 21 | obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o |
| 21 | 22 | obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o |
| @@ -27,4 +28,6 @@ obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o · 5 unmodified lines | ||
| 27 | 28 | obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o |
| 28 | 29 | obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o |
| 29 | 30 | obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o |
| 30 | −obj-$(CONFIG_GPIO_SCH) += sch_gpio.o | |
| 31 | +obj-$(CONFIG_GPIO_SCH) += sch_gpio.o | |
| 32 | +obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o | |
| 33 | +obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o | |
| @@ -0,0 +1,258 @@ | ||
| 1 | +/* | |
| 2 | + * Janz MODULbus VMOD-TTL GPIO Driver | |
| 3 | + * | |
| 4 | + * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu> | |
| 5 | + * | |
| 6 | + * This program is free software; you can redistribute it and/or modify it | |
| 7 | + * under the terms of the GNU General Public License as published by the | |
| 8 | + * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | + * option) any later version. | |
| 10 | + */ | |
| 11 | + | |
| 12 | +#include <linux/kernel.h> | |
| 13 | +#include <linux/module.h> | |
| 14 | +#include <linux/init.h> | |
| 15 | +#include <linux/interrupt.h> | |
| 16 | +#include <linux/delay.h> | |
| 17 | +#include <linux/platform_device.h> | |
| 18 | +#include <linux/io.h> | |
| 19 | +#include <linux/gpio.h> | |
| 20 | +#include <linux/slab.h> | |
| 21 | + | |
| 22 | +#include <linux/mfd/janz.h> | |
| 23 | + | |
| 24 | +#define DRV_NAME "janz-ttl" | |
| 25 | + | |
| 26 | +#define PORTA_DIRECTION 0x23 | |
| 27 | +#define PORTB_DIRECTION 0x2B | |
| 28 | +#define PORTC_DIRECTION 0x06 | |
| 29 | +#define PORTA_IOCTL 0x24 | |
| 30 | +#define PORTB_IOCTL 0x2C | |
| 31 | +#define PORTC_IOCTL 0x07 | |
| 32 | + | |
| 33 | +#define MASTER_INT_CTL 0x00 | |
| 34 | +#define MASTER_CONF_CTL 0x01 | |
| 35 | + | |
| 36 | +#define CONF_PAE (1 << 2) | |
| 37 | +#define CONF_PBE (1 << 7) | |
| 38 | +#define CONF_PCE (1 << 4) | |
| 39 | + | |
| 40 | +struct ttl_control_regs { | |
| 41 | + __be16 portc; | |
| 42 | + __be16 portb; | |
| 43 | + __be16 porta; | |
| 44 | + __be16 control; | |
| 45 | +}; | |
| 46 | + | |
| 47 | +struct ttl_module { | |
| 48 | + struct gpio_chip gpio; | |
| 49 | + | |
| 50 | + /* base address of registers */ | |
| 51 | + struct ttl_control_regs __iomem *regs; | |
| 52 | + | |
| 53 | + u8 portc_shadow; | |
| 54 | + u8 portb_shadow; | |
| 55 | + u8 porta_shadow; | |
| 56 | + | |
| 57 | + spinlock_t lock; | |
| 58 | +}; | |
| 59 | + | |
| 60 | +static int ttl_get_value(struct gpio_chip *gpio, unsigned offset) | |
| 61 | +{ | |
| 62 | + struct ttl_module *mod = dev_get_drvdata(gpio->dev); | |
| 63 | + u8 *shadow; | |
| 64 | + int ret; | |
| 65 | + | |
| 66 | + if (offset < 8) { | |
| 67 | + shadow = &mod->porta_shadow; | |
| 68 | + } else if (offset < 16) { | |
| 69 | + shadow = &mod->portb_shadow; | |
| 70 | + offset -= 8; | |
| 71 | + } else { | |
| 72 | + shadow = &mod->portc_shadow; | |
| 73 | + offset -= 16; | |
| 74 | + } | |
| 75 | + | |
| 76 | + spin_lock(&mod->lock); | |
| 77 | + ret = *shadow & (1 << offset); | |
| 78 | + spin_unlock(&mod->lock); | |
| 79 | + return ret; | |
| 80 | +} | |
| 81 | + | |
| 82 | +static void ttl_set_value(struct gpio_chip *gpio, unsigned offset, int value) | |
| 83 | +{ | |
| 84 | + struct ttl_module *mod = dev_get_drvdata(gpio->dev); | |
| 85 | + void __iomem *port; | |
| 86 | + u8 *shadow; | |
| 87 | + | |
| 88 | + if (offset < 8) { | |
| 89 | + port = &mod->regs->porta; | |
| 90 | + shadow = &mod->porta_shadow; | |
| 91 | + } else if (offset < 16) { | |
| 92 | + port = &mod->regs->portb; | |
| 93 | + shadow = &mod->portb_shadow; | |
| 94 | + offset -= 8; | |
| 95 | + } else { | |
| 96 | + port = &mod->regs->portc; | |
| 97 | + shadow = &mod->portc_shadow; | |
| 98 | + offset -= 16; | |
| 99 | + } | |
| 100 | + | |
| 101 | + spin_lock(&mod->lock); | |
| 102 | + if (value) | |
| 103 | + *shadow |= (1 << offset); | |
| 104 | + else | |
| 105 | + *shadow &= ~(1 << offset); | |
| 106 | + | |
| 107 | + iowrite16be(*shadow, port); | |
| 108 | + spin_unlock(&mod->lock); | |
| 109 | +} | |
| 110 | + | |
| 111 | +static void __devinit ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val) | |
| 112 | +{ | |
| 113 | + iowrite16be(reg, &mod->regs->control); | |
| 114 | + iowrite16be(val, &mod->regs->control); | |
| 115 | +} | |
| 116 | + | |
| 117 | +static void __devinit ttl_setup_device(struct ttl_module *mod) | |
| 118 | +{ | |
| 119 | + /* reset the device to a known state */ | |
| 120 | + iowrite16be(0x0000, &mod->regs->control); | |
| 121 | + iowrite16be(0x0001, &mod->regs->control); | |
| 122 | + iowrite16be(0x0000, &mod->regs->control); | |
| 123 | + | |
| 124 | + /* put all ports in open-drain mode */ | |
| 125 | + ttl_write_reg(mod, PORTA_IOCTL, 0x00ff); | |
| 126 | + ttl_write_reg(mod, PORTB_IOCTL, 0x00ff); | |
| 127 | + ttl_write_reg(mod, PORTC_IOCTL, 0x000f); | |
| 128 | + | |
| 129 | + /* set all ports as outputs */ | |
| 130 | + ttl_write_reg(mod, PORTA_DIRECTION, 0x0000); | |
| 131 | + ttl_write_reg(mod, PORTB_DIRECTION, 0x0000); | |
| 132 | + ttl_write_reg(mod, PORTC_DIRECTION, 0x0000); | |
| 133 | + | |
| 134 | + /* set all ports to drive zeroes */ | |
| 135 | + iowrite16be(0x0000, &mod->regs->porta); | |
| 136 | + iowrite16be(0x0000, &mod->regs->portb); | |
| 137 | + iowrite16be(0x0000, &mod->regs->portc); | |
| 138 | + | |
| 139 | + /* enable all ports */ | |
| 140 | + ttl_write_reg(mod, MASTER_CONF_CTL, CONF_PAE | CONF_PBE | CONF_PCE); | |
| 141 | +} | |
| 142 | + | |
| 143 | +static int __devinit ttl_probe(struct platform_device *pdev) | |
| 144 | +{ | |
| 145 | + struct janz_platform_data *pdata; | |
| 146 | + struct device *dev = &pdev->dev; | |
| 147 | + struct ttl_module *mod; | |
| 148 | + struct gpio_chip *gpio; | |
| 149 | + struct resource *res; | |
| 150 | + int ret; | |
| 151 | + | |
| 152 | + pdata = pdev->dev.platform_data; | |
| 153 | + if (!pdata) { | |
| 154 | + dev_err(dev, "no platform data\n"); | |
| 155 | + ret = -ENXIO; | |
| 156 | + goto out_return; | |
| 157 | + } | |
| 158 | + | |
| 159 | + mod = kzalloc(sizeof(*mod), GFP_KERNEL); | |
| 160 | + if (!mod) { | |
| 161 | + dev_err(dev, "unable to allocate private data\n"); | |
| 162 | + ret = -ENOMEM; | |
| 163 | + goto out_return; | |
| 164 | + } | |
| 165 | + | |
| 166 | + platform_set_drvdata(pdev, mod); | |
| 167 | + spin_lock_init(&mod->lock); | |
| 168 | + | |
| 169 | + /* get access to the MODULbus registers for this module */ | |
| 170 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
| 171 | + if (!res) { | |
| 172 | + dev_err(dev, "MODULbus registers not found\n"); | |
| 173 | + ret = -ENODEV; | |
| 174 | + goto out_free_mod; | |
| 175 | + } | |
| 176 | + | |
| 177 | + mod->regs = ioremap(res->start, resource_size(res)); | |
| 178 | + if (!mod->regs) { | |
| 179 | + dev_err(dev, "MODULbus registers not ioremap\n"); | |
| 180 | + ret = -ENOMEM; | |
| 181 | + goto out_free_mod; | |
| 182 | + } | |
| 183 | + | |
| 184 | + ttl_setup_device(mod); | |
| 185 | + | |
| 186 | + /* Initialize the GPIO data structures */ | |
| 187 | + gpio = &mod->gpio; | |
| 188 | + gpio->dev = &pdev->dev; | |
| 189 | + gpio->label = pdev->name; | |
| 190 | + gpio->get = ttl_get_value; | |
| 191 | + gpio->set = ttl_set_value; | |
| 192 | + gpio->owner = THIS_MODULE; | |
| 193 | + | |
| 194 | + /* request dynamic allocation */ | |
| 195 | + gpio->base = -1; | |
| 196 | + gpio->ngpio = 20; | |
| 197 | + | |
| 198 | + ret = gpiochip_add(gpio); | |
| 199 | + if (ret) { | |
| 200 | + dev_err(dev, "unable to add GPIO chip\n"); | |
| 201 | + goto out_iounmap_regs; | |
| 202 | + } | |
| 203 | + | |
| 204 | + dev_info(&pdev->dev, "module %d: registered GPIO device\n", | |
| 205 | + pdata->modno); | |
| 206 | + return 0; | |
| 207 | + | |
| 208 | +out_iounmap_regs: | |
| 209 | + iounmap(mod->regs); | |
| 210 | +out_free_mod: | |
| 211 | + kfree(mod); | |
| 212 | +out_return: | |
| 213 | + return ret; | |
| 214 | +} | |
| 215 | + | |
| 216 | +static int __devexit ttl_remove(struct platform_device *pdev) | |
| 217 | +{ | |
| 218 | + struct ttl_module *mod = platform_get_drvdata(pdev); | |
| 219 | + struct device *dev = &pdev->dev; | |
| 220 | + int ret; | |
| 221 | + | |
| 222 | + ret = gpiochip_remove(&mod->gpio); | |
| 223 | + if (ret) { | |
| 224 | + dev_err(dev, "unable to remove GPIO chip\n"); | |
| 225 | + return ret; | |
| 226 | + } | |
| 227 | + | |
| 228 | + iounmap(mod->regs); | |
| 229 | + kfree(mod); | |
| 230 | + return 0; | |
| 231 | +} | |
| 232 | + | |
| 233 | +static struct platform_driver ttl_driver = { | |
| 234 | + .driver = { | |
| 235 | + .name = DRV_NAME, | |
| 236 | + .owner = THIS_MODULE, | |
| 237 | + }, | |
| 238 | + .probe = ttl_probe, | |
| 239 | + .remove = __devexit_p(ttl_remove), | |
| 240 | +}; | |
| 241 | + | |
| 242 | +static int __init ttl_init(void) | |
| 243 | +{ | |
| 244 | + return platform_driver_register(&ttl_driver); | |
| 245 | +} | |
| 246 | + | |
| 247 | +static void __exit ttl_exit(void) | |
| 248 | +{ | |
| 249 | + platform_driver_unregister(&ttl_driver); | |
| 250 | +} | |
| 251 | + | |
| 252 | +MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>"); | |
| 253 | +MODULE_DESCRIPTION("Janz MODULbus VMOD-TTL Driver"); | |
| 254 | +MODULE_LICENSE("GPL"); | |
| 255 | +MODULE_ALIAS("platform:janz-ttl"); | |
| 256 | + | |
| 257 | +module_init(ttl_init); | |
| 258 | +module_exit(ttl_exit); | |
| @@ -0,0 +1,246 @@ | ||
| 1 | +/* | |
| 2 | + * RDC321x GPIO driver | |
| 3 | + * | |
| 4 | + * Copyright (C) 2008, Volker Weiss <dev@tintuc.de> | |
| 5 | + * Copyright (C) 2007-2010 Florian Fainelli <florian@openwrt.org> | |
| 6 | + * | |
| 7 | + * This program is free software; you can redistribute it and/or modify | |
| 8 | + * it under the terms of the GNU General Public License as published by | |
| 9 | + * the Free Software Foundation; either version 2 of the License, or | |
| 10 | + * (at your option) any later version. | |
| 11 | + * | |
| 12 | + * This program is distributed in the hope that it will be useful, | |
| 13 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | + * GNU General Public License for more details. | |
| 16 | + * | |
| 17 | + * You should have received a copy of the GNU General Public License | |
| 18 | + * along with this program; if not, write to the Free Software | |
| 19 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 20 | + * | |
| 21 | + */ | |
| 22 | +#include <linux/module.h> | |
| 23 | +#include <linux/kernel.h> | |
| 24 | +#include <linux/init.h> | |
| 25 | +#include <linux/spinlock.h> | |
| 26 | +#include <linux/platform_device.h> | |
| 27 | +#include <linux/pci.h> | |
| 28 | +#include <linux/gpio.h> | |
| 29 | +#include <linux/mfd/rdc321x.h> | |
| 30 | +#include <linux/slab.h> | |
| 31 | + | |
| 32 | +struct rdc321x_gpio { | |
| 33 | + spinlock_t lock; | |
| 34 | + struct pci_dev *sb_pdev; | |
| 35 | + u32 data_reg[2]; | |
| 36 | + int reg1_ctrl_base; | |
| 37 | + int reg1_data_base; | |
| 38 | + int reg2_ctrl_base; | |
| 39 | + int reg2_data_base; | |
| 40 | + struct gpio_chip chip; | |
| 41 | +}; | |
| 42 | + | |
| 43 | +/* read GPIO pin */ | |
| 44 | +static int rdc_gpio_get_value(struct gpio_chip *chip, unsigned gpio) | |
| 45 | +{ | |
| 46 | + struct rdc321x_gpio *gpch; | |
| 47 | + u32 value = 0; | |
| 48 | + int reg; | |
| 49 | + | |
| 50 | + gpch = container_of(chip, struct rdc321x_gpio, chip); | |
| 51 | + reg = gpio < 32 ? gpch->reg1_data_base : gpch->reg2_data_base; | |
| 52 | + | |
| 53 | + spin_lock(&gpch->lock); | |
| 54 | + pci_write_config_dword(gpch->sb_pdev, reg, | |
| 55 | + gpch->data_reg[gpio < 32 ? 0 : 1]); | |
| 56 | + pci_read_config_dword(gpch->sb_pdev, reg, &value); | |
| 57 | + spin_unlock(&gpch->lock); | |
| 58 | + | |
| 59 | + return (1 << (gpio & 0x1f)) & value ? 1 : 0; | |
| 60 | +} | |
| 61 | + | |
| 62 | +static void rdc_gpio_set_value_impl(struct gpio_chip *chip, | |
| 63 | + unsigned gpio, int value) | |
| 64 | +{ | |
| 65 | + struct rdc321x_gpio *gpch; | |
| 66 | + int reg = (gpio < 32) ? 0 : 1; | |
| 67 | + | |
| 68 | + gpch = container_of(chip, struct rdc321x_gpio, chip); | |
| 69 | + | |
| 70 | + if (value) | |
| 71 | + gpch->data_reg[reg] |= 1 << (gpio & 0x1f); | |
| 72 | + else | |
| 73 | + gpch->data_reg[reg] &= ~(1 << (gpio & 0x1f)); | |
| 74 | + | |
| 75 | + pci_write_config_dword(gpch->sb_pdev, | |
| 76 | + reg ? gpch->reg2_data_base : gpch->reg1_data_base, | |
| 77 | + gpch->data_reg[reg]); | |
| 78 | +} | |
| 79 | + | |
| 80 | +/* set GPIO pin to value */ | |
| 81 | +static void rdc_gpio_set_value(struct gpio_chip *chip, | |
| 82 | + unsigned gpio, int value) | |
| 83 | +{ | |
| 84 | + struct rdc321x_gpio *gpch; | |
| 85 | + | |
| 86 | + gpch = container_of(chip, struct rdc321x_gpio, chip); | |
| 87 | + spin_lock(&gpch->lock); | |
| 88 | + rdc_gpio_set_value_impl(chip, gpio, value); | |
| 89 | + spin_unlock(&gpch->lock); | |
| 90 | +} | |
| 91 | + | |
| 92 | +static int rdc_gpio_config(struct gpio_chip *chip, | |
| 93 | + unsigned gpio, int value) | |
| 94 | +{ | |
| 95 | + struct rdc321x_gpio *gpch; | |
| 96 | + int err; | |
| 97 | + u32 reg; | |
| 98 | + | |
| 99 | + gpch = container_of(chip, struct rdc321x_gpio, chip); | |
| 100 | + | |
| 101 | + spin_lock(&gpch->lock); | |
| 102 | + err = pci_read_config_dword(gpch->sb_pdev, gpio < 32 ? | |
| 103 | + gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, ®); | |
| 104 | + if (err) | |
| 105 | + goto unlock; | |
| 106 | + | |
| 107 | + reg |= 1 << (gpio & 0x1f); | |
| 108 | + | |
| 109 | + err = pci_write_config_dword(gpch->sb_pdev, gpio < 32 ? | |
| 110 | + gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, reg); | |
| 111 | + if (err) | |
| 112 | + goto unlock; | |
| 113 | + | |
| 114 | + rdc_gpio_set_value_impl(chip, gpio, value); | |
| 115 | + | |
| 116 | +unlock: | |
| 117 | + spin_unlock(&gpch->lock); | |
| 118 | + | |
| 119 | + return err; | |
| 120 | +} | |
| 121 | + | |
| 122 | +/* configure GPIO pin as input */ | |
| 123 | +static int rdc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
| 124 | +{ | |
| 125 | + return rdc_gpio_config(chip, gpio, 1); | |
| 126 | +} | |
| 127 | + | |
| 128 | +/* | |
| 129 | + * Cache the initial value of both GPIO data registers | |
| 130 | + */ | |
| 131 | +static int __devinit rdc321x_gpio_probe(struct platform_device *pdev) | |
| 132 | +{ | |
| 133 | + int err; | |
| 134 | + struct resource *r; | |
| 135 | + struct rdc321x_gpio *rdc321x_gpio_dev; | |
| 136 | + struct rdc321x_gpio_pdata *pdata; | |
| 137 | + | |
| 138 | + pdata = pdev->dev.platform_data; | |
| 139 | + if (!pdata) { | |
| 140 | + dev_err(&pdev->dev, "no platform data supplied\n"); | |
| 141 | + return -ENODEV; | |
| 142 | + } | |
| 143 | + | |
| 144 | + rdc321x_gpio_dev = kzalloc(sizeof(struct rdc321x_gpio), GFP_KERNEL); | |
| 145 | + if (!rdc321x_gpio_dev) { | |
| 146 | + dev_err(&pdev->dev, "failed to allocate private data\n"); | |
| 147 | + return -ENOMEM; | |
| 148 | + } | |
| 149 | + | |
| 150 | + r = platform_get_resource_byname(pdev, IORESOURCE_IO, "gpio-reg1"); | |
| 151 | + if (!r) { | |
| 152 | + dev_err(&pdev->dev, "failed to get gpio-reg1 resource\n"); | |
| 153 | + err = -ENODEV; | |
| 154 | + goto out_free; | |
| 155 | + } | |
| 156 | + | |
| 157 | + spin_lock_init(&rdc321x_gpio_dev->lock); | |
| 158 | + rdc321x_gpio_dev->sb_pdev = pdata->sb_pdev; | |
| 159 | + rdc321x_gpio_dev->reg1_ctrl_base = r->start; | |
| 160 | + rdc321x_gpio_dev->reg1_data_base = r->start + 0x4; | |
| 161 | + | |
| 162 | + r = platform_get_resource_byname(pdev, IORESOURCE_IO, "gpio-reg2"); | |
| 163 | + if (!r) { | |
| 164 | + dev_err(&pdev->dev, "failed to get gpio-reg2 resource\n"); | |
| 165 | + err = -ENODEV; | |
| 166 | + goto out_free; | |
| 167 | + } | |
| 168 | + | |
| 169 | + rdc321x_gpio_dev->reg2_ctrl_base = r->start; | |
| 170 | + rdc321x_gpio_dev->reg2_data_base = r->start + 0x4; | |
| 171 | + | |
| 172 | + rdc321x_gpio_dev->chip.label = "rdc321x-gpio"; | |
| 173 | + rdc321x_gpio_dev->chip.direction_input = rdc_gpio_direction_input; | |
| 174 | + rdc321x_gpio_dev->chip.direction_output = rdc_gpio_config; | |
| 175 | + rdc321x_gpio_dev->chip.get = rdc_gpio_get_value; | |
| 176 | + rdc321x_gpio_dev->chip.set = rdc_gpio_set_value; | |
| 177 | + rdc321x_gpio_dev->chip.base = 0; | |
| 178 | + rdc321x_gpio_dev->chip.ngpio = pdata->max_gpios; | |
| 179 | + | |
| 180 | + platform_set_drvdata(pdev, rdc321x_gpio_dev); | |
| 181 | + | |
| 182 | + /* This might not be, what others (BIOS, bootloader, etc.) | |
| 183 | + wrote to these registers before, but it's a good guess. Still | |
| 184 | + better than just using 0xffffffff. */ | |
| 185 | + err = pci_read_config_dword(rdc321x_gpio_dev->sb_pdev, | |
| 186 | + rdc321x_gpio_dev->reg1_data_base, | |
| 187 | + &rdc321x_gpio_dev->data_reg[0]); | |
| 188 | + if (err) | |
| 189 | + goto out_drvdata; | |
| 190 | + | |
| 191 | + err = pci_read_config_dword(rdc321x_gpio_dev->sb_pdev, | |
| 192 | + rdc321x_gpio_dev->reg2_data_base, | |
| 193 | + &rdc321x_gpio_dev->data_reg[1]); | |
| 194 | + if (err) | |
| 195 | + goto out_drvdata; | |
| 196 | + | |
| 197 | + dev_info(&pdev->dev, "registering %d GPIOs\n", | |
| 198 | + rdc321x_gpio_dev->chip.ngpio); | |
| 199 | + return gpiochip_add(&rdc321x_gpio_dev->chip); | |
| 200 | + | |
| 201 | +out_drvdata: | |
| 202 | + platform_set_drvdata(pdev, NULL); | |
| 203 | +out_free: | |
| 204 | + kfree(rdc321x_gpio_dev); | |
| 205 | + return err; | |
| 206 | +} | |
| 207 | + | |
| 208 | +static int __devexit rdc321x_gpio_remove(struct platform_device *pdev) | |
| 209 | +{ | |
| 210 | + int ret; | |
| 211 | + struct rdc321x_gpio *rdc321x_gpio_dev = platform_get_drvdata(pdev); | |
| 212 | + | |
| 213 | + ret = gpiochip_remove(&rdc321x_gpio_dev->chip); | |
| 214 | + if (ret) | |
| 215 | + dev_err(&pdev->dev, "failed to unregister chip\n"); | |
| 216 | + | |
| 217 | + kfree(rdc321x_gpio_dev); | |
| 218 | + platform_set_drvdata(pdev, NULL); | |
| 219 | + | |
| 220 | + return ret; | |
| 221 | +} | |
| 222 | + | |
| 223 | +static struct platform_driver rdc321x_gpio_driver = { | |
| 224 | + .driver.name = "rdc321x-gpio", | |
| 225 | + .driver.owner = THIS_MODULE, | |
| 226 | + .probe = rdc321x_gpio_probe, | |
| 227 | + .remove = __devexit_p(rdc321x_gpio_remove), | |
| 228 | +}; | |
| 229 | + | |
| 230 | +static int __init rdc321x_gpio_init(void) | |
| 231 | +{ | |
| 232 | + return platform_driver_register(&rdc321x_gpio_driver); | |
| 233 | +} | |
| 234 | + | |
| 235 | +static void __exit rdc321x_gpio_exit(void) | |
| 236 | +{ | |
| 237 | + platform_driver_unregister(&rdc321x_gpio_driver); | |
| 238 | +} | |
| 239 | + | |
| 240 | +module_init(rdc321x_gpio_init); | |
| 241 | +module_exit(rdc321x_gpio_exit); | |
| 242 | + | |
| 243 | +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); | |
| 244 | +MODULE_DESCRIPTION("RDC321x GPIO driver"); | |
| 245 | +MODULE_LICENSE("GPL"); | |
| 246 | +MODULE_ALIAS("platform:rdc321x-gpio"); | |
| @@ -0,0 +1,381 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | + * | |
| 4 | + * License Terms: GNU General Public License, version 2 | |
| 5 | + * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson | |
| 6 | + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#include <linux/module.h> | |
| 10 | +#include <linux/init.h> | |
| 11 | +#include <linux/platform_device.h> | |
| 12 | +#include <linux/slab.h> | |
| 13 | +#include <linux/gpio.h> | |
| 14 | +#include <linux/irq.h> | |
| 15 | +#include <linux/interrupt.h> | |
| 16 | +#include <linux/mfd/tc35892.h> | |
| 17 | + | |
| 18 | +/* | |
| 19 | + * These registers are modified under the irq bus lock and cached to avoid | |
| 20 | + * unnecessary writes in bus_sync_unlock. | |
| 21 | + */ | |
| 22 | +enum { REG_IBE, REG_IEV, REG_IS, REG_IE }; | |
| 23 | + | |
| 24 | +#define CACHE_NR_REGS 4 | |
| 25 | +#define CACHE_NR_BANKS 3 | |
| 26 | + | |
| 27 | +struct tc35892_gpio { | |
| 28 | + struct gpio_chip chip; | |
| 29 | + struct tc35892 *tc35892; | |
| 30 | + struct device *dev; | |
| 31 | + struct mutex irq_lock; | |
| 32 | + | |
| 33 | + int irq_base; | |
| 34 | + | |
| 35 | + /* Caches of interrupt control registers for bus_lock */ | |
| 36 | + u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
| 37 | + u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
| 38 | +}; | |
| 39 | + | |
| 40 | +static inline struct tc35892_gpio *to_tc35892_gpio(struct gpio_chip *chip) | |
| 41 | +{ | |
| 42 | + return container_of(chip, struct tc35892_gpio, chip); | |
| 43 | +} | |
| 44 | + | |
| 45 | +static int tc35892_gpio_get(struct gpio_chip *chip, unsigned offset) | |
| 46 | +{ | |
| 47 | + struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); | |
| 48 | + struct tc35892 *tc35892 = tc35892_gpio->tc35892; | |
| 49 | + u8 reg = TC35892_GPIODATA0 + (offset / 8) * 2; | |
| 50 | + u8 mask = 1 << (offset % 8); | |
| 51 | + int ret; | |
| 52 | + | |
| 53 | + ret = tc35892_reg_read(tc35892, reg); | |
| 54 | + if (ret < 0) | |
| 55 | + return ret; | |
| 56 | + | |
| 57 | + return ret & mask; | |
| 58 | +} | |
| 59 | + | |
| 60 | +static void tc35892_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
| 61 | +{ | |
| 62 | + struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); | |
| 63 | + struct tc35892 *tc35892 = tc35892_gpio->tc35892; | |
| 64 | + u8 reg = TC35892_GPIODATA0 + (offset / 8) * 2; | |
| 65 | + unsigned pos = offset % 8; | |
| 66 | + u8 data[] = {!!val << pos, 1 << pos}; | |
| 67 | + | |
| 68 | + tc35892_block_write(tc35892, reg, ARRAY_SIZE(data), data); | |
| 69 | +} | |
| 70 | + | |
| 71 | +static int tc35892_gpio_direction_output(struct gpio_chip *chip, | |
| 72 | + unsigned offset, int val) | |
| 73 | +{ | |
| 74 | + struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); | |
| 75 | + struct tc35892 *tc35892 = tc35892_gpio->tc35892; | |
| 76 | + u8 reg = TC35892_GPIODIR0 + offset / 8; | |
| 77 | + unsigned pos = offset % 8; | |
| 78 | + | |
| 79 | + tc35892_gpio_set(chip, offset, val); | |
| 80 | + | |
| 81 | + return tc35892_set_bits(tc35892, reg, 1 << pos, 1 << pos); | |
| 82 | +} | |
| 83 | + | |
| 84 | +static int tc35892_gpio_direction_input(struct gpio_chip *chip, | |
| 85 | + unsigned offset) | |
| 86 | +{ | |
| 87 | + struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); | |
| 88 | + struct tc35892 *tc35892 = tc35892_gpio->tc35892; | |
| 89 | + u8 reg = TC35892_GPIODIR0 + offset / 8; | |
| 90 | + unsigned pos = offset % 8; | |
| 91 | + | |
| 92 | + return tc35892_set_bits(tc35892, reg, 1 << pos, 0); | |
| 93 | +} | |
| 94 | + | |
| 95 | +static int tc35892_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
| 96 | +{ | |
| 97 | + struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); | |
| 98 | + | |
| 99 | + return tc35892_gpio->irq_base + offset; | |
| 100 | +} | |
| 101 | + | |
| 102 | +static struct gpio_chip template_chip = { | |
| 103 | + .label = "tc35892", | |
| 104 | + .owner = THIS_MODULE, | |
| 105 | + .direction_input = tc35892_gpio_direction_input, | |
| 106 | + .get = tc35892_gpio_get, | |
| 107 | + .direction_output = tc35892_gpio_direction_output, | |
| 108 | + .set = tc35892_gpio_set, | |
| 109 | + .to_irq = tc35892_gpio_to_irq, | |
| 110 | + .can_sleep = 1, | |
| 111 | +}; | |
| 112 | + | |
| 113 | +static int tc35892_gpio_irq_set_type(unsigned int irq, unsigned int type) | |
| 114 | +{ | |
| 115 | + struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); | |
| 116 | + int offset = irq - tc35892_gpio->irq_base; | |
| 117 | + int regoffset = offset / 8; | |
| 118 | + int mask = 1 << (offset % 8); | |
| 119 | + | |
| 120 | + if (type == IRQ_TYPE_EDGE_BOTH) { | |
| 121 | + tc35892_gpio->regs[REG_IBE][regoffset] |= mask; | |
| 122 | + return 0; | |
| 123 | + } | |
| 124 | + | |
| 125 | + tc35892_gpio->regs[REG_IBE][regoffset] &= ~mask; | |
| 126 | + | |
| 127 | + if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) | |
| 128 | + tc35892_gpio->regs[REG_IS][regoffset] |= mask; | |
| 129 | + else | |
| 130 | + tc35892_gpio->regs[REG_IS][regoffset] &= ~mask; | |
| 131 | + | |
| 132 | + if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) | |
| 133 | + tc35892_gpio->regs[REG_IEV][regoffset] |= mask; | |
| 134 | + else | |
| 135 | + tc35892_gpio->regs[REG_IEV][regoffset] &= ~mask; | |
| 136 | + | |
| 137 | + return 0; | |
| 138 | +} | |
| 139 | + | |
| 140 | +static void tc35892_gpio_irq_lock(unsigned int irq) | |
| 141 | +{ | |
| 142 | + struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); | |
| 143 | + | |
| 144 | + mutex_lock(&tc35892_gpio->irq_lock); | |
| 145 | +} | |
| 146 | + | |
| 147 | +static void tc35892_gpio_irq_sync_unlock(unsigned int irq) | |
| 148 | +{ | |
| 149 | + struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); | |
| 150 | + struct tc35892 *tc35892 = tc35892_gpio->tc35892; | |
| 151 | + static const u8 regmap[] = { | |
| 152 | + [REG_IBE] = TC35892_GPIOIBE0, | |
| 153 | + [REG_IEV] = TC35892_GPIOIEV0, | |
| 154 | + [REG_IS] = TC35892_GPIOIS0, | |
| 155 | + [REG_IE] = TC35892_GPIOIE0, | |
| 156 | + }; | |
| 157 | + int i, j; | |
| 158 | + | |
| 159 | + for (i = 0; i < CACHE_NR_REGS; i++) { | |
| 160 | + for (j = 0; j < CACHE_NR_BANKS; j++) { | |
| 161 | + u8 old = tc35892_gpio->oldregs[i][j]; | |
| 162 | + u8 new = tc35892_gpio->regs[i][j]; | |
| 163 | + | |
| 164 | + if (new == old) | |
| 165 | + continue; | |
| 166 | + | |
| 167 | + tc35892_gpio->oldregs[i][j] = new; | |
| 168 | + tc35892_reg_write(tc35892, regmap[i] + j * 8, new); | |
| 169 | + } | |
| 170 | + } | |
| 171 | + | |
| 172 | + mutex_unlock(&tc35892_gpio->irq_lock); | |
| 173 | +} | |
| 174 | + | |
| 175 | +static void tc35892_gpio_irq_mask(unsigned int irq) | |
| 176 | +{ | |
| 177 | + struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); | |
| 178 | + int offset = irq - tc35892_gpio->irq_base; | |
| 179 | + int regoffset = offset / 8; | |
| 180 | + int mask = 1 << (offset % 8); | |
| 181 | + | |
| 182 | + tc35892_gpio->regs[REG_IE][regoffset] &= ~mask; | |
| 183 | +} | |
| 184 | + | |
| 185 | +static void tc35892_gpio_irq_unmask(unsigned int irq) | |
| 186 | +{ | |
| 187 | + struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); | |
| 188 | + int offset = irq - tc35892_gpio->irq_base; | |
| 189 | + int regoffset = offset / 8; | |
| 190 | + int mask = 1 << (offset % 8); | |
| 191 | + | |
| 192 | + tc35892_gpio->regs[REG_IE][regoffset] |= mask; | |
| 193 | +} | |
| 194 | + | |
| 195 | +static struct irq_chip tc35892_gpio_irq_chip = { | |
| 196 | + .name = "tc35892-gpio", | |
| 197 | + .bus_lock = tc35892_gpio_irq_lock, | |
| 198 | + .bus_sync_unlock = tc35892_gpio_irq_sync_unlock, | |
| 199 | + .mask = tc35892_gpio_irq_mask, | |
| 200 | + .unmask = tc35892_gpio_irq_unmask, | |
| 201 | + .set_type = tc35892_gpio_irq_set_type, | |
| 202 | +}; | |
| 203 | + | |
| 204 | +static irqreturn_t tc35892_gpio_irq(int irq, void *dev) | |
| 205 | +{ | |
| 206 | + struct tc35892_gpio *tc35892_gpio = dev; | |
| 207 | + struct tc35892 *tc35892 = tc35892_gpio->tc35892; | |
| 208 | + u8 status[CACHE_NR_BANKS]; | |
| 209 | + int ret; | |
| 210 | + int i; | |
| 211 | + | |
| 212 | + ret = tc35892_block_read(tc35892, TC35892_GPIOMIS0, | |
| 213 | + ARRAY_SIZE(status), status); | |
| 214 | + if (ret < 0) | |
| 215 | + return IRQ_NONE; | |
| 216 | + | |
| 217 | + for (i = 0; i < ARRAY_SIZE(status); i++) { | |
| 218 | + unsigned int stat = status[i]; | |
| 219 | + if (!stat) | |
| 220 | + continue; | |
| 221 | + | |
| 222 | + while (stat) { | |
| 223 | + int bit = __ffs(stat); | |
| 224 | + int line = i * 8 + bit; | |
| 225 | + | |
| 226 | + handle_nested_irq(tc35892_gpio->irq_base + line); | |
| 227 | + stat &= ~(1 << bit); | |
| 228 | + } | |
| 229 | + | |
| 230 | + tc35892_reg_write(tc35892, TC35892_GPIOIC0 + i, status[i]); | |
| 231 | + } | |
| 232 | + | |
| 233 | + return IRQ_HANDLED; | |
| 234 | +} | |
| 235 | + | |
| 236 | +static int tc35892_gpio_irq_init(struct tc35892_gpio *tc35892_gpio) | |
| 237 | +{ | |
| 238 | + int base = tc35892_gpio->irq_base; | |
| 239 | + int irq; | |
| 240 | + | |
| 241 | + for (irq = base; irq < base + tc35892_gpio->chip.ngpio; irq++) { | |
| 242 | + set_irq_chip_data(irq, tc35892_gpio); | |
| 243 | + set_irq_chip_and_handler(irq, &tc35892_gpio_irq_chip, | |
| 244 | + handle_simple_irq); | |
| 245 | + set_irq_nested_thread(irq, 1); | |
| 246 | +#ifdef CONFIG_ARM | |
| 247 | + set_irq_flags(irq, IRQF_VALID); | |
| 248 | +#else | |
| 249 | + set_irq_noprobe(irq); | |
| 250 | +#endif | |
| 251 | + } | |
| 252 | + | |
| 253 | + return 0; | |
| 254 | +} | |
| 255 | + | |
| 256 | +static void tc35892_gpio_irq_remove(struct tc35892_gpio *tc35892_gpio) | |
| 257 | +{ | |
| 258 | + int base = tc35892_gpio->irq_base; | |
| 259 | + int irq; | |
| 260 | + | |
| 261 | + for (irq = base; irq < base + tc35892_gpio->chip.ngpio; irq++) { | |
| 262 | +#ifdef CONFIG_ARM | |
| 263 | + set_irq_flags(irq, 0); | |
| 264 | +#endif | |
| 265 | + set_irq_chip_and_handler(irq, NULL, NULL); | |
| 266 | + set_irq_chip_data(irq, NULL); | |
| 267 | + } | |
| 268 | +} | |
| 269 | + | |
| 270 | +static int __devinit tc35892_gpio_probe(struct platform_device *pdev) | |
| 271 | +{ | |
| 272 | + struct tc35892 *tc35892 = dev_get_drvdata(pdev->dev.parent); | |
| 273 | + struct tc35892_gpio_platform_data *pdata; | |
| 274 | + struct tc35892_gpio *tc35892_gpio; | |
| 275 | + int ret; | |
| 276 | + int irq; | |
| 277 | + | |
| 278 | + pdata = tc35892->pdata->gpio; | |
| 279 | + if (!pdata) | |
| 280 | + return -ENODEV; | |
| 281 | + | |
| 282 | + irq = platform_get_irq(pdev, 0); | |
| 283 | + if (irq < 0) | |
| 284 | + return irq; | |
| 285 | + | |
| 286 | + tc35892_gpio = kzalloc(sizeof(struct tc35892_gpio), GFP_KERNEL); | |
| 287 | + if (!tc35892_gpio) | |
| 288 | + return -ENOMEM; | |
| 289 | + | |
| 290 | + mutex_init(&tc35892_gpio->irq_lock); | |
| 291 | + | |
| 292 | + tc35892_gpio->dev = &pdev->dev; | |
| 293 | + tc35892_gpio->tc35892 = tc35892; | |
| 294 | + | |
| 295 | + tc35892_gpio->chip = template_chip; | |
| 296 | + tc35892_gpio->chip.ngpio = tc35892->num_gpio; | |
| 297 | + tc35892_gpio->chip.dev = &pdev->dev; | |
| 298 | + tc35892_gpio->chip.base = pdata->gpio_base; | |
| 299 | + | |
| 300 | + tc35892_gpio->irq_base = tc35892->irq_base + TC35892_INT_GPIO(0); | |
| 301 | + | |
| 302 | + /* Bring the GPIO module out of reset */ | |
| 303 | + ret = tc35892_set_bits(tc35892, TC35892_RSTCTRL, | |
| 304 | + TC35892_RSTCTRL_GPIRST, 0); | |
| 305 | + if (ret < 0) | |
| 306 | + goto out_free; | |
| 307 | + | |
| 308 | + ret = tc35892_gpio_irq_init(tc35892_gpio); | |
| 309 | + if (ret) | |
| 310 | + goto out_free; | |
| 311 | + | |
| 312 | + ret = request_threaded_irq(irq, NULL, tc35892_gpio_irq, IRQF_ONESHOT, | |
| 313 | + "tc35892-gpio", tc35892_gpio); | |
| 314 | + if (ret) { | |
| 315 | + dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
| 316 | + goto out_removeirq; | |
| 317 | + } | |
| 318 | + | |
| 319 | + ret = gpiochip_add(&tc35892_gpio->chip); | |
| 320 | + if (ret) { | |
| 321 | + dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
| 322 | + goto out_freeirq; | |
| 323 | + } | |
| 324 | + | |
| 325 | + platform_set_drvdata(pdev, tc35892_gpio); | |
| 326 | + | |
| 327 | + return 0; | |
| 328 | + | |
| 329 | +out_freeirq: | |
| 330 | + free_irq(irq, tc35892_gpio); | |
| 331 | +out_removeirq: | |
| 332 | + tc35892_gpio_irq_remove(tc35892_gpio); | |
| 333 | +out_free: | |
| 334 | + kfree(tc35892_gpio); | |
| 335 | + return ret; | |
| 336 | +} | |
| 337 | + | |
| 338 | +static int __devexit tc35892_gpio_remove(struct platform_device *pdev) | |
| 339 | +{ | |
| 340 | + struct tc35892_gpio *tc35892_gpio = platform_get_drvdata(pdev); | |
| 341 | + int irq = platform_get_irq(pdev, 0); | |
| 342 | + int ret; | |
| 343 | + | |
| 344 | + ret = gpiochip_remove(&tc35892_gpio->chip); | |
| 345 | + if (ret < 0) { | |
| 346 | + dev_err(tc35892_gpio->dev, | |
| 347 | + "unable to remove gpiochip: %d\n", ret); | |
| 348 | + return ret; | |
| 349 | + } | |
| 350 | + | |
| 351 | + free_irq(irq, tc35892_gpio); | |
| 352 | + tc35892_gpio_irq_remove(tc35892_gpio); | |
| 353 | + | |
| 354 | + platform_set_drvdata(pdev, NULL); | |
| 355 | + kfree(tc35892_gpio); | |
| 356 | + | |
| 357 | + return 0; | |
| 358 | +} | |
| 359 | + | |
| 360 | +static struct platform_driver tc35892_gpio_driver = { | |
| 361 | + .driver.name = "tc35892-gpio", | |
| 362 | + .driver.owner = THIS_MODULE, | |
| 363 | + .probe = tc35892_gpio_probe, | |
| 364 | + .remove = __devexit_p(tc35892_gpio_remove), | |
| 365 | +}; | |
| 366 | + | |
| 367 | +static int __init tc35892_gpio_init(void) | |
| 368 | +{ | |
| 369 | + return platform_driver_register(&tc35892_gpio_driver); | |
| 370 | +} | |
| 371 | +subsys_initcall(tc35892_gpio_init); | |
| 372 | + | |
| 373 | +static void __exit tc35892_gpio_exit(void) | |
| 374 | +{ | |
| 375 | + platform_driver_unregister(&tc35892_gpio_driver); | |
| 376 | +} | |
| 377 | +module_exit(tc35892_gpio_exit); | |
| 378 | + | |
| 379 | +MODULE_LICENSE("GPL v2"); | |
| 380 | +MODULE_DESCRIPTION("TC35892 GPIO driver"); | |
| 381 | +MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); | |
| @@ -590,4 +590,17 @@ config TOUCHSCREEN_PCAP · 589 unmodified lines | ||
| 590 | 590 | |
| 591 | 591 | To compile this driver as a module, choose M here: the |
| 592 | 592 | module will be called pcap_ts. |
| 593 | + | |
| 594 | +config TOUCHSCREEN_TPS6507X | |
| 595 | + tristate "TPS6507x based touchscreens" | |
| 596 | + depends on I2C | |
| 597 | + help | |
| 598 | + Say Y here if you have a TPS6507x based touchscreen | |
| 599 | + controller. | |
| 600 | + | |
| 601 | + If unsure, say N. | |
| 602 | + | |
| 603 | + To compile this driver as a module, choose M here: the | |
| 604 | + module will be called tps6507x_ts. | |
| 605 | + | |
| 593 | 606 | endif |
| @@ -46,3 +46,4 @@ obj-$(CONFIG_TOUCHSCREEN_WM97XX_ATMEL) += atmel-wm97xx.o · 45 unmodified lines | ||
| 46 | 46 | obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o |
| 47 | 47 | obj-$(CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE) += zylonite-wm97xx.o |
| 48 | 48 | obj-$(CONFIG_TOUCHSCREEN_W90X900) += w90p910_ts.o |
| 49 | +obj-$(CONFIG_TOUCHSCREEN_TPS6507X) += tps6507x-ts.o | |
| @@ -0,0 +1,400 @@ | ||
| 1 | +/* | |
| 2 | + * drivers/input/touchscreen/tps6507x_ts.c | |
| 3 | + * | |
| 4 | + * Touchscreen driver for the tps6507x chip. | |
| 5 | + * | |
| 6 | + * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com) | |
| 7 | + * | |
| 8 | + * Credits: | |
| 9 | + * | |
| 10 | + * Using code from tsc2007, MtekVision Co., Ltd. | |
| 11 | + * | |
| 12 | + * For licencing details see kernel-base/COPYING | |
| 13 | + * | |
| 14 | + * TPS65070, TPS65073, TPS650731, and TPS650732 support | |
| 15 | + * 10 bit touch screen interface. | |
| 16 | + */ | |
| 17 | + | |
| 18 | +#include <linux/module.h> | |
| 19 | +#include <linux/workqueue.h> | |
| 20 | +#include <linux/slab.h> | |
| 21 | +#include <linux/input.h> | |
| 22 | +#include <linux/platform_device.h> | |
| 23 | +#include <linux/mfd/tps6507x.h> | |
| 24 | +#include <linux/input/tps6507x-ts.h> | |
| 25 | +#include <linux/delay.h> | |
| 26 | + | |
| 27 | +#define TSC_DEFAULT_POLL_PERIOD 30 /* ms */ | |
| 28 | +#define TPS_DEFAULT_MIN_PRESSURE 0x30 | |
| 29 | +#define MAX_10BIT ((1 << 10) - 1) | |
| 30 | + | |
| 31 | +#define TPS6507X_ADCONFIG_CONVERT_TS (TPS6507X_ADCONFIG_AD_ENABLE | \ | |
| 32 | + TPS6507X_ADCONFIG_START_CONVERSION | \ | |
| 33 | + TPS6507X_ADCONFIG_INPUT_REAL_TSC) | |
| 34 | +#define TPS6507X_ADCONFIG_POWER_DOWN_TS (TPS6507X_ADCONFIG_INPUT_REAL_TSC) | |
| 35 | + | |
| 36 | +struct ts_event { | |
| 37 | + u16 x; | |
| 38 | + u16 y; | |
| 39 | + u16 pressure; | |
| 40 | +}; | |
| 41 | + | |
| 42 | +struct tps6507x_ts { | |
| 43 | + struct input_dev *input_dev; | |
| 44 | + struct device *dev; | |
| 45 | + char phys[32]; | |
| 46 | + struct workqueue_struct *wq; | |
| 47 | + struct delayed_work work; | |
| 48 | + unsigned polling; /* polling is active */ | |
| 49 | + struct ts_event tc; | |
| 50 | + struct tps6507x_dev *mfd; | |
| 51 | + u16 model; | |
| 52 | + unsigned pendown; | |
| 53 | + int irq; | |
| 54 | + void (*clear_penirq)(void); | |
| 55 | + unsigned long poll_period; /* ms */ | |
| 56 | + u16 min_pressure; | |
| 57 | + int vref; /* non-zero to leave vref on */ | |
| 58 | +}; | |
| 59 | + | |
| 60 | +static int tps6507x_read_u8(struct tps6507x_ts *tsc, u8 reg, u8 *data) | |
| 61 | +{ | |
| 62 | + int err; | |
| 63 | + | |
| 64 | + err = tsc->mfd->read_dev(tsc->mfd, reg, 1, data); | |
| 65 | + | |
| 66 | + if (err) | |
| 67 | + return err; | |
| 68 | + | |
| 69 | + return 0; | |
| 70 | +} | |
| 71 | + | |
| 72 | +static int tps6507x_write_u8(struct tps6507x_ts *tsc, u8 reg, u8 data) | |
| 73 | +{ | |
| 74 | + return tsc->mfd->write_dev(tsc->mfd, reg, 1, &data); | |
| 75 | +} | |
| 76 | + | |
| 77 | +static s32 tps6507x_adc_conversion(struct tps6507x_ts *tsc, | |
| 78 | + u8 tsc_mode, u16 *value) | |
| 79 | +{ | |
| 80 | + s32 ret; | |
| 81 | + u8 adc_status; | |
| 82 | + u8 result; | |
| 83 | + | |
| 84 | + /* Route input signal to A/D converter */ | |
| 85 | + | |
| 86 | + ret = tps6507x_write_u8(tsc, TPS6507X_REG_TSCMODE, tsc_mode); | |
| 87 | + if (ret) { | |
| 88 | + dev_err(tsc->dev, "TSC mode read failed\n"); | |
| 89 | + goto err; | |
| 90 | + } | |
| 91 | + | |
| 92 | + /* Start A/D conversion */ | |
| 93 | + | |
| 94 | + ret = tps6507x_write_u8(tsc, TPS6507X_REG_ADCONFIG, | |
| 95 | + TPS6507X_ADCONFIG_CONVERT_TS); | |
| 96 | + if (ret) { | |
| 97 | + dev_err(tsc->dev, "ADC config write failed\n"); | |
| 98 | + return ret; | |
| 99 | + } | |
| 100 | + | |
| 101 | + do { | |
| 102 | + ret = tps6507x_read_u8(tsc, TPS6507X_REG_ADCONFIG, | |
| 103 | + &adc_status); | |
| 104 | + if (ret) { | |
| 105 | + dev_err(tsc->dev, "ADC config read failed\n"); | |
| 106 | + goto err; | |
| 107 | + } | |
| 108 | + } while (adc_status & TPS6507X_ADCONFIG_START_CONVERSION); | |
| 109 | + | |
| 110 | + ret = tps6507x_read_u8(tsc, TPS6507X_REG_ADRESULT_2, &result); | |
| 111 | + if (ret) { | |
| 112 | + dev_err(tsc->dev, "ADC result 2 read failed\n"); | |
| 113 | + goto err; | |
| 114 | + } | |
| 115 | + | |
| 116 | + *value = (result & TPS6507X_REG_ADRESULT_2_MASK) << 8; | |
| 117 | + | |
| 118 | + ret = tps6507x_read_u8(tsc, TPS6507X_REG_ADRESULT_1, &result); | |
| 119 | + if (ret) { | |
| 120 | + dev_err(tsc->dev, "ADC result 1 read failed\n"); | |
| 121 | + goto err; | |
| 122 | + } | |
| 123 | + | |
| 124 | + *value |= result; | |
| 125 | + | |
| 126 | + dev_dbg(tsc->dev, "TSC channel %d = 0x%X\n", tsc_mode, *value); | |
| 127 | + | |
| 128 | +err: | |
| 129 | + return ret; | |
| 130 | +} | |
| 131 | + | |
| 132 | +/* Need to call tps6507x_adc_standby() after using A/D converter for the | |
| 133 | + * touch screen interrupt to work properly. | |
| 134 | + */ | |
| 135 | + | |
| 136 | +static s32 tps6507x_adc_standby(struct tps6507x_ts *tsc) | |
| 137 | +{ | |
| 138 | + s32 ret; | |
| 139 | + s32 loops = 0; | |
| 140 | + u8 val; | |
| 141 | + | |
| 142 | + ret = tps6507x_write_u8(tsc, TPS6507X_REG_ADCONFIG, | |
| 143 | + TPS6507X_ADCONFIG_INPUT_TSC); | |
| 144 | + if (ret) | |
| 145 | + return ret; | |
| 146 | + | |
| 147 | + ret = tps6507x_write_u8(tsc, TPS6507X_REG_TSCMODE, | |
| 148 | + TPS6507X_TSCMODE_STANDBY); | |
| 149 | + if (ret) | |
| 150 | + return ret; | |
| 151 | + | |
| 152 | + ret = tps6507x_read_u8(tsc, TPS6507X_REG_INT, &val); | |
| 153 | + if (ret) | |
| 154 | + return ret; | |
| 155 | + | |
| 156 | + while (val & TPS6507X_REG_TSC_INT) { | |
| 157 | + mdelay(10); | |
| 158 | + ret = tps6507x_read_u8(tsc, TPS6507X_REG_INT, &val); | |
| 159 | + if (ret) | |
| 160 | + return ret; | |
| 161 | + loops++; | |
| 162 | + } | |
| 163 | + | |
| 164 | + return ret; | |
| 165 | +} | |
| 166 | + | |
| 167 | +static void tps6507x_ts_handler(struct work_struct *work) | |
| 168 | +{ | |
| 169 | + struct tps6507x_ts *tsc = container_of(work, | |
| 170 | + struct tps6507x_ts, work.work); | |
| 171 | + struct input_dev *input_dev = tsc->input_dev; | |
| 172 | + int pendown; | |
| 173 | + int schd; | |
| 174 | + int poll = 0; | |
| 175 | + s32 ret; | |
| 176 | + | |
| 177 | + ret = tps6507x_adc_conversion(tsc, TPS6507X_TSCMODE_PRESSURE, | |
| 178 | + &tsc->tc.pressure); | |
| 179 | + if (ret) | |
| 180 | + goto done; | |
| 181 | + | |
| 182 | + pendown = tsc->tc.pressure > tsc->min_pressure; | |
| 183 | + | |
| 184 | + if (unlikely(!pendown && tsc->pendown)) { | |
| 185 | + dev_dbg(tsc->dev, "UP\n"); | |
| 186 | + input_report_key(input_dev, BTN_TOUCH, 0); | |
| 187 | + input_report_abs(input_dev, ABS_PRESSURE, 0); | |
| 188 | + input_sync(input_dev); | |
| 189 | + tsc->pendown = 0; | |
| 190 | + } | |
| 191 | + | |
| 192 | + if (pendown) { | |
| 193 | + | |
| 194 | + if (!tsc->pendown) { | |
| 195 | + dev_dbg(tsc->dev, "DOWN\n"); | |
| 196 | + input_report_key(input_dev, BTN_TOUCH, 1); | |
| 197 | + } else | |
| 198 | + dev_dbg(tsc->dev, "still down\n"); | |
| 199 | + | |
| 200 | + ret = tps6507x_adc_conversion(tsc, TPS6507X_TSCMODE_X_POSITION, | |
| 201 | + &tsc->tc.x); | |
| 202 | + if (ret) | |
| 203 | + goto done; | |
| 204 | + | |
| 205 | + ret = tps6507x_adc_conversion(tsc, TPS6507X_TSCMODE_Y_POSITION, | |
| 206 | + &tsc->tc.y); | |
| 207 | + if (ret) | |
| 208 | + goto done; | |
| 209 | + | |
| 210 | + input_report_abs(input_dev, ABS_X, tsc->tc.x); | |
| 211 | + input_report_abs(input_dev, ABS_Y, tsc->tc.y); | |
| 212 | + input_report_abs(input_dev, ABS_PRESSURE, tsc->tc.pressure); | |
| 213 | + input_sync(input_dev); | |
| 214 | + tsc->pendown = 1; | |
| 215 | + poll = 1; | |
| 216 | + } | |
| 217 | + | |
| 218 | +done: | |
| 219 | + /* always poll if not using interrupts */ | |
| 220 | + poll = 1; | |
| 221 | + | |
| 222 | + if (poll) { | |
| 223 | + schd = queue_delayed_work(tsc->wq, &tsc->work, | |
| 224 | + tsc->poll_period * HZ / 1000); | |
| 225 | + if (schd) | |
| 226 | + tsc->polling = 1; | |
| 227 | + else { | |
| 228 | + tsc->polling = 0; | |
| 229 | + dev_err(tsc->dev, "re-schedule failed"); | |
| 230 | + } | |
| 231 | + } else | |
| 232 | + tsc->polling = 0; | |
| 233 | + | |
| 234 | + ret = tps6507x_adc_standby(tsc); | |
| 235 | +} | |
| 236 | + | |
| 237 | +static int tps6507x_ts_probe(struct platform_device *pdev) | |
| 238 | +{ | |
| 239 | + int error; | |
| 240 | + struct tps6507x_ts *tsc; | |
| 241 | + struct tps6507x_dev *tps6507x_dev = dev_get_drvdata(pdev->dev.parent); | |
| 242 | + struct touchscreen_init_data *init_data; | |
| 243 | + struct input_dev *input_dev; | |
| 244 | + struct tps6507x_board *tps_board; | |
| 245 | + int schd; | |
| 246 | + | |
| 247 | + /** | |
| 248 | + * tps_board points to pmic related constants | |
| 249 | + * coming from the board-evm file. | |
| 250 | + */ | |
| 251 | + | |
| 252 | + tps_board = (struct tps6507x_board *)tps6507x_dev->dev->platform_data; | |
| 253 | + | |
| 254 | + if (!tps_board) { | |
| 255 | + dev_err(tps6507x_dev->dev, | |
| 256 | + "Could not find tps6507x platform data\n"); | |
| 257 | + return -EIO; | |
| 258 | + } | |
| 259 | + | |
| 260 | + /** | |
| 261 | + * init_data points to array of regulator_init structures | |
| 262 | + * coming from the board-evm file. | |
| 263 | + */ | |
| 264 | + | |
| 265 | + init_data = tps_board->tps6507x_ts_init_data; | |
| 266 | + | |
| 267 | + tsc = kzalloc(sizeof(struct tps6507x_ts), GFP_KERNEL); | |
| 268 | + if (!tsc) { | |
| 269 | + dev_err(tps6507x_dev->dev, "failed to allocate driver data\n"); | |
| 270 | + error = -ENOMEM; | |
| 271 | + goto err0; | |
| 272 | + } | |
| 273 | + | |
| 274 | + tps6507x_dev->ts = tsc; | |
| 275 | + tsc->mfd = tps6507x_dev; | |
| 276 | + tsc->dev = tps6507x_dev->dev; | |
| 277 | + input_dev = input_allocate_device(); | |
| 278 | + if (!input_dev) { | |
| 279 | + dev_err(tsc->dev, "Failed to allocate input device.\n"); | |
| 280 | + error = -ENOMEM; | |
| 281 | + goto err1; | |
| 282 | + } | |
| 283 | + | |
| 284 | + input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); | |
| 285 | + input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); | |
| 286 | + | |
| 287 | + input_set_abs_params(input_dev, ABS_X, 0, MAX_10BIT, 0, 0); | |
| 288 | + input_set_abs_params(input_dev, ABS_Y, 0, MAX_10BIT, 0, 0); | |
| 289 | + input_set_abs_params(input_dev, ABS_PRESSURE, 0, MAX_10BIT, 0, 0); | |
| 290 | + | |
| 291 | + input_dev->name = "TPS6507x Touchscreen"; | |
| 292 | + input_dev->id.bustype = BUS_I2C; | |
| 293 | + input_dev->dev.parent = tsc->dev; | |
| 294 | + | |
| 295 | + snprintf(tsc->phys, sizeof(tsc->phys), | |
| 296 | + "%s/input0", dev_name(tsc->dev)); | |
| 297 | + input_dev->phys = tsc->phys; | |
| 298 | + | |
| 299 | + dev_dbg(tsc->dev, "device: %s\n", input_dev->phys); | |
| 300 | + | |
| 301 | + input_set_drvdata(input_dev, tsc); | |
| 302 | + | |
| 303 | + tsc->input_dev = input_dev; | |
| 304 | + | |
| 305 | + INIT_DELAYED_WORK(&tsc->work, tps6507x_ts_handler); | |
| 306 | + tsc->wq = create_workqueue("TPS6507x Touchscreen"); | |
| 307 | + | |
| 308 | + if (init_data) { | |
| 309 | + tsc->poll_period = init_data->poll_period; | |
| 310 | + tsc->vref = init_data->vref; | |
| 311 | + tsc->min_pressure = init_data->min_pressure; | |
| 312 | + input_dev->id.vendor = init_data->vendor; | |
| 313 | + input_dev->id.product = init_data->product; | |
| 314 | + input_dev->id.version = init_data->version; | |
| 315 | + } else { | |
| 316 | + tsc->poll_period = TSC_DEFAULT_POLL_PERIOD; | |
| 317 | + tsc->min_pressure = TPS_DEFAULT_MIN_PRESSURE; | |
| 318 | + } | |
| 319 | + | |
| 320 | + error = tps6507x_adc_standby(tsc); | |
| 321 | + if (error) | |
| 322 | + goto err2; | |
| 323 | + | |
| 324 | + error = input_register_device(input_dev); | |
| 325 | + if (error) | |
| 326 | + goto err2; | |
| 327 | + | |
| 328 | + schd = queue_delayed_work(tsc->wq, &tsc->work, | |
| 329 | + tsc->poll_period * HZ / 1000); | |
| 330 | + | |
| 331 | + if (schd) | |
| 332 | + tsc->polling = 1; | |
| 333 | + else { | |
| 334 | + tsc->polling = 0; | |
| 335 | + dev_err(tsc->dev, "schedule failed"); | |
| 336 | + goto err2; | |
| 337 | + } | |
| 338 | + | |
| 339 | + return 0; | |
| 340 | + | |
| 341 | +err2: | |
| 342 | + cancel_delayed_work(&tsc->work); | |
| 343 | + flush_workqueue(tsc->wq); | |
| 344 | + destroy_workqueue(tsc->wq); | |
| 345 | + tsc->wq = 0; | |
| 346 | + input_free_device(input_dev); | |
| 347 | +err1: | |
| 348 | + kfree(tsc); | |
| 349 | + tps6507x_dev->ts = NULL; | |
| 350 | +err0: | |
| 351 | + return error; | |
| 352 | +} | |
| 353 | + | |
| 354 | +static int __devexit tps6507x_ts_remove(struct platform_device *pdev) | |
| 355 | +{ | |
| 356 | + struct tps6507x_dev *tps6507x_dev = platform_get_drvdata(pdev); | |
| 357 | + struct tps6507x_ts *tsc = tps6507x_dev->ts; | |
| 358 | + struct input_dev *input_dev = tsc->input_dev; | |
| 359 | + | |
| 360 | + if (!tsc) | |
| 361 | + return 0; | |
| 362 | + | |
| 363 | + cancel_delayed_work(&tsc->work); | |
| 364 | + flush_workqueue(tsc->wq); | |
| 365 | + destroy_workqueue(tsc->wq); | |
| 366 | + tsc->wq = 0; | |
| 367 | + | |
| 368 | + input_free_device(input_dev); | |
| 369 | + | |
| 370 | + tps6507x_dev->ts = NULL; | |
| 371 | + kfree(tsc); | |
| 372 | + | |
| 373 | + return 0; | |
| 374 | +} | |
| 375 | + | |
| 376 | +static struct platform_driver tps6507x_ts_driver = { | |
| 377 | + .driver = { | |
| 378 | + .name = "tps6507x-ts", | |
| 379 | + .owner = THIS_MODULE, | |
| 380 | + }, | |
| 381 | + .probe = tps6507x_ts_probe, | |
| 382 | + .remove = __devexit_p(tps6507x_ts_remove), | |
| 383 | +}; | |
| 384 | + | |
| 385 | +static int __init tps6507x_ts_init(void) | |
| 386 | +{ | |
| 387 | + return platform_driver_register(&tps6507x_ts_driver); | |
| 388 | +} | |
| 389 | +module_init(tps6507x_ts_init); | |
| 390 | + | |
| 391 | +static void __exit tps6507x_ts_exit(void) | |
| 392 | +{ | |
| 393 | + platform_driver_unregister(&tps6507x_ts_driver); | |
| 394 | +} | |
| 395 | +module_exit(tps6507x_ts_exit); | |
| 396 | + | |
| 397 | +MODULE_AUTHOR("Todd Fischer <todd.fischer@ridgerun.com>"); | |
| 398 | +MODULE_DESCRIPTION("TPS6507x - TouchScreen driver"); | |
| 399 | +MODULE_LICENSE("GPL v2"); | |
| 400 | +MODULE_ALIAS("platform:tps6507x-tsc"); | |
| @@ -566,7 +566,7 @@ out: · 565 unmodified lines | ||
| 566 | 566 | return ret; |
| 567 | 567 | } |
| 568 | 568 | |
| 569 | −static void __devexit device_irq_exit(struct pm860x_chip *chip) | |
| 569 | +static void device_irq_exit(struct pm860x_chip *chip) | |
| 570 | 570 | { |
| 571 | 571 | if (chip->core_irq) |
| 572 | 572 | free_irq(chip->core_irq, chip); |
| @@ -703,7 +703,7 @@ out: · 130 unmodified lines | ||
| 703 | 703 | return; |
| 704 | 704 | } |
| 705 | 705 | |
| 706 | −int pm860x_device_init(struct pm860x_chip *chip, | |
| 706 | +int __devinit pm860x_device_init(struct pm860x_chip *chip, | |
| 707 | 707 | struct pm860x_platform_data *pdata) |
| 708 | 708 | { |
| 709 | 709 | chip->core_irq = 0; |
| @@ -731,7 +731,7 @@ int pm860x_device_init(struct pm860x_chip *chip, · 21 unmodified lines | ||
| 731 | 731 | return 0; |
| 732 | 732 | } |
| 733 | 733 | |
| 734 | −void pm860x_device_exit(struct pm860x_chip *chip) | |
| 734 | +void __devexit pm860x_device_exit(struct pm860x_chip *chip) | |
| 735 | 735 | { |
| 736 | 736 | device_irq_exit(chip); |
| 737 | 737 | mfd_remove_devices(chip->dev); |
| @@ -200,8 +200,8 @@ static int __devexit pm860x_remove(struct i2c_client *client) · 199 unmodified lines | ||
| 200 | 200 | |
| 201 | 201 | pm860x_device_exit(chip); |
| 202 | 202 | i2c_unregister_device(chip->companion); |
| 203 | − i2c_set_clientdata(chip->companion, NULL); | |
| 204 | 203 | i2c_set_clientdata(chip->client, NULL); |
| 204 | + i2c_set_clientdata(client, NULL); | |
| 205 | 205 | kfree(chip); |
| 206 | 206 | return 0; |
| 207 | 207 | } |
| @@ -2,8 +2,14 @@ · 1 unmodified line | ||
| 2 | 2 | # Multifunction miscellaneous devices |
| 3 | 3 | # |
| 4 | 4 | |
| 5 | −menu "Multifunction device drivers" | |
| 5 | +menuconfig MFD_SUPPORT | |
| 6 | + bool "Multifunction device drivers" | |
| 6 | 7 | depends on HAS_IOMEM |
| 8 | + default y | |
| 9 | + help | |
| 10 | + Configure MFD device drivers. | |
| 11 | + | |
| 12 | +if MFD_SUPPORT | |
| 7 | 13 | |
| 8 | 14 | config MFD_CORE |
| 9 | 15 | tristate |
| @@ -116,6 +122,18 @@ config TPS65010 · 106 unmodified lines | ||
| 116 | 122 | This driver can also be built as a module. If so, the module |
| 117 | 123 | will be called tps65010. |
| 118 | 124 | |
| 125 | +config TPS6507X | |
| 126 | + tristate "TPS6507x Power Management / Touch Screen chips" | |
| 127 | + select MFD_CORE | |
| 128 | + depends on I2C | |
| 129 | + help | |
| 130 | + If you say yes here you get support for the TPS6507x series of | |
| 131 | + Power Management / Touch Screen chips. These include voltage | |
| 132 | + regulators, lithium ion/polymer battery charging, touch screen | |
| 133 | + and other features that are often used in portable devices. | |
| 134 | + This driver can also be built as a module. If so, the module | |
| 135 | + will be called tps6507x. | |
| 136 | + | |
| 119 | 137 | config MENELAUS |
| 120 | 138 | bool "Texas Instruments TWL92330/Menelaus PM chip" |
| 121 | 139 | depends on I2C=y && ARCH_OMAP2 |
| @@ -159,6 +177,17 @@ config TWL4030_CODEC · 37 unmodified lines | ||
| 159 | 177 | select MFD_CORE |
| 160 | 178 | default n |
| 161 | 179 | |
| 180 | +config MFD_TC35892 | |
| 181 | + bool "Support Toshiba TC35892" | |
| 182 | + depends on I2C=y && GENERIC_HARDIRQS | |
| 183 | + select MFD_CORE | |
| 184 | + help | |
| 185 | + Support for the Toshiba TC35892 I/O Expander. | |
| 186 | + | |
| 187 | + This driver provides common support for accessing the device, | |
| 188 | + additional drivers must be enabled in order to use the | |
| 189 | + functionality of the device. | |
| 190 | + | |
| 162 | 191 | config MFD_TMIO |
| 163 | 192 | bool |
| 164 | 193 | default n |
| @@ -351,9 +380,19 @@ config PCF50633_GPIO · 186 unmodified lines | ||
| 351 | 380 | Say yes here if you want to include support GPIO for pins on |
| 352 | 381 | the PCF50633 chip. |
| 353 | 382 | |
| 383 | +config ABX500_CORE | |
| 384 | + bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions" | |
| 385 | + default y if ARCH_U300 | |
| 386 | + help | |
| 387 | + Say yes here if you have the ABX500 Mixed Signal IC family | |
| 388 | + chips. This core driver expose register access functions. | |
| 389 | + Functionality specific drivers using these functions can | |
| 390 | + remain unchanged when IC changes. Binding of the functions to | |
| 391 | + actual register access is done by the IC core driver. | |
| 392 | + | |
| 354 | 393 | config AB3100_CORE |
| 355 | 394 | bool "ST-Ericsson AB3100 Mixed Signal Circuit core functions" |
| 356 | − depends on I2C=y | |
| 395 | + depends on I2C=y && ABX500_CORE | |
| 357 | 396 | default y if ARCH_U300 |
| 358 | 397 | help |
| 359 | 398 | Select this to enable the AB3100 Mixed Signal IC core |
| @@ -381,15 +420,30 @@ config EZX_PCAP · 21 unmodified lines | ||
| 381 | 420 | This enables the PCAP ASIC present on EZX Phones. This is |
| 382 | 421 | needed for MMC, TouchScreen, Sound, USB, etc.. |
| 383 | 422 | |
| 384 | −config AB4500_CORE | |
| 385 | − tristate "ST-Ericsson's AB4500 Mixed Signal Power management chip" | |
| 386 | − depends on SPI | |
| 423 | +config AB8500_CORE | |
| 424 | + bool "ST-Ericsson AB8500 Mixed Signal Power Management chip" | |
| 425 | + depends on SPI=y && GENERIC_HARDIRQS | |
| 426 | + select MFD_CORE | |
| 387 | 427 | help |
| 388 | − Select this option to enable access to AB4500 power management | |
| 428 | + Select this option to enable access to AB8500 power management | |
| 389 | 429 | chip. This connects to U8500 on the SSP/SPI bus and exports |
| 390 | 430 | read/write functions for the devices to get access to this chip. |
| 391 | 431 | This chip embeds various other multimedia funtionalities as well. |
| 392 | 432 | |
| 433 | +config AB3550_CORE | |
| 434 | + bool "ST-Ericsson AB3550 Mixed Signal Circuit core functions" | |
| 435 | + select MFD_CORE | |
| 436 | + depends on I2C=y && GENERIC_HARDIRQS && ABX500_CORE | |
| 437 | + help | |
| 438 | + Select this to enable the AB3550 Mixed Signal IC core | |
| 439 | + functionality. This connects to a AB3550 on the I2C bus | |
| 440 | + and expose a number of symbols needed for dependent devices | |
| 441 | + to read and write registers and subscribe to events from | |
| 442 | + this multi-functional IC. This is needed to use other features | |
| 443 | + of the AB3550 such as battery-backed RTC, charging control, | |
| 444 | + LEDs, vibrator, system power and temperature, power management | |
| 445 | + and ALSA sound. | |
| 446 | + | |
| 393 | 447 | config MFD_TIMBERDALE |
| 394 | 448 | tristate "Support for the Timberdale FPGA" |
| 395 | 449 | select MFD_CORE |
| @@ -409,7 +463,26 @@ config LPC_SCH · 13 unmodified lines | ||
| 409 | 463 | LPC bridge function of the Intel SCH provides support for |
| 410 | 464 | System Management Bus and General Purpose I/O. |
| 411 | 465 | |
| 412 | −endmenu | |
| 466 | +config MFD_RDC321X | |
| 467 | + tristate "Support for RDC-R321x southbridge" | |
| 468 | + select MFD_CORE | |
| 469 | + depends on PCI | |
| 470 | + help | |
| 471 | + Say yes here if you want to have support for the RDC R-321x SoC | |
| 472 | + southbridge which provides access to GPIOs and Watchdog using the | |
| 473 | + southbridge PCI device configuration space. | |
| 474 | + | |
| 475 | +config MFD_JANZ_CMODIO | |
| 476 | + tristate "Support for Janz CMOD-IO PCI MODULbus Carrier Board" | |
| 477 | + select MFD_CORE | |
| 478 | + depends on PCI | |
| 479 | + help | |
| 480 | + This is the core driver for the Janz CMOD-IO PCI MODULbus | |
| 481 | + carrier board. This device is a PCI to MODULbus bridge which may | |
| 482 | + host many different types of MODULbus daughterboards, including | |
| 483 | + CAN and GPIO controllers. | |
| 484 | + | |
| 485 | +endif # MFD_SUPPORT | |
| 413 | 486 | |
| 414 | 487 | menu "Multimedia Capabilities Port drivers" |
| 415 | 488 | depends on ARCH_SA1100 |
| @@ -15,6 +15,7 @@ obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o · 14 unmodified lines | ||
| 15 | 15 | obj-$(CONFIG_MFD_DAVINCI_VOICECODEC) += davinci_voicecodec.o |
| 16 | 16 | obj-$(CONFIG_MFD_DM355EVM_MSP) += dm355evm_msp.o |
| 17 | 17 | |
| 18 | +obj-$(CONFIG_MFD_TC35892) += tc35892.o | |
| 18 | 19 | obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o |
| 19 | 20 | obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o |
| 20 | 21 | obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o |
| @@ -29,6 +30,7 @@ obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o · 8 unmodified lines | ||
| 29 | 30 | obj-$(CONFIG_MFD_WM8994) += wm8994-core.o wm8994-irq.o |
| 30 | 31 | |
| 31 | 32 | obj-$(CONFIG_TPS65010) += tps65010.o |
| 33 | +obj-$(CONFIG_TPS6507X) += tps6507x.o | |
| 32 | 34 | obj-$(CONFIG_MENELAUS) += menelaus.o |
| 33 | 35 | |
| 34 | 36 | obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o |
| @@ -55,12 +57,17 @@ obj-$(CONFIG_PMIC_DA903X) += da903x.o · 20 unmodified lines | ||
| 55 | 57 | max8925-objs := max8925-core.o max8925-i2c.o |
| 56 | 58 | obj-$(CONFIG_MFD_MAX8925) += max8925.o |
| 57 | 59 | |
| 58 | −obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o | |
| 60 | +pcf50633-objs := pcf50633-core.o pcf50633-irq.o | |
| 61 | +obj-$(CONFIG_MFD_PCF50633) += pcf50633.o | |
| 59 | 62 | obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o |
| 60 | 63 | obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o |
| 64 | +obj-$(CONFIG_ABX500_CORE) += abx500-core.o | |
| 61 | 65 | obj-$(CONFIG_AB3100_CORE) += ab3100-core.o |
| 62 | 66 | obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o |
| 63 | −obj-$(CONFIG_AB4500_CORE) += ab4500-core.o | |
| 67 | +obj-$(CONFIG_AB3550_CORE) += ab3550-core.o | |
| 68 | +obj-$(CONFIG_AB8500_CORE) += ab8500-core.o ab8500-spi.o | |
| 64 | 69 | obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o |
| 65 | 70 | obj-$(CONFIG_PMIC_ADP5520) += adp5520.o |
| 66 | −obj-$(CONFIG_LPC_SCH) += lpc_sch.o | |
| 71 | +obj-$(CONFIG_LPC_SCH) += lpc_sch.o | |
| 72 | +obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o | |
| 73 | +obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o | |
| @@ -19,7 +19,7 @@ · 18 unmodified lines | ||
| 19 | 19 | #include <linux/debugfs.h> |
| 20 | 20 | #include <linux/seq_file.h> |
| 21 | 21 | #include <linux/uaccess.h> |
| 22 | −#include <linux/mfd/ab3100.h> | |
| 22 | +#include <linux/mfd/abx500.h> | |
| 23 | 23 | |
| 24 | 24 | /* These are the only registers inside AB3100 used in this main file */ |
| 25 | 25 | |
| @@ -59,24 +59,15 @@ · 33 unmodified lines | ||
| 59 | 59 | * The AB3100 is usually assigned address 0x48 (7-bit) |
| 60 | 60 | * The chip is defined in the platform i2c_board_data section. |
| 61 | 61 | */ |
| 62 | − | |
| 63 | −u8 ab3100_get_chip_type(struct ab3100 *ab3100) | |
| 62 | +static int ab3100_get_chip_id(struct device *dev) | |
| 64 | 63 | { |
| 65 | − u8 chip = ABUNKNOWN; | |
| 66 | − | |
| 67 | − switch (ab3100->chip_id & 0xf0) { | |
| 68 | − case 0xa0: | |
| 69 | − chip = AB3000; | |
| 70 | − break; | |
| 71 | − case 0xc0: | |
| 72 | − chip = AB3100; | |
| 73 | − break; | |
| 74 | − } | |
| 75 | − return chip; | |
| 64 | + struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); | |
| 65 | + | |
| 66 | + return (int)ab3100->chip_id; | |
| 76 | 67 | } |
| 77 | −EXPORT_SYMBOL(ab3100_get_chip_type); | |
| 78 | 68 | |
| 79 | −int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval) | |
| 69 | +static int ab3100_set_register_interruptible(struct ab3100 *ab3100, | |
| 70 | + u8 reg, u8 regval) | |
| 80 | 71 | { |
| 81 | 72 | u8 regandval[2] = {reg, regval}; |
| 82 | 73 | int err; |
| @@ -108,8 +99,14 @@ int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval) · 25 unmodified lines | ||
| 108 | 99 | mutex_unlock(&ab3100->access_mutex); |
| 109 | 100 | return err; |
| 110 | 101 | } |
| 111 | −EXPORT_SYMBOL(ab3100_set_register_interruptible); | |
| 112 | 102 | |
| 103 | +static int set_register_interruptible(struct device *dev, | |
| 104 | + u8 bank, u8 reg, u8 value) | |
| 105 | +{ | |
| 106 | + struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); | |
| 107 | + | |
| 108 | + return ab3100_set_register_interruptible(ab3100, reg, value); | |
| 109 | +} | |
| 113 | 110 | |
| 114 | 111 | /* |
| 115 | 112 | * The test registers exist at an I2C bus address up one |
| @@ -148,8 +145,8 @@ static int ab3100_set_test_register_interruptible(struct ab3100 *ab3100, · 32 unmodified lines | ||
| 148 | 145 | return err; |
| 149 | 146 | } |
| 150 | 147 | |
| 151 | − | |
| 152 | −int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval) | |
| 148 | +static int ab3100_get_register_interruptible(struct ab3100 *ab3100, | |
| 149 | + u8 reg, u8 *regval) | |
| 153 | 150 | { |
| 154 | 151 | int err; |
| 155 | 152 | |
| @@ -203,10 +200,16 @@ int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval) · 47 unmodified lines | ||
| 203 | 200 | mutex_unlock(&ab3100->access_mutex); |
| 204 | 201 | return err; |
| 205 | 202 | } |
| 206 | −EXPORT_SYMBOL(ab3100_get_register_interruptible); | |
| 207 | 203 | |
| 204 | +static int get_register_interruptible(struct device *dev, u8 bank, u8 reg, | |
| 205 | + u8 *value) | |
| 206 | +{ | |
| 207 | + struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); | |
| 208 | + | |
| 209 | + return ab3100_get_register_interruptible(ab3100, reg, value); | |
| 210 | +} | |
| 208 | 211 | |
| 209 | −int ab3100_get_register_page_interruptible(struct ab3100 *ab3100, | |
| 212 | +static int ab3100_get_register_page_interruptible(struct ab3100 *ab3100, | |
| 210 | 213 | u8 first_reg, u8 *regvals, u8 numregs) |
| 211 | 214 | { |
| 212 | 215 | int err; |
| @@ -260,10 +263,17 @@ int ab3100_get_register_page_interruptible(struct ab3100 *ab3100, · 47 unmodified lines | ||
| 260 | 263 | mutex_unlock(&ab3100->access_mutex); |
| 261 | 264 | return err; |
| 262 | 265 | } |
| 263 | −EXPORT_SYMBOL(ab3100_get_register_page_interruptible); | |
| 264 | 266 | |
| 267 | +static int get_register_page_interruptible(struct device *dev, u8 bank, | |
| 268 | + u8 first_reg, u8 *regvals, u8 numregs) | |
| 269 | +{ | |
| 270 | + struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); | |
| 271 | + | |
| 272 | + return ab3100_get_register_page_interruptible(ab3100, | |
| 273 | + first_reg, regvals, numregs); | |
| 274 | +} | |
| 265 | 275 | |
| 266 | −int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100, | |
| 276 | +static int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100, | |
| 267 | 277 | u8 reg, u8 andmask, u8 ormask) |
| 268 | 278 | { |
| 269 | 279 | u8 regandval[2] = {reg, 0}; |
| @@ -331,8 +341,15 @@ int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100, · 61 unmodified lines | ||
| 331 | 341 | mutex_unlock(&ab3100->access_mutex); |
| 332 | 342 | return err; |
| 333 | 343 | } |
| 334 | −EXPORT_SYMBOL(ab3100_mask_and_set_register_interruptible); | |
| 335 | 344 | |
| 345 | +static int mask_and_set_register_interruptible(struct device *dev, u8 bank, | |
| 346 | + u8 reg, u8 bitmask, u8 bitvalues) | |
| 347 | +{ | |
| 348 | + struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); | |
| 349 | + | |
| 350 | + return ab3100_mask_and_set_register_interruptible(ab3100, | |
| 351 | + reg, bitmask, (bitmask & bitvalues)); | |
| 352 | +} | |
| 336 | 353 | |
| 337 | 354 | /* |
| 338 | 355 | * Register a simple callback for handling any AB3100 events. |
| @@ -357,15 +374,27 @@ int ab3100_event_unregister(struct ab3100 *ab3100, · 18 unmodified lines | ||
| 357 | 374 | EXPORT_SYMBOL(ab3100_event_unregister); |
| 358 | 375 | |
| 359 | 376 | |
| 360 | −int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100, | |
| 361 | − u32 *fatevent) | |
| 377 | +static int ab3100_event_registers_startup_state_get(struct device *dev, | |
| 378 | + u8 *event) | |
| 362 | 379 | { |
| 380 | + struct ab3100 *ab3100 = dev_get_drvdata(dev->parent); | |
| 363 | 381 | if (!ab3100->startup_events_read) |
| 364 | 382 | return -EAGAIN; /* Try again later */ |
| 365 | − *fatevent = ab3100->startup_events; | |
| 383 | + memcpy(event, ab3100->startup_events, 3); | |
| 366 | 384 | return 0; |
| 367 | 385 | } |
| 368 | −EXPORT_SYMBOL(ab3100_event_registers_startup_state_get); | |
| 386 | + | |
| 387 | +static struct abx500_ops ab3100_ops = { | |
| 388 | + .get_chip_id = ab3100_get_chip_id, | |
| 389 | + .set_register = set_register_interruptible, | |
| 390 | + .get_register = get_register_interruptible, | |
| 391 | + .get_register_page = get_register_page_interruptible, | |
| 392 | + .set_register_page = NULL, | |
| 393 | + .mask_and_set_register = mask_and_set_register_interruptible, | |
| 394 | + .event_registers_startup_state_get = | |
| 395 | + ab3100_event_registers_startup_state_get, | |
| 396 | + .startup_irq_enabled = NULL, | |
| 397 | +}; | |
| 369 | 398 | |
| 370 | 399 | /* |
| 371 | 400 | * This is a threaded interrupt handler so we can make some |
| @@ -390,7 +419,9 @@ static irqreturn_t ab3100_irq_handler(int irq, void *data) · 18 unmodified lines | ||
| 390 | 419 | event_regs[2]; |
| 391 | 420 | |
| 392 | 421 | if (!ab3100->startup_events_read) { |
| 393 | − ab3100->startup_events = fatevent; | |
| 422 | + ab3100->startup_events[0] = event_regs[0]; | |
| 423 | + ab3100->startup_events[1] = event_regs[1]; | |
| 424 | + ab3100->startup_events[2] = event_regs[2]; | |
| 394 | 425 | ab3100->startup_events_read = true; |
| 395 | 426 | } |
| 396 | 427 | /* |
| @@ -703,7 +734,8 @@ static int __init ab3100_setup(struct ab3100 *ab3100) · 306 unmodified lines | ||
| 703 | 734 | dev_warn(ab3100->dev, |
| 704 | 735 | "AB3100 P1E variant detected, " |
| 705 | 736 | "forcing chip to 32KHz\n"); |
| 706 | − err = ab3100_set_test_register_interruptible(ab3100, 0x02, 0x08); | |
| 737 | + err = ab3100_set_test_register_interruptible(ab3100, | |
| 738 | + 0x02, 0x08); | |
| 707 | 739 | } |
| 708 | 740 | |
| 709 | 741 | exit_no_setup: |
| @@ -898,6 +930,10 @@ static int __init ab3100_probe(struct i2c_client *client, · 188 unmodified lines | ||
| 898 | 930 | if (err) |
| 899 | 931 | goto exit_no_irq; |
| 900 | 932 | |
| 933 | + err = abx500_register_ops(&client->dev, &ab3100_ops); | |
| 934 | + if (err) | |
| 935 | + goto exit_no_ops; | |
| 936 | + | |
| 901 | 937 | /* Set parent and a pointer back to the container in device data */ |
| 902 | 938 | for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++) { |
| 903 | 939 | ab3100_platform_devs[i]->dev.parent = |
| @@ -915,11 +951,13 @@ static int __init ab3100_probe(struct i2c_client *client, · 11 unmodified lines | ||
| 915 | 951 | |
| 916 | 952 | return 0; |
| 917 | 953 | |
| 954 | + exit_no_ops: | |
| 918 | 955 | exit_no_irq: |
| 919 | 956 | exit_no_setup: |
| 920 | 957 | i2c_unregister_device(ab3100->testreg_client); |
| 921 | 958 | exit_no_testreg_client: |
| 922 | 959 | exit_no_detect: |
| 960 | + i2c_set_clientdata(client, NULL); | |
| 923 | 961 | kfree(ab3100); |
| 924 | 962 | return err; |
| 925 | 963 | } |
| @@ -941,6 +979,7 @@ static int __exit ab3100_remove(struct i2c_client *client) · 15 unmodified lines | ||
| 941 | 979 | * their notifiers so deactivate IRQ |
| 942 | 980 | */ |
| 943 | 981 | free_irq(client->irq, ab3100); |
| 982 | + i2c_set_clientdata(client, NULL); | |
| 944 | 983 | kfree(ab3100); |
| 945 | 984 | return 0; |
| 946 | 985 | } |
| @@ -12,7 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | #include <linux/slab.h> |
| 13 | 13 | #include <linux/init.h> |
| 14 | 14 | #include <linux/platform_device.h> |
| 15 | −#include <linux/mfd/ab3100.h> | |
| 15 | +#include <linux/mfd/abx500.h> | |
| 16 | 16 | #include <linux/debugfs.h> |
| 17 | 17 | #include <linux/seq_file.h> |
| 18 | 18 | |
| @@ -30,7 +30,6 @@ · 11 unmodified lines | ||
| 30 | 30 | /** |
| 31 | 31 | * struct ab3100_otp |
| 32 | 32 | * @dev containing device |
| 33 | − * @ab3100 a pointer to the parent ab3100 device struct | |
| 34 | 33 | * @locked whether the OTP is locked, after locking, no more bits |
| 35 | 34 | * can be changed but before locking it is still possible |
| 36 | 35 | * to change bits from 1->0. |
| @@ -49,7 +48,6 @@ · 12 unmodified lines | ||
| 49 | 48 | */ |
| 50 | 49 | struct ab3100_otp { |
| 51 | 50 | struct device *dev; |
| 52 | − struct ab3100 *ab3100; | |
| 53 | 51 | bool locked; |
| 54 | 52 | u32 freq; |
| 55 | 53 | bool paf; |
| @@ -63,19 +61,19 @@ struct ab3100_otp { · 7 unmodified lines | ||
| 63 | 61 | |
| 64 | 62 | static int __init ab3100_otp_read(struct ab3100_otp *otp) |
| 65 | 63 | { |
| 66 | − struct ab3100 *ab = otp->ab3100; | |
| 67 | 64 | u8 otpval[8]; |
| 68 | 65 | u8 otpp; |
| 69 | 66 | int err; |
| 70 | 67 | |
| 71 | − err = ab3100_get_register_interruptible(ab, AB3100_OTPP, &otpp); | |
| 68 | + err = abx500_get_register_interruptible(otp->dev, 0, | |
| 69 | + AB3100_OTPP, &otpp); | |
| 72 | 70 | if (err) { |
| 73 | 71 | dev_err(otp->dev, "unable to read OTPP register\n"); |
| 74 | 72 | return err; |
| 75 | 73 | } |
| 76 | 74 | |
| 77 | − err = ab3100_get_register_page_interruptible(ab, AB3100_OTP0, | |
| 78 | − otpval, 8); | |
| 75 | + err = abx500_get_register_page_interruptible(otp->dev, 0, | |
| 76 | + AB3100_OTP0, otpval, 8); | |
| 79 | 77 | if (err) { |
| 80 | 78 | dev_err(otp->dev, "unable to read OTP register page\n"); |
| 81 | 79 | return err; |
| @@ -197,7 +195,6 @@ static int __init ab3100_otp_probe(struct platform_device *pdev) · 115 unmodified lines | ||
| 197 | 195 | otp->dev = &pdev->dev; |
| 198 | 196 | |
| 199 | 197 | /* Replace platform data coming in with a local struct */ |
| 200 | − otp->ab3100 = platform_get_drvdata(pdev); | |
| 201 | 198 | platform_set_drvdata(pdev, otp); |
| 202 | 199 | |
| 203 | 200 | err = ab3100_otp_read(otp); |
| @@ -0,0 +1,1401 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2007-2010 ST-Ericsson | |
| 3 | + * License terms: GNU General Public License (GPL) version 2 | |
| 4 | + * Low-level core for exclusive access to the AB3550 IC on the I2C bus | |
| 5 | + * and some basic chip-configuration. | |
| 6 | + * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> | |
| 7 | + * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> | |
| 8 | + * Author: Mattias Wallin <mattias.wallin@stericsson.com> | |
| 9 | + * Author: Rickard Andersson <rickard.andersson@stericsson.com> | |
| 10 | + */ | |
| 11 | + | |
| 12 | +#include <linux/i2c.h> | |
| 13 | +#include <linux/mutex.h> | |
| 14 | +#include <linux/err.h> | |
| 15 | +#include <linux/platform_device.h> | |
| 16 | +#include <linux/slab.h> | |
| 17 | +#include <linux/device.h> | |
| 18 | +#include <linux/irq.h> | |
| 19 | +#include <linux/interrupt.h> | |
| 20 | +#include <linux/random.h> | |
| 21 | +#include <linux/workqueue.h> | |
| 22 | +#include <linux/debugfs.h> | |
| 23 | +#include <linux/seq_file.h> | |
| 24 | +#include <linux/uaccess.h> | |
| 25 | +#include <linux/mfd/abx500.h> | |
| 26 | +#include <linux/list.h> | |
| 27 | +#include <linux/bitops.h> | |
| 28 | +#include <linux/spinlock.h> | |
| 29 | +#include <linux/mfd/core.h> | |
| 30 | + | |
| 31 | +#define AB3550_NAME_STRING "ab3550" | |
| 32 | +#define AB3550_ID_FORMAT_STRING "AB3550 %s" | |
| 33 | +#define AB3550_NUM_BANKS 2 | |
| 34 | +#define AB3550_NUM_EVENT_REG 5 | |
| 35 | + | |
| 36 | +/* These are the only registers inside AB3550 used in this main file */ | |
| 37 | + | |
| 38 | +/* Chip ID register */ | |
| 39 | +#define AB3550_CID_REG 0x20 | |
| 40 | + | |
| 41 | +/* Interrupt event registers */ | |
| 42 | +#define AB3550_EVENT_BANK 0 | |
| 43 | +#define AB3550_EVENT_REG 0x22 | |
| 44 | + | |
| 45 | +/* Read/write operation values. */ | |
| 46 | +#define AB3550_PERM_RD (0x01) | |
| 47 | +#define AB3550_PERM_WR (0x02) | |
| 48 | + | |
| 49 | +/* Read/write permissions. */ | |
| 50 | +#define AB3550_PERM_RO (AB3550_PERM_RD) | |
| 51 | +#define AB3550_PERM_RW (AB3550_PERM_RD | AB3550_PERM_WR) | |
| 52 | + | |
| 53 | +/** | |
| 54 | + * struct ab3550 | |
| 55 | + * @access_mutex: lock out concurrent accesses to the AB registers | |
| 56 | + * @i2c_client: I2C client for this chip | |
| 57 | + * @chip_name: name of this chip variant | |
| 58 | + * @chip_id: 8 bit chip ID for this chip variant | |
| 59 | + * @mask_work: a worker for writing to mask registers | |
| 60 | + * @event_lock: a lock to protect the event_mask | |
| 61 | + * @event_mask: a local copy of the mask event registers | |
| 62 | + * @startup_events: a copy of the first reading of the event registers | |
| 63 | + * @startup_events_read: whether the first events have been read | |
| 64 | + */ | |
| 65 | +struct ab3550 { | |
| 66 | + struct mutex access_mutex; | |
| 67 | + struct i2c_client *i2c_client[AB3550_NUM_BANKS]; | |
| 68 | + char chip_name[32]; | |
| 69 | + u8 chip_id; | |
| 70 | + struct work_struct mask_work; | |
| 71 | + spinlock_t event_lock; | |
| 72 | + u8 event_mask[AB3550_NUM_EVENT_REG]; | |
| 73 | + u8 startup_events[AB3550_NUM_EVENT_REG]; | |
| 74 | + bool startup_events_read; | |
| 75 | +#ifdef CONFIG_DEBUG_FS | |
| 76 | + unsigned int debug_bank; | |
| 77 | + unsigned int debug_address; | |
| 78 | +#endif | |
| 79 | +}; | |
| 80 | + | |
| 81 | +/** | |
| 82 | + * struct ab3550_reg_range | |
| 83 | + * @first: the first address of the range | |
| 84 | + * @last: the last address of the range | |
| 85 | + * @perm: access permissions for the range | |
| 86 | + */ | |
| 87 | +struct ab3550_reg_range { | |
| 88 | + u8 first; | |
| 89 | + u8 last; | |
| 90 | + u8 perm; | |
| 91 | +}; | |
| 92 | + | |
| 93 | +/** | |
| 94 | + * struct ab3550_reg_ranges | |
| 95 | + * @count: the number of ranges in the list | |
| 96 | + * @range: the list of register ranges | |
| 97 | + */ | |
| 98 | +struct ab3550_reg_ranges { | |
| 99 | + u8 count; | |
| 100 | + const struct ab3550_reg_range *range; | |
| 101 | +}; | |
| 102 | + | |
| 103 | +/* | |
| 104 | + * Permissible register ranges for reading and writing per device and bank. | |
| 105 | + * | |
| 106 | + * The ranges must be listed in increasing address order, and no overlaps are | |
| 107 | + * allowed. It is assumed that write permission implies read permission | |
| 108 | + * (i.e. only RO and RW permissions should be used). Ranges with write | |
| 109 | + * permission must not be split up. | |
| 110 | + */ | |
| 111 | + | |
| 112 | +#define NO_RANGE {.count = 0, .range = NULL,} | |
| 113 | + | |
| 114 | +static struct | |
| 115 | +ab3550_reg_ranges ab3550_reg_ranges[AB3550_NUM_DEVICES][AB3550_NUM_BANKS] = { | |
| 116 | + [AB3550_DEVID_DAC] = { | |
| 117 | + NO_RANGE, | |
| 118 | + { | |
| 119 | + .count = 2, | |
| 120 | + .range = (struct ab3550_reg_range[]) { | |
| 121 | + { | |
| 122 | + .first = 0xb0, | |
| 123 | + .last = 0xba, | |
| 124 | + .perm = AB3550_PERM_RW, | |
| 125 | + }, | |
| 126 | + { | |
| 127 | + .first = 0xbc, | |
| 128 | + .last = 0xc3, | |
| 129 | + .perm = AB3550_PERM_RW, | |
| 130 | + }, | |
| 131 | + }, | |
| 132 | + }, | |
| 133 | + }, | |
| 134 | + [AB3550_DEVID_LEDS] = { | |
| 135 | + NO_RANGE, | |
| 136 | + { | |
| 137 | + .count = 2, | |
| 138 | + .range = (struct ab3550_reg_range[]) { | |
| 139 | + { | |
| 140 | + .first = 0x5a, | |
| 141 | + .last = 0x88, | |
| 142 | + .perm = AB3550_PERM_RW, | |
| 143 | + }, | |
| 144 | + { | |
| 145 | + .first = 0x8a, | |
| 146 | + .last = 0xad, | |
| 147 | + .perm = AB3550_PERM_RW, | |
| 148 | + }, | |
| 149 | + } | |
| 150 | + }, | |
| 151 | + }, | |
| 152 | + [AB3550_DEVID_POWER] = { | |
| 153 | + { | |
| 154 | + .count = 1, | |
| 155 | + .range = (struct ab3550_reg_range[]) { | |
| 156 | + { | |
| 157 | + .first = 0x21, | |
| 158 | + .last = 0x21, | |
| 159 | + .perm = AB3550_PERM_RO, | |
| 160 | + }, | |
| 161 | + } | |
| 162 | + }, | |
| 163 | + NO_RANGE, | |
| 164 | + }, | |
| 165 | + [AB3550_DEVID_REGULATORS] = { | |
| 166 | + { | |
| 167 | + .count = 1, | |
| 168 | + .range = (struct ab3550_reg_range[]) { | |
| 169 | + { | |
| 170 | + .first = 0x69, | |
| 171 | + .last = 0xa3, | |
| 172 | + .perm = AB3550_PERM_RW, | |
| 173 | + }, | |
| 174 | + } | |
| 175 | + }, | |
| 176 | + { | |
| 177 | + .count = 1, | |
| 178 | + .range = (struct ab3550_reg_range[]) { | |
| 179 | + { | |
| 180 | + .first = 0x14, | |
| 181 | + .last = 0x16, | |
| 182 | + .perm = AB3550_PERM_RW, | |
| 183 | + }, | |
| 184 | + } | |
| 185 | + }, | |
| 186 | + }, | |
| 187 | + [AB3550_DEVID_SIM] = { | |
| 188 | + { | |
| 189 | + .count = 1, | |
| 190 | + .range = (struct ab3550_reg_range[]) { | |
| 191 | + { | |
| 192 | + .first = 0x21, | |
| 193 | + .last = 0x21, | |
| 194 | + .perm = AB3550_PERM_RO, | |
| 195 | + }, | |
| 196 | + } | |
| 197 | + }, | |
| 198 | + { | |
| 199 | + .count = 1, | |
| 200 | + .range = (struct ab3550_reg_range[]) { | |
| 201 | + { | |
| 202 | + .first = 0x14, | |
| 203 | + .last = 0x17, | |
| 204 | + .perm = AB3550_PERM_RW, | |
| 205 | + }, | |
| 206 | + } | |
| 207 | + | |
| 208 | + }, | |
| 209 | + }, | |
| 210 | + [AB3550_DEVID_UART] = { | |
| 211 | + NO_RANGE, | |
| 212 | + NO_RANGE, | |
| 213 | + }, | |
| 214 | + [AB3550_DEVID_RTC] = { | |
| 215 | + { | |
| 216 | + .count = 1, | |
| 217 | + .range = (struct ab3550_reg_range[]) { | |
| 218 | + { | |
| 219 | + .first = 0x00, | |
| 220 | + .last = 0x0c, | |
| 221 | + .perm = AB3550_PERM_RW, | |
| 222 | + }, | |
| 223 | + } | |
| 224 | + }, | |
| 225 | + NO_RANGE, | |
| 226 | + }, | |
| 227 | + [AB3550_DEVID_CHARGER] = { | |
| 228 | + { | |
| 229 | + .count = 2, | |
| 230 | + .range = (struct ab3550_reg_range[]) { | |
| 231 | + { | |
| 232 | + .first = 0x10, | |
| 233 | + .last = 0x1a, | |
| 234 | + .perm = AB3550_PERM_RW, | |
| 235 | + }, | |
| 236 | + { | |
| 237 | + .first = 0x21, | |
| 238 | + .last = 0x21, | |
| 239 | + .perm = AB3550_PERM_RO, | |
| 240 | + }, | |
| 241 | + } | |
| 242 | + }, | |
| 243 | + NO_RANGE, | |
| 244 | + }, | |
| 245 | + [AB3550_DEVID_ADC] = { | |
| 246 | + NO_RANGE, | |
| 247 | + { | |
| 248 | + .count = 1, | |
| 249 | + .range = (struct ab3550_reg_range[]) { | |
| 250 | + { | |
| 251 | + .first = 0x20, | |
| 252 | + .last = 0x56, | |
| 253 | + .perm = AB3550_PERM_RW, | |
| 254 | + }, | |
| 255 | + | |
| 256 | + } | |
| 257 | + }, | |
| 258 | + }, | |
| 259 | + [AB3550_DEVID_FUELGAUGE] = { | |
| 260 | + { | |
| 261 | + .count = 1, | |
| 262 | + .range = (struct ab3550_reg_range[]) { | |
| 263 | + { | |
| 264 | + .first = 0x21, | |
| 265 | + .last = 0x21, | |
| 266 | + .perm = AB3550_PERM_RO, | |
| 267 | + }, | |
| 268 | + } | |
| 269 | + }, | |
| 270 | + { | |
| 271 | + .count = 1, | |
| 272 | + .range = (struct ab3550_reg_range[]) { | |
| 273 | + { | |
| 274 | + .first = 0x00, | |
| 275 | + .last = 0x0e, | |
| 276 | + .perm = AB3550_PERM_RW, | |
| 277 | + }, | |
| 278 | + } | |
| 279 | + }, | |
| 280 | + }, | |
| 281 | + [AB3550_DEVID_VIBRATOR] = { | |
| 282 | + NO_RANGE, | |
| 283 | + { | |
| 284 | + .count = 1, | |
| 285 | + .range = (struct ab3550_reg_range[]) { | |
| 286 | + { | |
| 287 | + .first = 0x10, | |
| 288 | + .last = 0x13, | |
| 289 | + .perm = AB3550_PERM_RW, | |
| 290 | + }, | |
| 291 | + | |
| 292 | + } | |
| 293 | + }, | |
| 294 | + }, | |
| 295 | + [AB3550_DEVID_CODEC] = { | |
| 296 | + { | |
| 297 | + .count = 2, | |
| 298 | + .range = (struct ab3550_reg_range[]) { | |
| 299 | + { | |
| 300 | + .first = 0x31, | |
| 301 | + .last = 0x63, | |
| 302 | + .perm = AB3550_PERM_RW, | |
| 303 | + }, | |
| 304 | + { | |
| 305 | + .first = 0x65, | |
| 306 | + .last = 0x68, | |
| 307 | + .perm = AB3550_PERM_RW, | |
| 308 | + }, | |
| 309 | + } | |
| 310 | + }, | |
| 311 | + NO_RANGE, | |
| 312 | + }, | |
| 313 | +}; | |
| 314 | + | |
| 315 | +static struct mfd_cell ab3550_devs[AB3550_NUM_DEVICES] = { | |
| 316 | + [AB3550_DEVID_DAC] = { | |
| 317 | + .name = "ab3550-dac", | |
| 318 | + .id = AB3550_DEVID_DAC, | |
| 319 | + .num_resources = 0, | |
| 320 | + }, | |
| 321 | + [AB3550_DEVID_LEDS] = { | |
| 322 | + .name = "ab3550-leds", | |
| 323 | + .id = AB3550_DEVID_LEDS, | |
| 324 | + }, | |
| 325 | + [AB3550_DEVID_POWER] = { | |
| 326 | + .name = "ab3550-power", | |
| 327 | + .id = AB3550_DEVID_POWER, | |
| 328 | + }, | |
| 329 | + [AB3550_DEVID_REGULATORS] = { | |
| 330 | + .name = "ab3550-regulators", | |
| 331 | + .id = AB3550_DEVID_REGULATORS, | |
| 332 | + }, | |
| 333 | + [AB3550_DEVID_SIM] = { | |
| 334 | + .name = "ab3550-sim", | |
| 335 | + .id = AB3550_DEVID_SIM, | |
| 336 | + }, | |
| 337 | + [AB3550_DEVID_UART] = { | |
| 338 | + .name = "ab3550-uart", | |
| 339 | + .id = AB3550_DEVID_UART, | |
| 340 | + }, | |
| 341 | + [AB3550_DEVID_RTC] = { | |
| 342 | + .name = "ab3550-rtc", | |
| 343 | + .id = AB3550_DEVID_RTC, | |
| 344 | + }, | |
| 345 | + [AB3550_DEVID_CHARGER] = { | |
| 346 | + .name = "ab3550-charger", | |
| 347 | + .id = AB3550_DEVID_CHARGER, | |
| 348 | + }, | |
| 349 | + [AB3550_DEVID_ADC] = { | |
| 350 | + .name = "ab3550-adc", | |
| 351 | + .id = AB3550_DEVID_ADC, | |
| 352 | + .num_resources = 10, | |
| 353 | + .resources = (struct resource[]) { | |
| 354 | + { | |
| 355 | + .name = "TRIGGER-0", | |
| 356 | + .flags = IORESOURCE_IRQ, | |
| 357 | + .start = 16, | |
| 358 | + .end = 16, | |
| 359 | + }, | |
| 360 | + { | |
| 361 | + .name = "TRIGGER-1", | |
| 362 | + .flags = IORESOURCE_IRQ, | |
| 363 | + .start = 17, | |
| 364 | + .end = 17, | |
| 365 | + }, | |
| 366 | + { | |
| 367 | + .name = "TRIGGER-2", | |
| 368 | + .flags = IORESOURCE_IRQ, | |
| 369 | + .start = 18, | |
| 370 | + .end = 18, | |
| 371 | + }, | |
| 372 | + { | |
| 373 | + .name = "TRIGGER-3", | |
| 374 | + .flags = IORESOURCE_IRQ, | |
| 375 | + .start = 19, | |
| 376 | + .end = 19, | |
| 377 | + }, | |
| 378 | + { | |
| 379 | + .name = "TRIGGER-4", | |
| 380 | + .flags = IORESOURCE_IRQ, | |
| 381 | + .start = 20, | |
| 382 | + .end = 20, | |
| 383 | + }, | |
| 384 | + { | |
| 385 | + .name = "TRIGGER-5", | |
| 386 | + .flags = IORESOURCE_IRQ, | |
| 387 | + .start = 21, | |
| 388 | + .end = 21, | |
| 389 | + }, | |
| 390 | + { | |
| 391 | + .name = "TRIGGER-6", | |
| 392 | + .flags = IORESOURCE_IRQ, | |
| 393 | + .start = 22, | |
| 394 | + .end = 22, | |
| 395 | + }, | |
| 396 | + { | |
| 397 | + .name = "TRIGGER-7", | |
| 398 | + .flags = IORESOURCE_IRQ, | |
| 399 | + .start = 23, | |
| 400 | + .end = 23, | |
| 401 | + }, | |
| 402 | + { | |
| 403 | + .name = "TRIGGER-VBAT-TXON", | |
| 404 | + .flags = IORESOURCE_IRQ, | |
| 405 | + .start = 13, | |
| 406 | + .end = 13, | |
| 407 | + }, | |
| 408 | + { | |
| 409 | + .name = "TRIGGER-VBAT", | |
| 410 | + .flags = IORESOURCE_IRQ, | |
| 411 | + .start = 12, | |
| 412 | + .end = 12, | |
| 413 | + }, | |
| 414 | + }, | |
| 415 | + }, | |
| 416 | + [AB3550_DEVID_FUELGAUGE] = { | |
| 417 | + .name = "ab3550-fuelgauge", | |
| 418 | + .id = AB3550_DEVID_FUELGAUGE, | |
| 419 | + }, | |
| 420 | + [AB3550_DEVID_VIBRATOR] = { | |
| 421 | + .name = "ab3550-vibrator", | |
| 422 | + .id = AB3550_DEVID_VIBRATOR, | |
| 423 | + }, | |
| 424 | + [AB3550_DEVID_CODEC] = { | |
| 425 | + .name = "ab3550-codec", | |
| 426 | + .id = AB3550_DEVID_CODEC, | |
| 427 | + }, | |
| 428 | +}; | |
| 429 | + | |
| 430 | +/* | |
| 431 | + * I2C transactions with error messages. | |
| 432 | + */ | |
| 433 | +static int ab3550_i2c_master_send(struct ab3550 *ab, u8 bank, u8 *data, | |
| 434 | + u8 count) | |
| 435 | +{ | |
| 436 | + int err; | |
| 437 | + | |
| 438 | + err = i2c_master_send(ab->i2c_client[bank], data, count); | |
| 439 | + if (err < 0) { | |
| 440 | + dev_err(&ab->i2c_client[0]->dev, "send error: %d\n", err); | |
| 441 | + return err; | |
| 442 | + } | |
| 443 | + return 0; | |
| 444 | +} | |
| 445 | + | |
| 446 | +static int ab3550_i2c_master_recv(struct ab3550 *ab, u8 bank, u8 *data, | |
| 447 | + u8 count) | |
| 448 | +{ | |
| 449 | + int err; | |
| 450 | + | |
| 451 | + err = i2c_master_recv(ab->i2c_client[bank], data, count); | |
| 452 | + if (err < 0) { | |
| 453 | + dev_err(&ab->i2c_client[0]->dev, "receive error: %d\n", err); | |
| 454 | + return err; | |
| 455 | + } | |
| 456 | + return 0; | |
| 457 | +} | |
| 458 | + | |
| 459 | +/* | |
| 460 | + * Functionality for getting/setting register values. | |
| 461 | + */ | |
| 462 | +static int get_register_interruptible(struct ab3550 *ab, u8 bank, u8 reg, | |
| 463 | + u8 *value) | |
| 464 | +{ | |
| 465 | + int err; | |
| 466 | + | |
| 467 | + err = mutex_lock_interruptible(&ab->access_mutex); | |
| 468 | + if (err) | |
| 469 | + return err; | |
| 470 | + | |
| 471 | + err = ab3550_i2c_master_send(ab, bank, ®, 1); | |
| 472 | + if (!err) | |
| 473 | + err = ab3550_i2c_master_recv(ab, bank, value, 1); | |
| 474 | + | |
| 475 | + mutex_unlock(&ab->access_mutex); | |
| 476 | + return err; | |
| 477 | +} | |
| 478 | + | |
| 479 | +static int get_register_page_interruptible(struct ab3550 *ab, u8 bank, | |
| 480 | + u8 first_reg, u8 *regvals, u8 numregs) | |
| 481 | +{ | |
| 482 | + int err; | |
| 483 | + | |
| 484 | + err = mutex_lock_interruptible(&ab->access_mutex); | |
| 485 | + if (err) | |
| 486 | + return err; | |
| 487 | + | |
| 488 | + err = ab3550_i2c_master_send(ab, bank, &first_reg, 1); | |
| 489 | + if (!err) | |
| 490 | + err = ab3550_i2c_master_recv(ab, bank, regvals, numregs); | |
| 491 | + | |
| 492 | + mutex_unlock(&ab->access_mutex); | |
| 493 | + return err; | |
| 494 | +} | |
| 495 | + | |
| 496 | +static int mask_and_set_register_interruptible(struct ab3550 *ab, u8 bank, | |
| 497 | + u8 reg, u8 bitmask, u8 bitvalues) | |
| 498 | +{ | |
| 499 | + int err = 0; | |
| 500 | + | |
| 501 | + if (likely(bitmask)) { | |
| 502 | + u8 reg_bits[2] = {reg, 0}; | |
| 503 | + | |
| 504 | + err = mutex_lock_interruptible(&ab->access_mutex); | |
| 505 | + if (err) | |
| 506 | + return err; | |
| 507 | + | |
| 508 | + if (bitmask == 0xFF) /* No need to read in this case. */ | |
| 509 | + reg_bits[1] = bitvalues; | |
| 510 | + else { /* Read and modify the register value. */ | |
| 511 | + u8 bits; | |
| 512 | + | |
| 513 | + err = ab3550_i2c_master_send(ab, bank, ®, 1); | |
| 514 | + if (err) | |
| 515 | + goto unlock_and_return; | |
| 516 | + err = ab3550_i2c_master_recv(ab, bank, &bits, 1); | |
| 517 | + if (err) | |
| 518 | + goto unlock_and_return; | |
| 519 | + reg_bits[1] = ((~bitmask & bits) | | |
| 520 | + (bitmask & bitvalues)); | |
| 521 | + } | |
| 522 | + /* Write the new value. */ | |
| 523 | + err = ab3550_i2c_master_send(ab, bank, reg_bits, 2); | |
| 524 | +unlock_and_return: | |
| 525 | + mutex_unlock(&ab->access_mutex); | |
| 526 | + } | |
| 527 | + return err; | |
| 528 | +} | |
| 529 | + | |
| 530 | +/* | |
| 531 | + * Read/write permission checking functions. | |
| 532 | + */ | |
| 533 | +static bool page_write_allowed(const struct ab3550_reg_ranges *ranges, | |
| 534 | + u8 first_reg, u8 last_reg) | |
| 535 | +{ | |
| 536 | + u8 i; | |
| 537 | + | |
| 538 | + if (last_reg < first_reg) | |
| 539 | + return false; | |
| 540 | + | |
| 541 | + for (i = 0; i < ranges->count; i++) { | |
| 542 | + if (first_reg < ranges->range[i].first) | |
| 543 | + break; | |
| 544 | + if ((last_reg <= ranges->range[i].last) && | |
| 545 | + (ranges->range[i].perm & AB3550_PERM_WR)) | |
| 546 | + return true; | |
| 547 | + } | |
| 548 | + return false; | |
| 549 | +} | |
| 550 | + | |
| 551 | +static bool reg_write_allowed(const struct ab3550_reg_ranges *ranges, u8 reg) | |
| 552 | +{ | |
| 553 | + return page_write_allowed(ranges, reg, reg); | |
| 554 | +} | |
| 555 | + | |
| 556 | +static bool page_read_allowed(const struct ab3550_reg_ranges *ranges, | |
| 557 | + u8 first_reg, u8 last_reg) | |
| 558 | +{ | |
| 559 | + u8 i; | |
| 560 | + | |
| 561 | + if (last_reg < first_reg) | |
| 562 | + return false; | |
| 563 | + /* Find the range (if it exists in the list) that includes first_reg. */ | |
| 564 | + for (i = 0; i < ranges->count; i++) { | |
| 565 | + if (first_reg < ranges->range[i].first) | |
| 566 | + return false; | |
| 567 | + if (first_reg <= ranges->range[i].last) | |
| 568 | + break; | |
| 569 | + } | |
| 570 | + /* Make sure that the entire range up to and including last_reg is | |
| 571 | + * readable. This may span several of the ranges in the list. | |
| 572 | + */ | |
| 573 | + while ((i < ranges->count) && | |
| 574 | + (ranges->range[i].perm & AB3550_PERM_RD)) { | |
| 575 | + if (last_reg <= ranges->range[i].last) | |
| 576 | + return true; | |
| 577 | + if ((++i >= ranges->count) || | |
| 578 | + (ranges->range[i].first != | |
| 579 | + (ranges->range[i - 1].last + 1))) { | |
| 580 | + break; | |
| 581 | + } | |
| 582 | + } | |
| 583 | + return false; | |
| 584 | +} | |
| 585 | + | |
| 586 | +static bool reg_read_allowed(const struct ab3550_reg_ranges *ranges, u8 reg) | |
| 587 | +{ | |
| 588 | + return page_read_allowed(ranges, reg, reg); | |
| 589 | +} | |
| 590 | + | |
| 591 | +/* | |
| 592 | + * The exported register access functionality. | |
| 593 | + */ | |
| 594 | +int ab3550_get_chip_id(struct device *dev) | |
| 595 | +{ | |
| 596 | + struct ab3550 *ab = dev_get_drvdata(dev->parent); | |
| 597 | + return (int)ab->chip_id; | |
| 598 | +} | |
| 599 | + | |
| 600 | +int ab3550_mask_and_set_register_interruptible(struct device *dev, u8 bank, | |
| 601 | + u8 reg, u8 bitmask, u8 bitvalues) | |
| 602 | +{ | |
| 603 | + struct ab3550 *ab; | |
| 604 | + struct platform_device *pdev = to_platform_device(dev); | |
| 605 | + | |
| 606 | + if ((AB3550_NUM_BANKS <= bank) || | |
| 607 | + !reg_write_allowed(&ab3550_reg_ranges[pdev->id][bank], reg)) | |
| 608 | + return -EINVAL; | |
| 609 | + | |
| 610 | + ab = dev_get_drvdata(dev->parent); | |
| 611 | + return mask_and_set_register_interruptible(ab, bank, reg, | |
| 612 | + bitmask, bitvalues); | |
| 613 | +} | |
| 614 | + | |
| 615 | +int ab3550_set_register_interruptible(struct device *dev, u8 bank, u8 reg, | |
| 616 | + u8 value) | |
| 617 | +{ | |
| 618 | + return ab3550_mask_and_set_register_interruptible(dev, bank, reg, 0xFF, | |
| 619 | + value); | |
| 620 | +} | |
| 621 | + | |
| 622 | +int ab3550_get_register_interruptible(struct device *dev, u8 bank, u8 reg, | |
| 623 | + u8 *value) | |
| 624 | +{ | |
| 625 | + struct ab3550 *ab; | |
| 626 | + struct platform_device *pdev = to_platform_device(dev); | |
| 627 | + | |
| 628 | + if ((AB3550_NUM_BANKS <= bank) || | |
| 629 | + !reg_read_allowed(&ab3550_reg_ranges[pdev->id][bank], reg)) | |
| 630 | + return -EINVAL; | |
| 631 | + | |
| 632 | + ab = dev_get_drvdata(dev->parent); | |
| 633 | + return get_register_interruptible(ab, bank, reg, value); | |
| 634 | +} | |
| 635 | + | |
| 636 | +int ab3550_get_register_page_interruptible(struct device *dev, u8 bank, | |
| 637 | + u8 first_reg, u8 *regvals, u8 numregs) | |
| 638 | +{ | |
| 639 | + struct ab3550 *ab; | |
| 640 | + struct platform_device *pdev = to_platform_device(dev); | |
| 641 | + | |
| 642 | + if ((AB3550_NUM_BANKS <= bank) || | |
| 643 | + !page_read_allowed(&ab3550_reg_ranges[pdev->id][bank], | |
| 644 | + first_reg, (first_reg + numregs - 1))) | |
| 645 | + return -EINVAL; | |
| 646 | + | |
| 647 | + ab = dev_get_drvdata(dev->parent); | |
| 648 | + return get_register_page_interruptible(ab, bank, first_reg, regvals, | |
| 649 | + numregs); | |
| 650 | +} | |
| 651 | + | |
| 652 | +int ab3550_event_registers_startup_state_get(struct device *dev, u8 *event) | |
| 653 | +{ | |
| 654 | + struct ab3550 *ab; | |
| 655 | + | |
| 656 | + ab = dev_get_drvdata(dev->parent); | |
| 657 | + if (!ab->startup_events_read) | |
| 658 | + return -EAGAIN; /* Try again later */ | |
| 659 | + | |
| 660 | + memcpy(event, ab->startup_events, AB3550_NUM_EVENT_REG); | |
| 661 | + return 0; | |
| 662 | +} | |
| 663 | + | |
| 664 | +int ab3550_startup_irq_enabled(struct device *dev, unsigned int irq) | |
| 665 | +{ | |
| 666 | + struct ab3550 *ab; | |
| 667 | + struct ab3550_platform_data *plf_data; | |
| 668 | + bool val; | |
| 669 | + | |
| 670 | + ab = get_irq_chip_data(irq); | |
| 671 | + plf_data = ab->i2c_client[0]->dev.platform_data; | |
| 672 | + irq -= plf_data->irq.base; | |
| 673 | + val = ((ab->startup_events[irq / 8] & BIT(irq % 8)) != 0); | |
| 674 | + | |
| 675 | + return val; | |
| 676 | +} | |
| 677 | + | |
| 678 | +static struct abx500_ops ab3550_ops = { | |
| 679 | + .get_chip_id = ab3550_get_chip_id, | |
| 680 | + .get_register = ab3550_get_register_interruptible, | |
| 681 | + .set_register = ab3550_set_register_interruptible, | |
| 682 | + .get_register_page = ab3550_get_register_page_interruptible, | |
| 683 | + .set_register_page = NULL, | |
| 684 | + .mask_and_set_register = ab3550_mask_and_set_register_interruptible, | |
| 685 | + .event_registers_startup_state_get = | |
| 686 | + ab3550_event_registers_startup_state_get, | |
| 687 | + .startup_irq_enabled = ab3550_startup_irq_enabled, | |
| 688 | +}; | |
| 689 | + | |
| 690 | +static irqreturn_t ab3550_irq_handler(int irq, void *data) | |
| 691 | +{ | |
| 692 | + struct ab3550 *ab = data; | |
| 693 | + int err; | |
| 694 | + unsigned int i; | |
| 695 | + u8 e[AB3550_NUM_EVENT_REG]; | |
| 696 | + u8 *events; | |
| 697 | + unsigned long flags; | |
| 698 | + | |
| 699 | + events = (ab->startup_events_read ? e : ab->startup_events); | |
| 700 | + | |
| 701 | + err = get_register_page_interruptible(ab, AB3550_EVENT_BANK, | |
| 702 | + AB3550_EVENT_REG, events, AB3550_NUM_EVENT_REG); | |
| 703 | + if (err) | |
| 704 | + goto err_event_rd; | |
| 705 | + | |
| 706 | + if (!ab->startup_events_read) { | |
| 707 | + dev_info(&ab->i2c_client[0]->dev, | |
| 708 | + "startup events 0x%x,0x%x,0x%x,0x%x,0x%x\n", | |
| 709 | + ab->startup_events[0], ab->startup_events[1], | |
| 710 | + ab->startup_events[2], ab->startup_events[3], | |
| 711 | + ab->startup_events[4]); | |
| 712 | + ab->startup_events_read = true; | |
| 713 | + goto out; | |
| 714 | + } | |
| 715 | + | |
| 716 | + /* The two highest bits in event[4] are not used. */ | |
| 717 | + events[4] &= 0x3f; | |
| 718 | + | |
| 719 | + spin_lock_irqsave(&ab->event_lock, flags); | |
| 720 | + for (i = 0; i < AB3550_NUM_EVENT_REG; i++) | |
| 721 | + events[i] &= ~ab->event_mask[i]; | |
| 722 | + spin_unlock_irqrestore(&ab->event_lock, flags); | |
| 723 | + | |
| 724 | + for (i = 0; i < AB3550_NUM_EVENT_REG; i++) { | |
| 725 | + u8 bit; | |
| 726 | + u8 event_reg; | |
| 727 | + | |
| 728 | + dev_dbg(&ab->i2c_client[0]->dev, "IRQ Event[%d]: 0x%2x\n", | |
| 729 | + i, events[i]); | |
| 730 | + | |
| 731 | + event_reg = events[i]; | |
| 732 | + for (bit = 0; event_reg; bit++, event_reg /= 2) { | |
| 733 | + if (event_reg % 2) { | |
| 734 | + unsigned int irq; | |
| 735 | + struct ab3550_platform_data *plf_data; | |
| 736 | + | |
| 737 | + plf_data = ab->i2c_client[0]->dev.platform_data; | |
| 738 | + irq = plf_data->irq.base + (i * 8) + bit; | |
| 739 | + handle_nested_irq(irq); | |
| 740 | + } | |
| 741 | + } | |
| 742 | + } | |
| 743 | +out: | |
| 744 | + return IRQ_HANDLED; | |
| 745 | + | |
| 746 | +err_event_rd: | |
| 747 | + dev_dbg(&ab->i2c_client[0]->dev, "error reading event registers\n"); | |
| 748 | + return IRQ_HANDLED; | |
| 749 | +} | |
| 750 | + | |
| 751 | +#ifdef CONFIG_DEBUG_FS | |
| 752 | +static struct ab3550_reg_ranges debug_ranges[AB3550_NUM_BANKS] = { | |
| 753 | + { | |
| 754 | + .count = 6, | |
| 755 | + .range = (struct ab3550_reg_range[]) { | |
| 756 | + { | |
| 757 | + .first = 0x00, | |
| 758 | + .last = 0x0e, | |
| 759 | + }, | |
| 760 | + { | |
| 761 | + .first = 0x10, | |
| 762 | + .last = 0x1a, | |
| 763 | + }, | |
| 764 | + { | |
| 765 | + .first = 0x1e, | |
| 766 | + .last = 0x4f, | |
| 767 | + }, | |
| 768 | + { | |
| 769 | + .first = 0x51, | |
| 770 | + .last = 0x63, | |
| 771 | + }, | |
| 772 | + { | |
| 773 | + .first = 0x65, | |
| 774 | + .last = 0xa3, | |
| 775 | + }, | |
| 776 | + { | |
| 777 | + .first = 0xa5, | |
| 778 | + .last = 0xa8, | |
| 779 | + }, | |
| 780 | + } | |
| 781 | + }, | |
| 782 | + { | |
| 783 | + .count = 8, | |
| 784 | + .range = (struct ab3550_reg_range[]) { | |
| 785 | + { | |
| 786 | + .first = 0x00, | |
| 787 | + .last = 0x0e, | |
| 788 | + }, | |
| 789 | + { | |
| 790 | + .first = 0x10, | |
| 791 | + .last = 0x17, | |
| 792 | + }, | |
| 793 | + { | |
| 794 | + .first = 0x1a, | |
| 795 | + .last = 0x1c, | |
| 796 | + }, | |
| 797 | + { | |
| 798 | + .first = 0x20, | |
| 799 | + .last = 0x56, | |
| 800 | + }, | |
| 801 | + { | |
| 802 | + .first = 0x5a, | |
| 803 | + .last = 0x88, | |
| 804 | + }, | |
| 805 | + { | |
| 806 | + .first = 0x8a, | |
| 807 | + .last = 0xad, | |
| 808 | + }, | |
| 809 | + { | |
| 810 | + .first = 0xb0, | |
| 811 | + .last = 0xba, | |
| 812 | + }, | |
| 813 | + { | |
| 814 | + .first = 0xbc, | |
| 815 | + .last = 0xc3, | |
| 816 | + }, | |
| 817 | + } | |
| 818 | + }, | |
| 819 | +}; | |
| 820 | + | |
| 821 | +static int ab3550_registers_print(struct seq_file *s, void *p) | |
| 822 | +{ | |
| 823 | + struct ab3550 *ab = s->private; | |
| 824 | + int bank; | |
| 825 | + | |
| 826 | + seq_printf(s, AB3550_NAME_STRING " register values:\n"); | |
| 827 | + | |
| 828 | + for (bank = 0; bank < AB3550_NUM_BANKS; bank++) { | |
| 829 | + unsigned int i; | |
| 830 | + | |
| 831 | + seq_printf(s, " bank %d:\n", bank); | |
| 832 | + for (i = 0; i < debug_ranges[bank].count; i++) { | |
| 833 | + u8 reg; | |
| 834 | + | |
| 835 | + for (reg = debug_ranges[bank].range[i].first; | |
| 836 | + reg <= debug_ranges[bank].range[i].last; | |
| 837 | + reg++) { | |
| 838 | + u8 value; | |
| 839 | + | |
| 840 | + get_register_interruptible(ab, bank, reg, | |
| 841 | + &value); | |
| 842 | + seq_printf(s, " [%d/0x%02X]: 0x%02X\n", bank, | |
| 843 | + reg, value); | |
| 844 | + } | |
| 845 | + } | |
| 846 | + } | |
| 847 | + return 0; | |
| 848 | +} | |
| 849 | + | |
| 850 | +static int ab3550_registers_open(struct inode *inode, struct file *file) | |
| 851 | +{ | |
| 852 | + return single_open(file, ab3550_registers_print, inode->i_private); | |
| 853 | +} | |
| 854 | + | |
| 855 | +static const struct file_operations ab3550_registers_fops = { | |
| 856 | + .open = ab3550_registers_open, | |
| 857 | + .read = seq_read, | |
| 858 | + .llseek = seq_lseek, | |
| 859 | + .release = single_release, | |
| 860 | + .owner = THIS_MODULE, | |
| 861 | +}; | |
| 862 | + | |
| 863 | +static int ab3550_bank_print(struct seq_file *s, void *p) | |
| 864 | +{ | |
| 865 | + struct ab3550 *ab = s->private; | |
| 866 | + | |
| 867 | + seq_printf(s, "%d\n", ab->debug_bank); | |
| 868 | + return 0; | |
| 869 | +} | |
| 870 | + | |
| 871 | +static int ab3550_bank_open(struct inode *inode, struct file *file) | |
| 872 | +{ | |
| 873 | + return single_open(file, ab3550_bank_print, inode->i_private); | |
| 874 | +} | |
| 875 | + | |
| 876 | +static ssize_t ab3550_bank_write(struct file *file, | |
| 877 | + const char __user *user_buf, | |
| 878 | + size_t count, loff_t *ppos) | |
| 879 | +{ | |
| 880 | + struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private; | |
| 881 | + char buf[32]; | |
| 882 | + int buf_size; | |
| 883 | + unsigned long user_bank; | |
| 884 | + int err; | |
| 885 | + | |
| 886 | + /* Get userspace string and assure termination */ | |
| 887 | + buf_size = min(count, (sizeof(buf) - 1)); | |
| 888 | + if (copy_from_user(buf, user_buf, buf_size)) | |
| 889 | + return -EFAULT; | |
| 890 | + buf[buf_size] = 0; | |
| 891 | + | |
| 892 | + err = strict_strtoul(buf, 0, &user_bank); | |
| 893 | + if (err) | |
| 894 | + return -EINVAL; | |
| 895 | + | |
| 896 | + if (user_bank >= AB3550_NUM_BANKS) { | |
| 897 | + dev_err(&ab->i2c_client[0]->dev, | |
| 898 | + "debugfs error input > number of banks\n"); | |
| 899 | + return -EINVAL; | |
| 900 | + } | |
| 901 | + | |
| 902 | + ab->debug_bank = user_bank; | |
| 903 | + | |
| 904 | + return buf_size; | |
| 905 | +} | |
| 906 | + | |
| 907 | +static int ab3550_address_print(struct seq_file *s, void *p) | |
| 908 | +{ | |
| 909 | + struct ab3550 *ab = s->private; | |
| 910 | + | |
| 911 | + seq_printf(s, "0x%02X\n", ab->debug_address); | |
| 912 | + return 0; | |
| 913 | +} | |
| 914 | + | |
| 915 | +static int ab3550_address_open(struct inode *inode, struct file *file) | |
| 916 | +{ | |
| 917 | + return single_open(file, ab3550_address_print, inode->i_private); | |
| 918 | +} | |
| 919 | + | |
| 920 | +static ssize_t ab3550_address_write(struct file *file, | |
| 921 | + const char __user *user_buf, | |
| 922 | + size_t count, loff_t *ppos) | |
| 923 | +{ | |
| 924 | + struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private; | |
| 925 | + char buf[32]; | |
| 926 | + int buf_size; | |
| 927 | + unsigned long user_address; | |
| 928 | + int err; | |
| 929 | + | |
| 930 | + /* Get userspace string and assure termination */ | |
| 931 | + buf_size = min(count, (sizeof(buf) - 1)); | |
| 932 | + if (copy_from_user(buf, user_buf, buf_size)) | |
| 933 | + return -EFAULT; | |
| 934 | + buf[buf_size] = 0; | |
| 935 | + | |
| 936 | + err = strict_strtoul(buf, 0, &user_address); | |
| 937 | + if (err) | |
| 938 | + return -EINVAL; | |
| 939 | + if (user_address > 0xff) { | |
| 940 | + dev_err(&ab->i2c_client[0]->dev, | |
| 941 | + "debugfs error input > 0xff\n"); | |
| 942 | + return -EINVAL; | |
| 943 | + } | |
| 944 | + ab->debug_address = user_address; | |
| 945 | + return buf_size; | |
| 946 | +} | |
| 947 | + | |
| 948 | +static int ab3550_val_print(struct seq_file *s, void *p) | |
| 949 | +{ | |
| 950 | + struct ab3550 *ab = s->private; | |
| 951 | + int err; | |
| 952 | + u8 regvalue; | |
| 953 | + | |
| 954 | + err = get_register_interruptible(ab, (u8)ab->debug_bank, | |
| 955 | + (u8)ab->debug_address, ®value); | |
| 956 | + if (err) | |
| 957 | + return -EINVAL; | |
| 958 | + seq_printf(s, "0x%02X\n", regvalue); | |
| 959 | + | |
| 960 | + return 0; | |
| 961 | +} | |
| 962 | + | |
| 963 | +static int ab3550_val_open(struct inode *inode, struct file *file) | |
| 964 | +{ | |
| 965 | + return single_open(file, ab3550_val_print, inode->i_private); | |
| 966 | +} | |
| 967 | + | |
| 968 | +static ssize_t ab3550_val_write(struct file *file, | |
| 969 | + const char __user *user_buf, | |
| 970 | + size_t count, loff_t *ppos) | |
| 971 | +{ | |
| 972 | + struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private; | |
| 973 | + char buf[32]; | |
| 974 | + int buf_size; | |
| 975 | + unsigned long user_val; | |
| 976 | + int err; | |
| 977 | + u8 regvalue; | |
| 978 | + | |
| 979 | + /* Get userspace string and assure termination */ | |
| 980 | + buf_size = min(count, (sizeof(buf)-1)); | |
| 981 | + if (copy_from_user(buf, user_buf, buf_size)) | |
| 982 | + return -EFAULT; | |
| 983 | + buf[buf_size] = 0; | |
| 984 | + | |
| 985 | + err = strict_strtoul(buf, 0, &user_val); | |
| 986 | + if (err) | |
| 987 | + return -EINVAL; | |
| 988 | + if (user_val > 0xff) { | |
| 989 | + dev_err(&ab->i2c_client[0]->dev, | |
| 990 | + "debugfs error input > 0xff\n"); | |
| 991 | + return -EINVAL; | |
| 992 | + } | |
| 993 | + err = mask_and_set_register_interruptible( | |
| 994 | + ab, (u8)ab->debug_bank, | |
| 995 | + (u8)ab->debug_address, 0xFF, (u8)user_val); | |
| 996 | + if (err) | |
| 997 | + return -EINVAL; | |
| 998 | + | |
| 999 | + get_register_interruptible(ab, (u8)ab->debug_bank, | |
| 1000 | + (u8)ab->debug_address, ®value); | |
| 1001 | + if (err) | |
| 1002 | + return -EINVAL; | |
| 1003 | + | |
| 1004 | + return buf_size; | |
| 1005 | +} | |
| 1006 | + | |
| 1007 | +static const struct file_operations ab3550_bank_fops = { | |
| 1008 | + .open = ab3550_bank_open, | |
| 1009 | + .write = ab3550_bank_write, | |
| 1010 | + .read = seq_read, | |
| 1011 | + .llseek = seq_lseek, | |
| 1012 | + .release = single_release, | |
| 1013 | + .owner = THIS_MODULE, | |
| 1014 | +}; | |
| 1015 | + | |
| 1016 | +static const struct file_operations ab3550_address_fops = { | |
| 1017 | + .open = ab3550_address_open, | |
| 1018 | + .write = ab3550_address_write, | |
| 1019 | + .read = seq_read, | |
| 1020 | + .llseek = seq_lseek, | |
| 1021 | + .release = single_release, | |
| 1022 | + .owner = THIS_MODULE, | |
| 1023 | +}; | |
| 1024 | + | |
| 1025 | +static const struct file_operations ab3550_val_fops = { | |
| 1026 | + .open = ab3550_val_open, | |
| 1027 | + .write = ab3550_val_write, | |
| 1028 | + .read = seq_read, | |
| 1029 | + .llseek = seq_lseek, | |
| 1030 | + .release = single_release, | |
| 1031 | + .owner = THIS_MODULE, | |
| 1032 | +}; | |
| 1033 | + | |
| 1034 | +static struct dentry *ab3550_dir; | |
| 1035 | +static struct dentry *ab3550_reg_file; | |
| 1036 | +static struct dentry *ab3550_bank_file; | |
| 1037 | +static struct dentry *ab3550_address_file; | |
| 1038 | +static struct dentry *ab3550_val_file; | |
| 1039 | + | |
| 1040 | +static inline void ab3550_setup_debugfs(struct ab3550 *ab) | |
| 1041 | +{ | |
| 1042 | + ab->debug_bank = 0; | |
| 1043 | + ab->debug_address = 0x00; | |
| 1044 | + | |
| 1045 | + ab3550_dir = debugfs_create_dir(AB3550_NAME_STRING, NULL); | |
| 1046 | + if (!ab3550_dir) | |
| 1047 | + goto exit_no_debugfs; | |
| 1048 | + | |
| 1049 | + ab3550_reg_file = debugfs_create_file("all-registers", | |
| 1050 | + S_IRUGO, ab3550_dir, ab, &ab3550_registers_fops); | |
| 1051 | + if (!ab3550_reg_file) | |
| 1052 | + goto exit_destroy_dir; | |
| 1053 | + | |
| 1054 | + ab3550_bank_file = debugfs_create_file("register-bank", | |
| 1055 | + (S_IRUGO | S_IWUGO), ab3550_dir, ab, &ab3550_bank_fops); | |
| 1056 | + if (!ab3550_bank_file) | |
| 1057 | + goto exit_destroy_reg; | |
| 1058 | + | |
| 1059 | + ab3550_address_file = debugfs_create_file("register-address", | |
| 1060 | + (S_IRUGO | S_IWUGO), ab3550_dir, ab, &ab3550_address_fops); | |
| 1061 | + if (!ab3550_address_file) | |
| 1062 | + goto exit_destroy_bank; | |
| 1063 | + | |
| 1064 | + ab3550_val_file = debugfs_create_file("register-value", | |
| 1065 | + (S_IRUGO | S_IWUGO), ab3550_dir, ab, &ab3550_val_fops); | |
| 1066 | + if (!ab3550_val_file) | |
| 1067 | + goto exit_destroy_address; | |
| 1068 | + | |
| 1069 | + return; | |
| 1070 | + | |
| 1071 | +exit_destroy_address: | |
| 1072 | + debugfs_remove(ab3550_address_file); | |
| 1073 | +exit_destroy_bank: | |
| 1074 | + debugfs_remove(ab3550_bank_file); | |
| 1075 | +exit_destroy_reg: | |
| 1076 | + debugfs_remove(ab3550_reg_file); | |
| 1077 | +exit_destroy_dir: | |
| 1078 | + debugfs_remove(ab3550_dir); | |
| 1079 | +exit_no_debugfs: | |
| 1080 | + dev_err(&ab->i2c_client[0]->dev, "failed to create debugfs entries.\n"); | |
| 1081 | + return; | |
| 1082 | +} | |
| 1083 | + | |
| 1084 | +static inline void ab3550_remove_debugfs(void) | |
| 1085 | +{ | |
| 1086 | + debugfs_remove(ab3550_val_file); | |
| 1087 | + debugfs_remove(ab3550_address_file); | |
| 1088 | + debugfs_remove(ab3550_bank_file); | |
| 1089 | + debugfs_remove(ab3550_reg_file); | |
| 1090 | + debugfs_remove(ab3550_dir); | |
| 1091 | +} | |
| 1092 | + | |
| 1093 | +#else /* !CONFIG_DEBUG_FS */ | |
| 1094 | +static inline void ab3550_setup_debugfs(struct ab3550 *ab) | |
| 1095 | +{ | |
| 1096 | +} | |
| 1097 | +static inline void ab3550_remove_debugfs(void) | |
| 1098 | +{ | |
| 1099 | +} | |
| 1100 | +#endif | |
| 1101 | + | |
| 1102 | +/* | |
| 1103 | + * Basic set-up, datastructure creation/destruction and I2C interface. | |
| 1104 | + * This sets up a default config in the AB3550 chip so that it | |
| 1105 | + * will work as expected. | |
| 1106 | + */ | |
| 1107 | +static int __init ab3550_setup(struct ab3550 *ab) | |
| 1108 | +{ | |
| 1109 | + int err = 0; | |
| 1110 | + int i; | |
| 1111 | + struct ab3550_platform_data *plf_data; | |
| 1112 | + struct abx500_init_settings *settings; | |
| 1113 | + | |
| 1114 | + plf_data = ab->i2c_client[0]->dev.platform_data; | |
| 1115 | + settings = plf_data->init_settings; | |
| 1116 | + | |
| 1117 | + for (i = 0; i < plf_data->init_settings_sz; i++) { | |
| 1118 | + err = mask_and_set_register_interruptible(ab, | |
| 1119 | + settings[i].bank, | |
| 1120 | + settings[i].reg, | |
| 1121 | + 0xFF, settings[i].setting); | |
| 1122 | + if (err) | |
| 1123 | + goto exit_no_setup; | |
| 1124 | + | |
| 1125 | + /* If event mask register update the event mask in ab3550 */ | |
| 1126 | + if ((settings[i].bank == 0) && | |
| 1127 | + (AB3550_IMR1 <= settings[i].reg) && | |
| 1128 | + (settings[i].reg <= AB3550_IMR5)) { | |
| 1129 | + ab->event_mask[settings[i].reg - AB3550_IMR1] = | |
| 1130 | + settings[i].setting; | |
| 1131 | + } | |
| 1132 | + } | |
| 1133 | +exit_no_setup: | |
| 1134 | + return err; | |
| 1135 | +} | |
| 1136 | + | |
| 1137 | +static void ab3550_mask_work(struct work_struct *work) | |
| 1138 | +{ | |
| 1139 | + struct ab3550 *ab = container_of(work, struct ab3550, mask_work); | |
| 1140 | + int i; | |
| 1141 | + unsigned long flags; | |
| 1142 | + u8 mask[AB3550_NUM_EVENT_REG]; | |
| 1143 | + | |
| 1144 | + spin_lock_irqsave(&ab->event_lock, flags); | |
| 1145 | + for (i = 0; i < AB3550_NUM_EVENT_REG; i++) | |
| 1146 | + mask[i] = ab->event_mask[i]; | |
| 1147 | + spin_unlock_irqrestore(&ab->event_lock, flags); | |
| 1148 | + | |
| 1149 | + for (i = 0; i < AB3550_NUM_EVENT_REG; i++) { | |
| 1150 | + int err; | |
| 1151 | + | |
| 1152 | + err = mask_and_set_register_interruptible(ab, 0, | |
| 1153 | + (AB3550_IMR1 + i), ~0, mask[i]); | |
| 1154 | + if (err) | |
| 1155 | + dev_err(&ab->i2c_client[0]->dev, | |
| 1156 | + "ab3550_mask_work failed 0x%x,0x%x\n", | |
| 1157 | + (AB3550_IMR1 + i), mask[i]); | |
| 1158 | + } | |
| 1159 | +} | |
| 1160 | + | |
| 1161 | +static void ab3550_mask(unsigned int irq) | |
| 1162 | +{ | |
| 1163 | + unsigned long flags; | |
| 1164 | + struct ab3550 *ab; | |
| 1165 | + struct ab3550_platform_data *plf_data; | |
| 1166 | + | |
| 1167 | + ab = get_irq_chip_data(irq); | |
| 1168 | + plf_data = ab->i2c_client[0]->dev.platform_data; | |
| 1169 | + irq -= plf_data->irq.base; | |
| 1170 | + | |
| 1171 | + spin_lock_irqsave(&ab->event_lock, flags); | |
| 1172 | + ab->event_mask[irq / 8] |= BIT(irq % 8); | |
| 1173 | + spin_unlock_irqrestore(&ab->event_lock, flags); | |
| 1174 | + | |
| 1175 | + schedule_work(&ab->mask_work); | |
| 1176 | +} | |
| 1177 | + | |
| 1178 | +static void ab3550_unmask(unsigned int irq) | |
| 1179 | +{ | |
| 1180 | + unsigned long flags; | |
| 1181 | + struct ab3550 *ab; | |
| 1182 | + struct ab3550_platform_data *plf_data; | |
| 1183 | + | |
| 1184 | + ab = get_irq_chip_data(irq); | |
| 1185 | + plf_data = ab->i2c_client[0]->dev.platform_data; | |
| 1186 | + irq -= plf_data->irq.base; | |
| 1187 | + | |
| 1188 | + spin_lock_irqsave(&ab->event_lock, flags); | |
| 1189 | + ab->event_mask[irq / 8] &= ~BIT(irq % 8); | |
| 1190 | + spin_unlock_irqrestore(&ab->event_lock, flags); | |
| 1191 | + | |
| 1192 | + schedule_work(&ab->mask_work); | |
| 1193 | +} | |
| 1194 | + | |
| 1195 | +static void noop(unsigned int irq) | |
| 1196 | +{ | |
| 1197 | +} | |
| 1198 | + | |
| 1199 | +static struct irq_chip ab3550_irq_chip = { | |
| 1200 | + .name = "ab3550-core", /* Keep the same name as the request */ | |
| 1201 | + .startup = NULL, /* defaults to enable */ | |
| 1202 | + .shutdown = NULL, /* defaults to disable */ | |
| 1203 | + .enable = NULL, /* defaults to unmask */ | |
| 1204 | + .disable = ab3550_mask, /* No default to mask in chip.c */ | |
| 1205 | + .ack = noop, | |
| 1206 | + .mask = ab3550_mask, | |
| 1207 | + .unmask = ab3550_unmask, | |
| 1208 | + .end = NULL, | |
| 1209 | +}; | |
| 1210 | + | |
| 1211 | +struct ab_family_id { | |
| 1212 | + u8 id; | |
| 1213 | + char *name; | |
| 1214 | +}; | |
| 1215 | + | |
| 1216 | +static const struct ab_family_id ids[] __initdata = { | |
| 1217 | + /* AB3550 */ | |
| 1218 | + { | |
| 1219 | + .id = AB3550_P1A, | |
| 1220 | + .name = "P1A" | |
| 1221 | + }, | |
| 1222 | + /* Terminator */ | |
| 1223 | + { | |
| 1224 | + .id = 0x00, | |
| 1225 | + } | |
| 1226 | +}; | |
| 1227 | + | |
| 1228 | +static int __init ab3550_probe(struct i2c_client *client, | |
| 1229 | + const struct i2c_device_id *id) | |
| 1230 | +{ | |
| 1231 | + struct ab3550 *ab; | |
| 1232 | + struct ab3550_platform_data *ab3550_plf_data = | |
| 1233 | + client->dev.platform_data; | |
| 1234 | + int err; | |
| 1235 | + int i; | |
| 1236 | + int num_i2c_clients = 0; | |
| 1237 | + | |
| 1238 | + ab = kzalloc(sizeof(struct ab3550), GFP_KERNEL); | |
| 1239 | + if (!ab) { | |
| 1240 | + dev_err(&client->dev, | |
| 1241 | + "could not allocate " AB3550_NAME_STRING " device\n"); | |
| 1242 | + return -ENOMEM; | |
| 1243 | + } | |
| 1244 | + | |
| 1245 | + /* Initialize data structure */ | |
| 1246 | + mutex_init(&ab->access_mutex); | |
| 1247 | + spin_lock_init(&ab->event_lock); | |
| 1248 | + ab->i2c_client[0] = client; | |
| 1249 | + | |
| 1250 | + i2c_set_clientdata(client, ab); | |
| 1251 | + | |
| 1252 | + /* Read chip ID register */ | |
| 1253 | + err = get_register_interruptible(ab, 0, AB3550_CID_REG, &ab->chip_id); | |
| 1254 | + if (err) { | |
| 1255 | + dev_err(&client->dev, "could not communicate with the analog " | |
| 1256 | + "baseband chip\n"); | |
| 1257 | + goto exit_no_detect; | |
| 1258 | + } | |
| 1259 | + | |
| 1260 | + for (i = 0; ids[i].id != 0x0; i++) { | |
| 1261 | + if (ids[i].id == ab->chip_id) { | |
| 1262 | + snprintf(&ab->chip_name[0], sizeof(ab->chip_name) - 1, | |
| 1263 | + AB3550_ID_FORMAT_STRING, ids[i].name); | |
| 1264 | + break; | |
| 1265 | + } | |
| 1266 | + } | |
| 1267 | + | |
| 1268 | + if (ids[i].id == 0x0) { | |
| 1269 | + dev_err(&client->dev, "unknown analog baseband chip id: 0x%x\n", | |
| 1270 | + ab->chip_id); | |
| 1271 | + dev_err(&client->dev, "driver not started!\n"); | |
| 1272 | + goto exit_no_detect; | |
| 1273 | + } | |
| 1274 | + | |
| 1275 | + dev_info(&client->dev, "detected AB chip: %s\n", &ab->chip_name[0]); | |
| 1276 | + | |
| 1277 | + /* Attach other dummy I2C clients. */ | |
| 1278 | + while (++num_i2c_clients < AB3550_NUM_BANKS) { | |
| 1279 | + ab->i2c_client[num_i2c_clients] = | |
| 1280 | + i2c_new_dummy(client->adapter, | |
| 1281 | + (client->addr + num_i2c_clients)); | |
| 1282 | + if (!ab->i2c_client[num_i2c_clients]) { | |
| 1283 | + err = -ENOMEM; | |
| 1284 | + goto exit_no_dummy_client; | |
| 1285 | + } | |
| 1286 | + strlcpy(ab->i2c_client[num_i2c_clients]->name, id->name, | |
| 1287 | + sizeof(ab->i2c_client[num_i2c_clients]->name)); | |
| 1288 | + } | |
| 1289 | + | |
| 1290 | + err = ab3550_setup(ab); | |
| 1291 | + if (err) | |
| 1292 | + goto exit_no_setup; | |
| 1293 | + | |
| 1294 | + INIT_WORK(&ab->mask_work, ab3550_mask_work); | |
| 1295 | + | |
| 1296 | + for (i = 0; i < ab3550_plf_data->irq.count; i++) { | |
| 1297 | + unsigned int irq; | |
| 1298 | + | |
| 1299 | + irq = ab3550_plf_data->irq.base + i; | |
| 1300 | + set_irq_chip_data(irq, ab); | |
| 1301 | + set_irq_chip_and_handler(irq, &ab3550_irq_chip, | |
| 1302 | + handle_simple_irq); | |
| 1303 | + set_irq_nested_thread(irq, 1); | |
| 1304 | +#ifdef CONFIG_ARM | |
| 1305 | + set_irq_flags(irq, IRQF_VALID); | |
| 1306 | +#else | |
| 1307 | + set_irq_noprobe(irq); | |
| 1308 | +#endif | |
| 1309 | + } | |
| 1310 | + | |
| 1311 | + err = request_threaded_irq(client->irq, NULL, ab3550_irq_handler, | |
| 1312 | + IRQF_ONESHOT, "ab3550-core", ab); | |
| 1313 | + /* This real unpredictable IRQ is of course sampled for entropy */ | |
| 1314 | + rand_initialize_irq(client->irq); | |
| 1315 | + | |
| 1316 | + if (err) | |
| 1317 | + goto exit_no_irq; | |
| 1318 | + | |
| 1319 | + err = abx500_register_ops(&client->dev, &ab3550_ops); | |
| 1320 | + if (err) | |
| 1321 | + goto exit_no_ops; | |
| 1322 | + | |
| 1323 | + /* Set up and register the platform devices. */ | |
| 1324 | + for (i = 0; i < AB3550_NUM_DEVICES; i++) { | |
| 1325 | + ab3550_devs[i].platform_data = ab3550_plf_data->dev_data[i]; | |
| 1326 | + ab3550_devs[i].data_size = ab3550_plf_data->dev_data_sz[i]; | |
| 1327 | + } | |
| 1328 | + | |
| 1329 | + err = mfd_add_devices(&client->dev, 0, ab3550_devs, | |
| 1330 | + ARRAY_SIZE(ab3550_devs), NULL, | |
| 1331 | + ab3550_plf_data->irq.base); | |
| 1332 | + | |
| 1333 | + ab3550_setup_debugfs(ab); | |
| 1334 | + | |
| 1335 | + return 0; | |
| 1336 | + | |
| 1337 | +exit_no_ops: | |
| 1338 | +exit_no_irq: | |
| 1339 | +exit_no_setup: | |
| 1340 | +exit_no_dummy_client: | |
| 1341 | + /* Unregister the dummy i2c clients. */ | |
| 1342 | + while (--num_i2c_clients) | |
| 1343 | + i2c_unregister_device(ab->i2c_client[num_i2c_clients]); | |
| 1344 | +exit_no_detect: | |
| 1345 | + kfree(ab); | |
| 1346 | + return err; | |
| 1347 | +} | |
| 1348 | + | |
| 1349 | +static int __exit ab3550_remove(struct i2c_client *client) | |
| 1350 | +{ | |
| 1351 | + struct ab3550 *ab = i2c_get_clientdata(client); | |
| 1352 | + int num_i2c_clients = AB3550_NUM_BANKS; | |
| 1353 | + | |
| 1354 | + mfd_remove_devices(&client->dev); | |
| 1355 | + ab3550_remove_debugfs(); | |
| 1356 | + | |
| 1357 | + while (--num_i2c_clients) | |
| 1358 | + i2c_unregister_device(ab->i2c_client[num_i2c_clients]); | |
| 1359 | + | |
| 1360 | + /* | |
| 1361 | + * At this point, all subscribers should have unregistered | |
| 1362 | + * their notifiers so deactivate IRQ | |
| 1363 | + */ | |
| 1364 | + free_irq(client->irq, ab); | |
| 1365 | + i2c_set_clientdata(client, NULL); | |
| 1366 | + kfree(ab); | |
| 1367 | + return 0; | |
| 1368 | +} | |
| 1369 | + | |
| 1370 | +static const struct i2c_device_id ab3550_id[] = { | |
| 1371 | + {AB3550_NAME_STRING, 0}, | |
| 1372 | + {} | |
| 1373 | +}; | |
| 1374 | +MODULE_DEVICE_TABLE(i2c, ab3550_id); | |
| 1375 | + | |
| 1376 | +static struct i2c_driver ab3550_driver = { | |
| 1377 | + .driver = { | |
| 1378 | + .name = AB3550_NAME_STRING, | |
| 1379 | + .owner = THIS_MODULE, | |
| 1380 | + }, | |
| 1381 | + .id_table = ab3550_id, | |
| 1382 | + .probe = ab3550_probe, | |
| 1383 | + .remove = __exit_p(ab3550_remove), | |
| 1384 | +}; | |
| 1385 | + | |
| 1386 | +static int __init ab3550_i2c_init(void) | |
| 1387 | +{ | |
| 1388 | + return i2c_add_driver(&ab3550_driver); | |
| 1389 | +} | |
| 1390 | + | |
| 1391 | +static void __exit ab3550_i2c_exit(void) | |
| 1392 | +{ | |
| 1393 | + i2c_del_driver(&ab3550_driver); | |
| 1394 | +} | |
| 1395 | + | |
| 1396 | +subsys_initcall(ab3550_i2c_init); | |
| 1397 | +module_exit(ab3550_i2c_exit); | |
| 1398 | + | |
| 1399 | +MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>"); | |
| 1400 | +MODULE_DESCRIPTION("AB3550 core driver"); | |
| 1401 | +MODULE_LICENSE("GPL"); | |
| @@ -1,209 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright (C) 2009 ST-Ericsson | |
| 3 | − * | |
| 4 | − * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> | |
| 5 | − * | |
| 6 | − * This program is free software; you can redistribute it | |
| 7 | − * and/or modify it under the terms of the GNU General Public | |
| 8 | − * License version 2, as published by the Free Software Foundation. | |
| 9 | − * | |
| 10 | − * AB4500 is a companion power management chip used with U8500. | |
| 11 | − * On this platform, this is interfaced with SSP0 controller | |
| 12 | − * which is a ARM primecell pl022. | |
| 13 | − * | |
| 14 | − * At the moment the module just exports read/write features. | |
| 15 | − * Interrupt management to be added - TODO. | |
| 16 | − */ | |
| 17 | −#include <linux/kernel.h> | |
| 18 | −#include <linux/slab.h> | |
| 19 | −#include <linux/init.h> | |
| 20 | −#include <linux/module.h> | |
| 21 | −#include <linux/platform_device.h> | |
| 22 | −#include <linux/spi/spi.h> | |
| 23 | −#include <linux/mfd/ab4500.h> | |
| 24 | − | |
| 25 | −/* just required if probe fails, we need to | |
| 26 | − * unregister the device | |
| 27 | − */ | |
| 28 | −static struct spi_driver ab4500_driver; | |
| 29 | − | |
| 30 | −/* | |
| 31 | − * This funtion writes to any AB4500 registers using | |
| 32 | − * SPI protocol & before it writes it packs the data | |
| 33 | − * in the below 24 bit frame format | |
| 34 | − * | |
| 35 | − * *|------------------------------------| | |
| 36 | − * *| 23|22...18|17.......10|9|8|7......0| | |
| 37 | − * *| r/w bank adr data | | |
| 38 | − * * ------------------------------------ | |
| 39 | − * | |
| 40 | − * This function shouldn't be called from interrupt | |
| 41 | − * context | |
| 42 | − */ | |
| 43 | −int ab4500_write(struct ab4500 *ab4500, unsigned char block, | |
| 44 | − unsigned long addr, unsigned char data) | |
| 45 | −{ | |
| 46 | − struct spi_transfer xfer; | |
| 47 | − struct spi_message msg; | |
| 48 | − int err; | |
| 49 | − unsigned long spi_data = | |
| 50 | − block << 18 | addr << 10 | data; | |
| 51 | − | |
| 52 | − mutex_lock(&ab4500->lock); | |
| 53 | − ab4500->tx_buf[0] = spi_data; | |
| 54 | − ab4500->rx_buf[0] = 0; | |
| 55 | − | |
| 56 | − xfer.tx_buf = ab4500->tx_buf; | |
| 57 | − xfer.rx_buf = NULL; | |
| 58 | − xfer.len = sizeof(unsigned long); | |
| 59 | − | |
| 60 | − spi_message_init(&msg); | |
| 61 | − spi_message_add_tail(&xfer, &msg); | |
| 62 | − | |
| 63 | − err = spi_sync(ab4500->spi, &msg); | |
| 64 | − mutex_unlock(&ab4500->lock); | |
| 65 | − | |
| 66 | − return err; | |
| 67 | −} | |
| 68 | −EXPORT_SYMBOL(ab4500_write); | |
| 69 | − | |
| 70 | −int ab4500_read(struct ab4500 *ab4500, unsigned char block, | |
| 71 | − unsigned long addr) | |
| 72 | −{ | |
| 73 | − struct spi_transfer xfer; | |
| 74 | − struct spi_message msg; | |
| 75 | − unsigned long spi_data = | |
| 76 | − 1 << 23 | block << 18 | addr << 10; | |
| 77 | − | |
| 78 | − mutex_lock(&ab4500->lock); | |
| 79 | − ab4500->tx_buf[0] = spi_data; | |
| 80 | − ab4500->rx_buf[0] = 0; | |
| 81 | − | |
| 82 | − xfer.tx_buf = ab4500->tx_buf; | |
| 83 | − xfer.rx_buf = ab4500->rx_buf; | |
| 84 | − xfer.len = sizeof(unsigned long); | |
| 85 | − | |
| 86 | − spi_message_init(&msg); | |
| 87 | − spi_message_add_tail(&xfer, &msg); | |
| 88 | − | |
| 89 | − spi_sync(ab4500->spi, &msg); | |
| 90 | − mutex_unlock(&ab4500->lock); | |
| 91 | − | |
| 92 | − return ab4500->rx_buf[0]; | |
| 93 | −} | |
| 94 | −EXPORT_SYMBOL(ab4500_read); | |
| 95 | − | |
| 96 | −/* ref: ab3100 core */ | |
| 97 | −#define AB4500_DEVICE(devname, devid) \ | |
| 98 | −static struct platform_device ab4500_##devname##_device = { \ | |
| 99 | − .name = devid, \ | |
| 100 | − .id = -1, \ | |
| 101 | −} | |
| 102 | − | |
| 103 | −/* list of childern devices of ab4500 - all are | |
| 104 | − * not populated here - TODO | |
| 105 | − */ | |
| 106 | −AB4500_DEVICE(charger, "ab4500-charger"); | |
| 107 | −AB4500_DEVICE(audio, "ab4500-audio"); | |
| 108 | −AB4500_DEVICE(usb, "ab4500-usb"); | |
| 109 | −AB4500_DEVICE(tvout, "ab4500-tvout"); | |
| 110 | −AB4500_DEVICE(sim, "ab4500-sim"); | |
| 111 | −AB4500_DEVICE(gpadc, "ab4500-gpadc"); | |
| 112 | −AB4500_DEVICE(clkmgt, "ab4500-clkmgt"); | |
| 113 | −AB4500_DEVICE(misc, "ab4500-misc"); | |
| 114 | − | |
| 115 | −static struct platform_device *ab4500_platform_devs[] = { | |
| 116 | − &ab4500_charger_device, | |
| 117 | − &ab4500_audio_device, | |
| 118 | − &ab4500_usb_device, | |
| 119 | − &ab4500_tvout_device, | |
| 120 | − &ab4500_sim_device, | |
| 121 | − &ab4500_gpadc_device, | |
| 122 | − &ab4500_clkmgt_device, | |
| 123 | − &ab4500_misc_device, | |
| 124 | −}; | |
| 125 | − | |
| 126 | −static int __init ab4500_probe(struct spi_device *spi) | |
| 127 | −{ | |
| 128 | − struct ab4500 *ab4500; | |
| 129 | − unsigned char revision; | |
| 130 | − int err = 0; | |
| 131 | − int i; | |
| 132 | − | |
| 133 | − ab4500 = kzalloc(sizeof *ab4500, GFP_KERNEL); | |
| 134 | − if (!ab4500) { | |
| 135 | − dev_err(&spi->dev, "could not allocate AB4500\n"); | |
| 136 | − err = -ENOMEM; | |
| 137 | − goto not_detect; | |
| 138 | − } | |
| 139 | − | |
| 140 | − ab4500->spi = spi; | |
| 141 | − spi_set_drvdata(spi, ab4500); | |
| 142 | − | |
| 143 | − mutex_init(&ab4500->lock); | |
| 144 | − | |
| 145 | − /* read the revision register */ | |
| 146 | − revision = ab4500_read(ab4500, AB4500_MISC, AB4500_REV_REG); | |
| 147 | − | |
| 148 | − /* revision id 0x0 is for early drop, 0x10 is for cut1.0 */ | |
| 149 | − if (revision == 0x0 || revision == 0x10) | |
| 150 | − dev_info(&spi->dev, "Detected chip: %s, revision = %x\n", | |
| 151 | − ab4500_driver.driver.name, revision); | |
| 152 | − else { | |
| 153 | − dev_err(&spi->dev, "unknown chip: 0x%x\n", revision); | |
| 154 | − goto not_detect; | |
| 155 | − } | |
| 156 | − | |
| 157 | − for (i = 0; i < ARRAY_SIZE(ab4500_platform_devs); i++) { | |
| 158 | − ab4500_platform_devs[i]->dev.parent = | |
| 159 | − &spi->dev; | |
| 160 | − platform_set_drvdata(ab4500_platform_devs[i], ab4500); | |
| 161 | − } | |
| 162 | − | |
| 163 | − /* register the ab4500 platform devices */ | |
| 164 | − platform_add_devices(ab4500_platform_devs, | |
| 165 | − ARRAY_SIZE(ab4500_platform_devs)); | |
| 166 | − | |
| 167 | − return err; | |
| 168 | − | |
| 169 | − not_detect: | |
| 170 | − spi_unregister_driver(&ab4500_driver); | |
| 171 | − kfree(ab4500); | |
| 172 | − return err; | |
| 173 | −} | |
| 174 | − | |
| 175 | −static int __devexit ab4500_remove(struct spi_device *spi) | |
| 176 | −{ | |
| 177 | − struct ab4500 *ab4500 = | |
| 178 | − spi_get_drvdata(spi); | |
| 179 | − | |
| 180 | − kfree(ab4500); | |
| 181 | − | |
| 182 | − return 0; | |
| 183 | −} | |
| 184 | − | |
| 185 | −static struct spi_driver ab4500_driver = { | |
| 186 | − .driver = { | |
| 187 | − .name = "ab4500", | |
| 188 | − .owner = THIS_MODULE, | |
| 189 | − }, | |
| 190 | − .probe = ab4500_probe, | |
| 191 | − .remove = __devexit_p(ab4500_remove) | |
| 192 | −}; | |
| 193 | − | |
| 194 | −static int __devinit ab4500_init(void) | |
| 195 | −{ | |
| 196 | − return spi_register_driver(&ab4500_driver); | |
| 197 | −} | |
| 198 | − | |
| 199 | −static void __exit ab4500_exit(void) | |
| 200 | −{ | |
| 201 | − spi_unregister_driver(&ab4500_driver); | |
| 202 | −} | |
| 203 | − | |
| 204 | −subsys_initcall(ab4500_init); | |
| 205 | −module_exit(ab4500_exit); | |
| 206 | − | |
| 207 | −MODULE_AUTHOR("Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com"); | |
| 208 | −MODULE_DESCRIPTION("AB4500 core driver"); | |
| 209 | −MODULE_LICENSE("GPL"); | |
| @@ -0,0 +1,444 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | + * | |
| 4 | + * License Terms: GNU General Public License v2 | |
| 5 | + * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
| 6 | + * Author: Rabin Vincent <rabin.vincent@stericsson.com> | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#include <linux/kernel.h> | |
| 10 | +#include <linux/slab.h> | |
| 11 | +#include <linux/init.h> | |
| 12 | +#include <linux/irq.h> | |
| 13 | +#include <linux/delay.h> | |
| 14 | +#include <linux/interrupt.h> | |
| 15 | +#include <linux/module.h> | |
| 16 | +#include <linux/platform_device.h> | |
| 17 | +#include <linux/mfd/core.h> | |
| 18 | +#include <linux/mfd/ab8500.h> | |
| 19 | + | |
| 20 | +/* | |
| 21 | + * Interrupt register offsets | |
| 22 | + * Bank : 0x0E | |
| 23 | + */ | |
| 24 | +#define AB8500_IT_SOURCE1_REG 0x0E00 | |
| 25 | +#define AB8500_IT_SOURCE2_REG 0x0E01 | |
| 26 | +#define AB8500_IT_SOURCE3_REG 0x0E02 | |
| 27 | +#define AB8500_IT_SOURCE4_REG 0x0E03 | |
| 28 | +#define AB8500_IT_SOURCE5_REG 0x0E04 | |
| 29 | +#define AB8500_IT_SOURCE6_REG 0x0E05 | |
| 30 | +#define AB8500_IT_SOURCE7_REG 0x0E06 | |
| 31 | +#define AB8500_IT_SOURCE8_REG 0x0E07 | |
| 32 | +#define AB8500_IT_SOURCE19_REG 0x0E12 | |
| 33 | +#define AB8500_IT_SOURCE20_REG 0x0E13 | |
| 34 | +#define AB8500_IT_SOURCE21_REG 0x0E14 | |
| 35 | +#define AB8500_IT_SOURCE22_REG 0x0E15 | |
| 36 | +#define AB8500_IT_SOURCE23_REG 0x0E16 | |
| 37 | +#define AB8500_IT_SOURCE24_REG 0x0E17 | |
| 38 | + | |
| 39 | +/* | |
| 40 | + * latch registers | |
| 41 | + */ | |
| 42 | +#define AB8500_IT_LATCH1_REG 0x0E20 | |
| 43 | +#define AB8500_IT_LATCH2_REG 0x0E21 | |
| 44 | +#define AB8500_IT_LATCH3_REG 0x0E22 | |
| 45 | +#define AB8500_IT_LATCH4_REG 0x0E23 | |
| 46 | +#define AB8500_IT_LATCH5_REG 0x0E24 | |
| 47 | +#define AB8500_IT_LATCH6_REG 0x0E25 | |
| 48 | +#define AB8500_IT_LATCH7_REG 0x0E26 | |
| 49 | +#define AB8500_IT_LATCH8_REG 0x0E27 | |
| 50 | +#define AB8500_IT_LATCH9_REG 0x0E28 | |
| 51 | +#define AB8500_IT_LATCH10_REG 0x0E29 | |
| 52 | +#define AB8500_IT_LATCH19_REG 0x0E32 | |
| 53 | +#define AB8500_IT_LATCH20_REG 0x0E33 | |
| 54 | +#define AB8500_IT_LATCH21_REG 0x0E34 | |
| 55 | +#define AB8500_IT_LATCH22_REG 0x0E35 | |
| 56 | +#define AB8500_IT_LATCH23_REG 0x0E36 | |
| 57 | +#define AB8500_IT_LATCH24_REG 0x0E37 | |
| 58 | + | |
| 59 | +/* | |
| 60 | + * mask registers | |
| 61 | + */ | |
| 62 | + | |
| 63 | +#define AB8500_IT_MASK1_REG 0x0E40 | |
| 64 | +#define AB8500_IT_MASK2_REG 0x0E41 | |
| 65 | +#define AB8500_IT_MASK3_REG 0x0E42 | |
| 66 | +#define AB8500_IT_MASK4_REG 0x0E43 | |
| 67 | +#define AB8500_IT_MASK5_REG 0x0E44 | |
| 68 | +#define AB8500_IT_MASK6_REG 0x0E45 | |
| 69 | +#define AB8500_IT_MASK7_REG 0x0E46 | |
| 70 | +#define AB8500_IT_MASK8_REG 0x0E47 | |
| 71 | +#define AB8500_IT_MASK9_REG 0x0E48 | |
| 72 | +#define AB8500_IT_MASK10_REG 0x0E49 | |
| 73 | +#define AB8500_IT_MASK11_REG 0x0E4A | |
| 74 | +#define AB8500_IT_MASK12_REG 0x0E4B | |
| 75 | +#define AB8500_IT_MASK13_REG 0x0E4C | |
| 76 | +#define AB8500_IT_MASK14_REG 0x0E4D | |
| 77 | +#define AB8500_IT_MASK15_REG 0x0E4E | |
| 78 | +#define AB8500_IT_MASK16_REG 0x0E4F | |
| 79 | +#define AB8500_IT_MASK17_REG 0x0E50 | |
| 80 | +#define AB8500_IT_MASK18_REG 0x0E51 | |
| 81 | +#define AB8500_IT_MASK19_REG 0x0E52 | |
| 82 | +#define AB8500_IT_MASK20_REG 0x0E53 | |
| 83 | +#define AB8500_IT_MASK21_REG 0x0E54 | |
| 84 | +#define AB8500_IT_MASK22_REG 0x0E55 | |
| 85 | +#define AB8500_IT_MASK23_REG 0x0E56 | |
| 86 | +#define AB8500_IT_MASK24_REG 0x0E57 | |
| 87 | + | |
| 88 | +#define AB8500_REV_REG 0x1080 | |
| 89 | + | |
| 90 | +/* | |
| 91 | + * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt | |
| 92 | + * numbers are indexed into this array with (num / 8). | |
| 93 | + * | |
| 94 | + * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at | |
| 95 | + * offset 0. | |
| 96 | + */ | |
| 97 | +static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = { | |
| 98 | + 0, 1, 2, 3, 4, 6, 7, 8, 9, 18, 19, 20, 21, | |
| 99 | +}; | |
| 100 | + | |
| 101 | +static int __ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data) | |
| 102 | +{ | |
| 103 | + int ret; | |
| 104 | + | |
| 105 | + dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data); | |
| 106 | + | |
| 107 | + ret = ab8500->write(ab8500, addr, data); | |
| 108 | + if (ret < 0) | |
| 109 | + dev_err(ab8500->dev, "failed to write reg %#x: %d\n", | |
| 110 | + addr, ret); | |
| 111 | + | |
| 112 | + return ret; | |
| 113 | +} | |
| 114 | + | |
| 115 | +/** | |
| 116 | + * ab8500_write() - write an AB8500 register | |
| 117 | + * @ab8500: device to write to | |
| 118 | + * @addr: address of the register | |
| 119 | + * @data: value to write | |
| 120 | + */ | |
| 121 | +int ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data) | |
| 122 | +{ | |
| 123 | + int ret; | |
| 124 | + | |
| 125 | + mutex_lock(&ab8500->lock); | |
| 126 | + ret = __ab8500_write(ab8500, addr, data); | |
| 127 | + mutex_unlock(&ab8500->lock); | |
| 128 | + | |
| 129 | + return ret; | |
| 130 | +} | |
| 131 | +EXPORT_SYMBOL_GPL(ab8500_write); | |
| 132 | + | |
| 133 | +static int __ab8500_read(struct ab8500 *ab8500, u16 addr) | |
| 134 | +{ | |
| 135 | + int ret; | |
| 136 | + | |
| 137 | + ret = ab8500->read(ab8500, addr); | |
| 138 | + if (ret < 0) | |
| 139 | + dev_err(ab8500->dev, "failed to read reg %#x: %d\n", | |
| 140 | + addr, ret); | |
| 141 | + | |
| 142 | + dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret); | |
| 143 | + | |
| 144 | + return ret; | |
| 145 | +} | |
| 146 | + | |
| 147 | +/** | |
| 148 | + * ab8500_read() - read an AB8500 register | |
| 149 | + * @ab8500: device to read from | |
| 150 | + * @addr: address of the register | |
| 151 | + */ | |
| 152 | +int ab8500_read(struct ab8500 *ab8500, u16 addr) | |
| 153 | +{ | |
| 154 | + int ret; | |
| 155 | + | |
| 156 | + mutex_lock(&ab8500->lock); | |
| 157 | + ret = __ab8500_read(ab8500, addr); | |
| 158 | + mutex_unlock(&ab8500->lock); | |
| 159 | + | |
| 160 | + return ret; | |
| 161 | +} | |
| 162 | +EXPORT_SYMBOL_GPL(ab8500_read); | |
| 163 | + | |
| 164 | +/** | |
| 165 | + * ab8500_set_bits() - set a bitfield in an AB8500 register | |
| 166 | + * @ab8500: device to read from | |
| 167 | + * @addr: address of the register | |
| 168 | + * @mask: mask of the bitfield to modify | |
| 169 | + * @data: value to set to the bitfield | |
| 170 | + */ | |
| 171 | +int ab8500_set_bits(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data) | |
| 172 | +{ | |
| 173 | + int ret; | |
| 174 | + | |
| 175 | + mutex_lock(&ab8500->lock); | |
| 176 | + | |
| 177 | + ret = __ab8500_read(ab8500, addr); | |
| 178 | + if (ret < 0) | |
| 179 | + goto out; | |
| 180 | + | |
| 181 | + ret &= ~mask; | |
| 182 | + ret |= data; | |
| 183 | + | |
| 184 | + ret = __ab8500_write(ab8500, addr, ret); | |
| 185 | + | |
| 186 | +out: | |
| 187 | + mutex_unlock(&ab8500->lock); | |
| 188 | + return ret; | |
| 189 | +} | |
| 190 | +EXPORT_SYMBOL_GPL(ab8500_set_bits); | |
| 191 | + | |
| 192 | +static void ab8500_irq_lock(unsigned int irq) | |
| 193 | +{ | |
| 194 | + struct ab8500 *ab8500 = get_irq_chip_data(irq); | |
| 195 | + | |
| 196 | + mutex_lock(&ab8500->irq_lock); | |
| 197 | +} | |
| 198 | + | |
| 199 | +static void ab8500_irq_sync_unlock(unsigned int irq) | |
| 200 | +{ | |
| 201 | + struct ab8500 *ab8500 = get_irq_chip_data(irq); | |
| 202 | + int i; | |
| 203 | + | |
| 204 | + for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) { | |
| 205 | + u8 old = ab8500->oldmask[i]; | |
| 206 | + u8 new = ab8500->mask[i]; | |
| 207 | + int reg; | |
| 208 | + | |
| 209 | + if (new == old) | |
| 210 | + continue; | |
| 211 | + | |
| 212 | + ab8500->oldmask[i] = new; | |
| 213 | + | |
| 214 | + reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i]; | |
| 215 | + ab8500_write(ab8500, reg, new); | |
| 216 | + } | |
| 217 | + | |
| 218 | + mutex_unlock(&ab8500->irq_lock); | |
| 219 | +} | |
| 220 | + | |
| 221 | +static void ab8500_irq_mask(unsigned int irq) | |
| 222 | +{ | |
| 223 | + struct ab8500 *ab8500 = get_irq_chip_data(irq); | |
| 224 | + int offset = irq - ab8500->irq_base; | |
| 225 | + int index = offset / 8; | |
| 226 | + int mask = 1 << (offset % 8); | |
| 227 | + | |
| 228 | + ab8500->mask[index] |= mask; | |
| 229 | +} | |
| 230 | + | |
| 231 | +static void ab8500_irq_unmask(unsigned int irq) | |
| 232 | +{ | |
| 233 | + struct ab8500 *ab8500 = get_irq_chip_data(irq); | |
| 234 | + int offset = irq - ab8500->irq_base; | |
| 235 | + int index = offset / 8; | |
| 236 | + int mask = 1 << (offset % 8); | |
| 237 | + | |
| 238 | + ab8500->mask[index] &= ~mask; | |
| 239 | +} | |
| 240 | + | |
| 241 | +static struct irq_chip ab8500_irq_chip = { | |
| 242 | + .name = "ab8500", | |
| 243 | + .bus_lock = ab8500_irq_lock, | |
| 244 | + .bus_sync_unlock = ab8500_irq_sync_unlock, | |
| 245 | + .mask = ab8500_irq_mask, | |
| 246 | + .unmask = ab8500_irq_unmask, | |
| 247 | +}; | |
| 248 | + | |
| 249 | +static irqreturn_t ab8500_irq(int irq, void *dev) | |
| 250 | +{ | |
| 251 | + struct ab8500 *ab8500 = dev; | |
| 252 | + int i; | |
| 253 | + | |
| 254 | + dev_vdbg(ab8500->dev, "interrupt\n"); | |
| 255 | + | |
| 256 | + for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) { | |
| 257 | + int regoffset = ab8500_irq_regoffset[i]; | |
| 258 | + int status; | |
| 259 | + | |
| 260 | + status = ab8500_read(ab8500, AB8500_IT_LATCH1_REG + regoffset); | |
| 261 | + if (status <= 0) | |
| 262 | + continue; | |
| 263 | + | |
| 264 | + do { | |
| 265 | + int bit = __ffs(status); | |
| 266 | + int line = i * 8 + bit; | |
| 267 | + | |
| 268 | + handle_nested_irq(ab8500->irq_base + line); | |
| 269 | + status &= ~(1 << bit); | |
| 270 | + } while (status); | |
| 271 | + } | |
| 272 | + | |
| 273 | + return IRQ_HANDLED; | |
| 274 | +} | |
| 275 | + | |
| 276 | +static int ab8500_irq_init(struct ab8500 *ab8500) | |
| 277 | +{ | |
| 278 | + int base = ab8500->irq_base; | |
| 279 | + int irq; | |
| 280 | + | |
| 281 | + for (irq = base; irq < base + AB8500_NR_IRQS; irq++) { | |
| 282 | + set_irq_chip_data(irq, ab8500); | |
| 283 | + set_irq_chip_and_handler(irq, &ab8500_irq_chip, | |
| 284 | + handle_simple_irq); | |
| 285 | + set_irq_nested_thread(irq, 1); | |
| 286 | +#ifdef CONFIG_ARM | |
| 287 | + set_irq_flags(irq, IRQF_VALID); | |
| 288 | +#else | |
| 289 | + set_irq_noprobe(irq); | |
| 290 | +#endif | |
| 291 | + } | |
| 292 | + | |
| 293 | + return 0; | |
| 294 | +} | |
| 295 | + | |
| 296 | +static void ab8500_irq_remove(struct ab8500 *ab8500) | |
| 297 | +{ | |
| 298 | + int base = ab8500->irq_base; | |
| 299 | + int irq; | |
| 300 | + | |
| 301 | + for (irq = base; irq < base + AB8500_NR_IRQS; irq++) { | |
| 302 | +#ifdef CONFIG_ARM | |
| 303 | + set_irq_flags(irq, 0); | |
| 304 | +#endif | |
| 305 | + set_irq_chip_and_handler(irq, NULL, NULL); | |
| 306 | + set_irq_chip_data(irq, NULL); | |
| 307 | + } | |
| 308 | +} | |
| 309 | + | |
| 310 | +static struct resource ab8500_gpadc_resources[] = { | |
| 311 | + { | |
| 312 | + .name = "HW_CONV_END", | |
| 313 | + .start = AB8500_INT_GP_HW_ADC_CONV_END, | |
| 314 | + .end = AB8500_INT_GP_HW_ADC_CONV_END, | |
| 315 | + .flags = IORESOURCE_IRQ, | |
| 316 | + }, | |
| 317 | + { | |
| 318 | + .name = "SW_CONV_END", | |
| 319 | + .start = AB8500_INT_GP_SW_ADC_CONV_END, | |
| 320 | + .end = AB8500_INT_GP_SW_ADC_CONV_END, | |
| 321 | + .flags = IORESOURCE_IRQ, | |
| 322 | + }, | |
| 323 | +}; | |
| 324 | + | |
| 325 | +static struct resource ab8500_rtc_resources[] = { | |
| 326 | + { | |
| 327 | + .name = "60S", | |
| 328 | + .start = AB8500_INT_RTC_60S, | |
| 329 | + .end = AB8500_INT_RTC_60S, | |
| 330 | + .flags = IORESOURCE_IRQ, | |
| 331 | + }, | |
| 332 | + { | |
| 333 | + .name = "ALARM", | |
| 334 | + .start = AB8500_INT_RTC_ALARM, | |
| 335 | + .end = AB8500_INT_RTC_ALARM, | |
| 336 | + .flags = IORESOURCE_IRQ, | |
| 337 | + }, | |
| 338 | +}; | |
| 339 | + | |
| 340 | +static struct mfd_cell ab8500_devs[] = { | |
| 341 | + { | |
| 342 | + .name = "ab8500-gpadc", | |
| 343 | + .num_resources = ARRAY_SIZE(ab8500_gpadc_resources), | |
| 344 | + .resources = ab8500_gpadc_resources, | |
| 345 | + }, | |
| 346 | + { | |
| 347 | + .name = "ab8500-rtc", | |
| 348 | + .num_resources = ARRAY_SIZE(ab8500_rtc_resources), | |
| 349 | + .resources = ab8500_rtc_resources, | |
| 350 | + }, | |
| 351 | + { .name = "ab8500-charger", }, | |
| 352 | + { .name = "ab8500-audio", }, | |
| 353 | + { .name = "ab8500-usb", }, | |
| 354 | + { .name = "ab8500-pwm", }, | |
| 355 | +}; | |
| 356 | + | |
| 357 | +int __devinit ab8500_init(struct ab8500 *ab8500) | |
| 358 | +{ | |
| 359 | + struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev); | |
| 360 | + int ret; | |
| 361 | + int i; | |
| 362 | + | |
| 363 | + if (plat) | |
| 364 | + ab8500->irq_base = plat->irq_base; | |
| 365 | + | |
| 366 | + mutex_init(&ab8500->lock); | |
| 367 | + mutex_init(&ab8500->irq_lock); | |
| 368 | + | |
| 369 | + ret = ab8500_read(ab8500, AB8500_REV_REG); | |
| 370 | + if (ret < 0) | |
| 371 | + return ret; | |
| 372 | + | |
| 373 | + /* | |
| 374 | + * 0x0 - Early Drop | |
| 375 | + * 0x10 - Cut 1.0 | |
| 376 | + * 0x11 - Cut 1.1 | |
| 377 | + */ | |
| 378 | + if (ret == 0x0 || ret == 0x10 || ret == 0x11) { | |
| 379 | + ab8500->revision = ret; | |
| 380 | + dev_info(ab8500->dev, "detected chip, revision: %#x\n", ret); | |
| 381 | + } else { | |
| 382 | + dev_err(ab8500->dev, "unknown chip, revision: %#x\n", ret); | |
| 383 | + return -EINVAL; | |
| 384 | + } | |
| 385 | + | |
| 386 | + if (plat && plat->init) | |
| 387 | + plat->init(ab8500); | |
| 388 | + | |
| 389 | + /* Clear and mask all interrupts */ | |
| 390 | + for (i = 0; i < 10; i++) { | |
| 391 | + ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i); | |
| 392 | + ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff); | |
| 393 | + } | |
| 394 | + | |
| 395 | + for (i = 18; i < 24; i++) { | |
| 396 | + ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i); | |
| 397 | + ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff); | |
| 398 | + } | |
| 399 | + | |
| 400 | + for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) | |
| 401 | + ab8500->mask[i] = ab8500->oldmask[i] = 0xff; | |
| 402 | + | |
| 403 | + if (ab8500->irq_base) { | |
| 404 | + ret = ab8500_irq_init(ab8500); | |
| 405 | + if (ret) | |
| 406 | + return ret; | |
| 407 | + | |
| 408 | + ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq, | |
| 409 | + IRQF_ONESHOT, "ab8500", ab8500); | |
| 410 | + if (ret) | |
| 411 | + goto out_removeirq; | |
| 412 | + } | |
| 413 | + | |
| 414 | + ret = mfd_add_devices(ab8500->dev, -1, ab8500_devs, | |
| 415 | + ARRAY_SIZE(ab8500_devs), NULL, | |
| 416 | + ab8500->irq_base); | |
| 417 | + if (ret) | |
| 418 | + goto out_freeirq; | |
| 419 | + | |
| 420 | + return ret; | |
| 421 | + | |
| 422 | +out_freeirq: | |
| 423 | + if (ab8500->irq_base) { | |
| 424 | + free_irq(ab8500->irq, ab8500); | |
| 425 | +out_removeirq: | |
| 426 | + ab8500_irq_remove(ab8500); | |
| 427 | + } | |
| 428 | + return ret; | |
| 429 | +} | |
| 430 | + | |
| 431 | +int __devexit ab8500_exit(struct ab8500 *ab8500) | |
| 432 | +{ | |
| 433 | + mfd_remove_devices(ab8500->dev); | |
| 434 | + if (ab8500->irq_base) { | |
| 435 | + free_irq(ab8500->irq, ab8500); | |
| 436 | + ab8500_irq_remove(ab8500); | |
| 437 | + } | |
| 438 | + | |
| 439 | + return 0; | |
| 440 | +} | |
| 441 | + | |
| 442 | +MODULE_AUTHOR("Srinidhi Kasagar, Rabin Vincent"); | |
| 443 | +MODULE_DESCRIPTION("AB8500 MFD core"); | |
| 444 | +MODULE_LICENSE("GPL v2"); | |
| @@ -0,0 +1,133 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | + * | |
| 4 | + * License Terms: GNU General Public License v2 | |
| 5 | + * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
| 6 | + */ | |
| 7 | + | |
| 8 | +#include <linux/kernel.h> | |
| 9 | +#include <linux/slab.h> | |
| 10 | +#include <linux/init.h> | |
| 11 | +#include <linux/module.h> | |
| 12 | +#include <linux/platform_device.h> | |
| 13 | +#include <linux/spi/spi.h> | |
| 14 | +#include <linux/mfd/ab8500.h> | |
| 15 | + | |
| 16 | +/* | |
| 17 | + * This funtion writes to any AB8500 registers using | |
| 18 | + * SPI protocol & before it writes it packs the data | |
| 19 | + * in the below 24 bit frame format | |
| 20 | + * | |
| 21 | + * *|------------------------------------| | |
| 22 | + * *| 23|22...18|17.......10|9|8|7......0| | |
| 23 | + * *| r/w bank adr data | | |
| 24 | + * * ------------------------------------ | |
| 25 | + * | |
| 26 | + * This function shouldn't be called from interrupt | |
| 27 | + * context | |
| 28 | + */ | |
| 29 | +static int ab8500_spi_write(struct ab8500 *ab8500, u16 addr, u8 data) | |
| 30 | +{ | |
| 31 | + struct spi_device *spi = container_of(ab8500->dev, struct spi_device, | |
| 32 | + dev); | |
| 33 | + unsigned long spi_data = addr << 10 | data; | |
| 34 | + struct spi_transfer xfer; | |
| 35 | + struct spi_message msg; | |
| 36 | + | |
| 37 | + ab8500->tx_buf[0] = spi_data; | |
| 38 | + ab8500->rx_buf[0] = 0; | |
| 39 | + | |
| 40 | + xfer.tx_buf = ab8500->tx_buf; | |
| 41 | + xfer.rx_buf = NULL; | |
| 42 | + xfer.len = sizeof(unsigned long); | |
| 43 | + | |
| 44 | + spi_message_init(&msg); | |
| 45 | + spi_message_add_tail(&xfer, &msg); | |
| 46 | + | |
| 47 | + return spi_sync(spi, &msg); | |
| 48 | +} | |
| 49 | + | |
| 50 | +static int ab8500_spi_read(struct ab8500 *ab8500, u16 addr) | |
| 51 | +{ | |
| 52 | + struct spi_device *spi = container_of(ab8500->dev, struct spi_device, | |
| 53 | + dev); | |
| 54 | + unsigned long spi_data = 1 << 23 | addr << 10; | |
| 55 | + struct spi_transfer xfer; | |
| 56 | + struct spi_message msg; | |
| 57 | + int ret; | |
| 58 | + | |
| 59 | + ab8500->tx_buf[0] = spi_data; | |
| 60 | + ab8500->rx_buf[0] = 0; | |
| 61 | + | |
| 62 | + xfer.tx_buf = ab8500->tx_buf; | |
| 63 | + xfer.rx_buf = ab8500->rx_buf; | |
| 64 | + xfer.len = sizeof(unsigned long); | |
| 65 | + | |
| 66 | + spi_message_init(&msg); | |
| 67 | + spi_message_add_tail(&xfer, &msg); | |
| 68 | + | |
| 69 | + ret = spi_sync(spi, &msg); | |
| 70 | + if (!ret) | |
| 71 | + ret = ab8500->rx_buf[0]; | |
| 72 | + | |
| 73 | + return ret; | |
| 74 | +} | |
| 75 | + | |
| 76 | +static int __devinit ab8500_spi_probe(struct spi_device *spi) | |
| 77 | +{ | |
| 78 | + struct ab8500 *ab8500; | |
| 79 | + int ret; | |
| 80 | + | |
| 81 | + ab8500 = kzalloc(sizeof *ab8500, GFP_KERNEL); | |
| 82 | + if (!ab8500) | |
| 83 | + return -ENOMEM; | |
| 84 | + | |
| 85 | + ab8500->dev = &spi->dev; | |
| 86 | + ab8500->irq = spi->irq; | |
| 87 | + | |
| 88 | + ab8500->read = ab8500_spi_read; | |
| 89 | + ab8500->write = ab8500_spi_write; | |
| 90 | + | |
| 91 | + spi_set_drvdata(spi, ab8500); | |
| 92 | + | |
| 93 | + ret = ab8500_init(ab8500); | |
| 94 | + if (ret) | |
| 95 | + kfree(ab8500); | |
| 96 | + | |
| 97 | + return ret; | |
| 98 | +} | |
| 99 | + | |
| 100 | +static int __devexit ab8500_spi_remove(struct spi_device *spi) | |
| 101 | +{ | |
| 102 | + struct ab8500 *ab8500 = spi_get_drvdata(spi); | |
| 103 | + | |
| 104 | + ab8500_exit(ab8500); | |
| 105 | + kfree(ab8500); | |
| 106 | + | |
| 107 | + return 0; | |
| 108 | +} | |
| 109 | + | |
| 110 | +static struct spi_driver ab8500_spi_driver = { | |
| 111 | + .driver = { | |
| 112 | + .name = "ab8500", | |
| 113 | + .owner = THIS_MODULE, | |
| 114 | + }, | |
| 115 | + .probe = ab8500_spi_probe, | |
| 116 | + .remove = __devexit_p(ab8500_spi_remove) | |
| 117 | +}; | |
| 118 | + | |
| 119 | +static int __init ab8500_spi_init(void) | |
| 120 | +{ | |
| 121 | + return spi_register_driver(&ab8500_spi_driver); | |
| 122 | +} | |
| 123 | +subsys_initcall(ab8500_spi_init); | |
| 124 | + | |
| 125 | +static void __exit ab8500_spi_exit(void) | |
| 126 | +{ | |
| 127 | + spi_unregister_driver(&ab8500_spi_driver); | |
| 128 | +} | |
| 129 | +module_exit(ab8500_spi_exit); | |
| 130 | + | |
| 131 | +MODULE_AUTHOR("Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com"); | |
| 132 | +MODULE_DESCRIPTION("AB8500 SPI"); | |
| 133 | +MODULE_LICENSE("GPL v2"); | |
| @@ -0,0 +1,157 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) 2007-2010 ST-Ericsson | |
| 3 | + * License terms: GNU General Public License (GPL) version 2 | |
| 4 | + * Register access functions for the ABX500 Mixed Signal IC family. | |
| 5 | + * Author: Mattias Wallin <mattias.wallin@stericsson.com> | |
| 6 | + */ | |
| 7 | + | |
| 8 | +#include <linux/list.h> | |
| 9 | +#include <linux/slab.h> | |
| 10 | +#include <linux/err.h> | |
| 11 | +#include <linux/mfd/abx500.h> | |
| 12 | + | |
| 13 | +static LIST_HEAD(abx500_list); | |
| 14 | + | |
| 15 | +struct abx500_device_entry { | |
| 16 | + struct list_head list; | |
| 17 | + struct abx500_ops ops; | |
| 18 | + struct device *dev; | |
| 19 | +}; | |
| 20 | + | |
| 21 | +static void lookup_ops(struct device *dev, struct abx500_ops **ops) | |
| 22 | +{ | |
| 23 | + struct abx500_device_entry *dev_entry; | |
| 24 | + | |
| 25 | + *ops = NULL; | |
| 26 | + list_for_each_entry(dev_entry, &abx500_list, list) { | |
| 27 | + if (dev_entry->dev == dev) { | |
| 28 | + *ops = &dev_entry->ops; | |
| 29 | + return; | |
| 30 | + } | |
| 31 | + } | |
| 32 | +} | |
| 33 | + | |
| 34 | +int abx500_register_ops(struct device *dev, struct abx500_ops *ops) | |
| 35 | +{ | |
| 36 | + struct abx500_device_entry *dev_entry; | |
| 37 | + | |
| 38 | + dev_entry = kzalloc(sizeof(struct abx500_device_entry), GFP_KERNEL); | |
| 39 | + if (IS_ERR(dev_entry)) { | |
| 40 | + dev_err(dev, "register_ops kzalloc failed"); | |
| 41 | + return -ENOMEM; | |
| 42 | + } | |
| 43 | + dev_entry->dev = dev; | |
| 44 | + memcpy(&dev_entry->ops, ops, sizeof(struct abx500_ops)); | |
| 45 | + | |
| 46 | + list_add_tail(&dev_entry->list, &abx500_list); | |
| 47 | + return 0; | |
| 48 | +} | |
| 49 | +EXPORT_SYMBOL(abx500_register_ops); | |
| 50 | + | |
| 51 | +void abx500_remove_ops(struct device *dev) | |
| 52 | +{ | |
| 53 | + struct abx500_device_entry *dev_entry, *tmp; | |
| 54 | + | |
| 55 | + list_for_each_entry_safe(dev_entry, tmp, &abx500_list, list) | |
| 56 | + { | |
| 57 | + if (dev_entry->dev == dev) { | |
| 58 | + list_del(&dev_entry->list); | |
| 59 | + kfree(dev_entry); | |
| 60 | + } | |
| 61 | + } | |
| 62 | +} | |
| 63 | +EXPORT_SYMBOL(abx500_remove_ops); | |
| 64 | + | |
| 65 | +int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, | |
| 66 | + u8 value) | |
| 67 | +{ | |
| 68 | + struct abx500_ops *ops; | |
| 69 | + | |
| 70 | + lookup_ops(dev->parent, &ops); | |
| 71 | + if ((ops != NULL) && (ops->set_register != NULL)) | |
| 72 | + return ops->set_register(dev, bank, reg, value); | |
| 73 | + else | |
| 74 | + return -ENOTSUPP; | |
| 75 | +} | |
| 76 | +EXPORT_SYMBOL(abx500_set_register_interruptible); | |
| 77 | + | |
| 78 | +int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, | |
| 79 | + u8 *value) | |
| 80 | +{ | |
| 81 | + struct abx500_ops *ops; | |
| 82 | + | |
| 83 | + lookup_ops(dev->parent, &ops); | |
| 84 | + if ((ops != NULL) && (ops->get_register != NULL)) | |
| 85 | + return ops->get_register(dev, bank, reg, value); | |
| 86 | + else | |
| 87 | + return -ENOTSUPP; | |
| 88 | +} | |
| 89 | +EXPORT_SYMBOL(abx500_get_register_interruptible); | |
| 90 | + | |
| 91 | +int abx500_get_register_page_interruptible(struct device *dev, u8 bank, | |
| 92 | + u8 first_reg, u8 *regvals, u8 numregs) | |
| 93 | +{ | |
| 94 | + struct abx500_ops *ops; | |
| 95 | + | |
| 96 | + lookup_ops(dev->parent, &ops); | |
| 97 | + if ((ops != NULL) && (ops->get_register_page != NULL)) | |
| 98 | + return ops->get_register_page(dev, bank, | |
| 99 | + first_reg, regvals, numregs); | |
| 100 | + else | |
| 101 | + return -ENOTSUPP; | |
| 102 | +} | |
| 103 | +EXPORT_SYMBOL(abx500_get_register_page_interruptible); | |
| 104 | + | |
| 105 | +int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank, | |
| 106 | + u8 reg, u8 bitmask, u8 bitvalues) | |
| 107 | +{ | |
| 108 | + struct abx500_ops *ops; | |
| 109 | + | |
| 110 | + lookup_ops(dev->parent, &ops); | |
| 111 | + if ((ops != NULL) && (ops->mask_and_set_register != NULL)) | |
| 112 | + return ops->mask_and_set_register(dev, bank, | |
| 113 | + reg, bitmask, bitvalues); | |
| 114 | + else | |
| 115 | + return -ENOTSUPP; | |
| 116 | +} | |
| 117 | +EXPORT_SYMBOL(abx500_mask_and_set_register_interruptible); | |
| 118 | + | |
| 119 | +int abx500_get_chip_id(struct device *dev) | |
| 120 | +{ | |
| 121 | + struct abx500_ops *ops; | |
| 122 | + | |
| 123 | + lookup_ops(dev->parent, &ops); | |
| 124 | + if ((ops != NULL) && (ops->get_chip_id != NULL)) | |
| 125 | + return ops->get_chip_id(dev); | |
| 126 | + else | |
| 127 | + return -ENOTSUPP; | |
| 128 | +} | |
| 129 | +EXPORT_SYMBOL(abx500_get_chip_id); | |
| 130 | + | |
| 131 | +int abx500_event_registers_startup_state_get(struct device *dev, u8 *event) | |
| 132 | +{ | |
| 133 | + struct abx500_ops *ops; | |
| 134 | + | |
| 135 | + lookup_ops(dev->parent, &ops); | |
| 136 | + if ((ops != NULL) && (ops->event_registers_startup_state_get != NULL)) | |
| 137 | + return ops->event_registers_startup_state_get(dev, event); | |
| 138 | + else | |
| 139 | + return -ENOTSUPP; | |
| 140 | +} | |
| 141 | +EXPORT_SYMBOL(abx500_event_registers_startup_state_get); | |
| 142 | + | |
| 143 | +int abx500_startup_irq_enabled(struct device *dev, unsigned int irq) | |
| 144 | +{ | |
| 145 | + struct abx500_ops *ops; | |
| 146 | + | |
| 147 | + lookup_ops(dev->parent, &ops); | |
| 148 | + if ((ops != NULL) && (ops->startup_irq_enabled != NULL)) | |
| 149 | + return ops->startup_irq_enabled(dev, irq); | |
| 150 | + else | |
| 151 | + return -ENOTSUPP; | |
| 152 | +} | |
| 153 | +EXPORT_SYMBOL(abx500_startup_irq_enabled); | |
| 154 | + | |
| 155 | +MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>"); | |
| 156 | +MODULE_DESCRIPTION("ABX500 core driver"); | |
| 157 | +MODULE_LICENSE("GPL"); | |
| @@ -544,6 +544,7 @@ static int __devexit da903x_remove(struct i2c_client *client) · 543 unmodified lines | ||
| 544 | 544 | struct da903x_chip *chip = i2c_get_clientdata(client); |
| 545 | 545 | |
| 546 | 546 | da903x_remove_subdevs(chip); |
| 547 | + i2c_set_clientdata(client, NULL); | |
| 547 | 548 | kfree(chip); |
| 548 | 549 | return 0; |
| 549 | 550 | } |
| @@ -0,0 +1,304 @@ | ||
| 1 | +/* | |
| 2 | + * Janz CMOD-IO MODULbus Carrier Board PCI Driver | |
| 3 | + * | |
| 4 | + * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu> | |
| 5 | + * | |
| 6 | + * Lots of inspiration and code was copied from drivers/mfd/sm501.c | |
| 7 | + * | |
| 8 | + * This program is free software; you can redistribute it and/or modify it | |
| 9 | + * under the terms of the GNU General Public License as published by the | |
| 10 | + * Free Software Foundation; either version 2 of the License, or (at your | |
| 11 | + * option) any later version. | |
| 12 | + */ | |
| 13 | + | |
| 14 | +#include <linux/kernel.h> | |
| 15 | +#include <linux/module.h> | |
| 16 | +#include <linux/init.h> | |
| 17 | +#include <linux/pci.h> | |
| 18 | +#include <linux/interrupt.h> | |
| 19 | +#include <linux/delay.h> | |
| 20 | +#include <linux/platform_device.h> | |
| 21 | +#include <linux/mfd/core.h> | |
| 22 | + | |
| 23 | +#include <linux/mfd/janz.h> | |
| 24 | + | |
| 25 | +#define DRV_NAME "janz-cmodio" | |
| 26 | + | |
| 27 | +/* Size of each MODULbus module in PCI BAR4 */ | |
| 28 | +#define CMODIO_MODULBUS_SIZE 0x200 | |
| 29 | + | |
| 30 | +/* Maximum number of MODULbus modules on a CMOD-IO carrier board */ | |
| 31 | +#define CMODIO_MAX_MODULES 4 | |
| 32 | + | |
| 33 | +/* Module Parameters */ | |
| 34 | +static unsigned int num_modules = CMODIO_MAX_MODULES; | |
| 35 | +static unsigned char *modules[CMODIO_MAX_MODULES] = { | |
| 36 | + "empty", "empty", "empty", "empty", | |
| 37 | +}; | |
| 38 | + | |
| 39 | +module_param_array(modules, charp, &num_modules, S_IRUGO); | |
| 40 | +MODULE_PARM_DESC(modules, "MODULbus modules attached to the carrier board"); | |
| 41 | + | |
| 42 | +/* Unique Device Id */ | |
| 43 | +static unsigned int cmodio_id; | |
| 44 | + | |
| 45 | +struct cmodio_device { | |
| 46 | + /* Parent PCI device */ | |
| 47 | + struct pci_dev *pdev; | |
| 48 | + | |
| 49 | + /* PLX control registers */ | |
| 50 | + struct janz_cmodio_onboard_regs __iomem *ctrl; | |
| 51 | + | |
| 52 | + /* hex switch position */ | |
| 53 | + u8 hex; | |
| 54 | + | |
| 55 | + /* mfd-core API */ | |
| 56 | + struct mfd_cell cells[CMODIO_MAX_MODULES]; | |
| 57 | + struct resource resources[3 * CMODIO_MAX_MODULES]; | |
| 58 | + struct janz_platform_data pdata[CMODIO_MAX_MODULES]; | |
| 59 | +}; | |
| 60 | + | |
| 61 | +/* | |
| 62 | + * Subdevices using the mfd-core API | |
| 63 | + */ | |
| 64 | + | |
| 65 | +static int __devinit cmodio_setup_subdevice(struct cmodio_device *priv, | |
| 66 | + char *name, unsigned int devno, | |
| 67 | + unsigned int modno) | |
| 68 | +{ | |
| 69 | + struct janz_platform_data *pdata; | |
| 70 | + struct mfd_cell *cell; | |
| 71 | + struct resource *res; | |
| 72 | + struct pci_dev *pci; | |
| 73 | + | |
| 74 | + pci = priv->pdev; | |
| 75 | + cell = &priv->cells[devno]; | |
| 76 | + res = &priv->resources[devno * 3]; | |
| 77 | + pdata = &priv->pdata[devno]; | |
| 78 | + | |
| 79 | + cell->name = name; | |
| 80 | + cell->resources = res; | |
| 81 | + cell->num_resources = 3; | |
| 82 | + | |
| 83 | + /* Setup the subdevice ID -- must be unique */ | |
| 84 | + cell->id = cmodio_id++; | |
| 85 | + | |
| 86 | + /* Add platform data */ | |
| 87 | + pdata->modno = modno; | |
| 88 | + cell->platform_data = pdata; | |
| 89 | + cell->data_size = sizeof(*pdata); | |
| 90 | + | |
| 91 | + /* MODULbus registers -- PCI BAR3 is big-endian MODULbus access */ | |
| 92 | + res->flags = IORESOURCE_MEM; | |
| 93 | + res->parent = &pci->resource[3]; | |
| 94 | + res->start = pci->resource[3].start + (CMODIO_MODULBUS_SIZE * modno); | |
| 95 | + res->end = res->start + CMODIO_MODULBUS_SIZE - 1; | |
| 96 | + res++; | |
| 97 | + | |
| 98 | + /* PLX Control Registers -- PCI BAR4 is interrupt and other registers */ | |
| 99 | + res->flags = IORESOURCE_MEM; | |
| 100 | + res->parent = &pci->resource[4]; | |
| 101 | + res->start = pci->resource[4].start; | |
| 102 | + res->end = pci->resource[4].end; | |
| 103 | + res++; | |
| 104 | + | |
| 105 | + /* | |
| 106 | + * IRQ | |
| 107 | + * | |
| 108 | + * The start and end fields are used as an offset to the irq_base | |
| 109 | + * parameter passed into the mfd_add_devices() function call. All | |
| 110 | + * devices share the same IRQ. | |
| 111 | + */ | |
| 112 | + res->flags = IORESOURCE_IRQ; | |
| 113 | + res->parent = NULL; | |
| 114 | + res->start = 0; | |
| 115 | + res->end = 0; | |
| 116 | + res++; | |
| 117 | + | |
| 118 | + return 0; | |
| 119 | +} | |
| 120 | + | |
| 121 | +/* Probe each submodule using kernel parameters */ | |
| 122 | +static int __devinit cmodio_probe_submodules(struct cmodio_device *priv) | |
| 123 | +{ | |
| 124 | + struct pci_dev *pdev = priv->pdev; | |
| 125 | + unsigned int num_probed = 0; | |
| 126 | + char *name; | |
| 127 | + int i; | |
| 128 | + | |
| 129 | + for (i = 0; i < num_modules; i++) { | |
| 130 | + name = modules[i]; | |
| 131 | + if (!strcmp(name, "") || !strcmp(name, "empty")) | |
| 132 | + continue; | |
| 133 | + | |
| 134 | + dev_dbg(&priv->pdev->dev, "MODULbus %d: name %s\n", i, name); | |
| 135 | + cmodio_setup_subdevice(priv, name, num_probed, i); | |
| 136 | + num_probed++; | |
| 137 | + } | |
| 138 | + | |
| 139 | + /* print an error message if no modules were probed */ | |
| 140 | + if (num_probed == 0) { | |
| 141 | + dev_err(&priv->pdev->dev, "no MODULbus modules specified, " | |
| 142 | + "please set the ``modules'' kernel " | |
| 143 | + "parameter according to your " | |
| 144 | + "hardware configuration\n"); | |
| 145 | + return -ENODEV; | |
| 146 | + } | |
| 147 | + | |
| 148 | + return mfd_add_devices(&pdev->dev, 0, priv->cells, | |
| 149 | + num_probed, NULL, pdev->irq); | |
| 150 | +} | |
| 151 | + | |
| 152 | +/* | |
| 153 | + * SYSFS Attributes | |
| 154 | + */ | |
| 155 | + | |
| 156 | +static ssize_t mbus_show(struct device *dev, struct device_attribute *attr, | |
| 157 | + char *buf) | |
| 158 | +{ | |
| 159 | + struct cmodio_device *priv = dev_get_drvdata(dev); | |
| 160 | + | |
| 161 | + return snprintf(buf, PAGE_SIZE, "%x\n", priv->hex); | |
| 162 | +} | |
| 163 | + | |
| 164 | +static DEVICE_ATTR(modulbus_number, S_IRUGO, mbus_show, NULL); | |
| 165 | + | |
| 166 | +static struct attribute *cmodio_sysfs_attrs[] = { | |
| 167 | + &dev_attr_modulbus_number.attr, | |
| 168 | + NULL, | |
| 169 | +}; | |
| 170 | + | |
| 171 | +static const struct attribute_group cmodio_sysfs_attr_group = { | |
| 172 | + .attrs = cmodio_sysfs_attrs, | |
| 173 | +}; | |
| 174 | + | |
| 175 | +/* | |
| 176 | + * PCI Driver | |
| 177 | + */ | |
| 178 | + | |
| 179 | +static int __devinit cmodio_pci_probe(struct pci_dev *dev, | |
| 180 | + const struct pci_device_id *id) | |
| 181 | +{ | |
| 182 | + struct cmodio_device *priv; | |
| 183 | + int ret; | |
| 184 | + | |
| 185 | + priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
| 186 | + if (!priv) { | |
| 187 | + dev_err(&dev->dev, "unable to allocate private data\n"); | |
| 188 | + ret = -ENOMEM; | |
| 189 | + goto out_return; | |
| 190 | + } | |
| 191 | + | |
| 192 | + pci_set_drvdata(dev, priv); | |
| 193 | + priv->pdev = dev; | |
| 194 | + | |
| 195 | + /* Hardware Initialization */ | |
| 196 | + ret = pci_enable_device(dev); | |
| 197 | + if (ret) { | |
| 198 | + dev_err(&dev->dev, "unable to enable device\n"); | |
| 199 | + goto out_free_priv; | |
| 200 | + } | |
| 201 | + | |
| 202 | + pci_set_master(dev); | |
| 203 | + ret = pci_request_regions(dev, DRV_NAME); | |
| 204 | + if (ret) { | |
| 205 | + dev_err(&dev->dev, "unable to request regions\n"); | |
| 206 | + goto out_pci_disable_device; | |
| 207 | + } | |
| 208 | + | |
| 209 | + /* Onboard configuration registers */ | |
| 210 | + priv->ctrl = pci_ioremap_bar(dev, 4); | |
| 211 | + if (!priv->ctrl) { | |
| 212 | + dev_err(&dev->dev, "unable to remap onboard regs\n"); | |
| 213 | + ret = -ENOMEM; | |
| 214 | + goto out_pci_release_regions; | |
| 215 | + } | |
| 216 | + | |
| 217 | + /* Read the hex switch on the carrier board */ | |
| 218 | + priv->hex = ioread8(&priv->ctrl->int_enable); | |
| 219 | + | |
| 220 | + /* Add the MODULbus number (hex switch value) to the device's sysfs */ | |
| 221 | + ret = sysfs_create_group(&dev->dev.kobj, &cmodio_sysfs_attr_group); | |
| 222 | + if (ret) { | |
| 223 | + dev_err(&dev->dev, "unable to create sysfs attributes\n"); | |
| 224 | + goto out_unmap_ctrl; | |
| 225 | + } | |
| 226 | + | |
| 227 | + /* | |
| 228 | + * Disable all interrupt lines, each submodule will enable its | |
| 229 | + * own interrupt line if needed | |
| 230 | + */ | |
| 231 | + iowrite8(0xf, &priv->ctrl->int_disable); | |
| 232 | + | |
| 233 | + /* Register drivers for all submodules */ | |
| 234 | + ret = cmodio_probe_submodules(priv); | |
| 235 | + if (ret) { | |
| 236 | + dev_err(&dev->dev, "unable to probe submodules\n"); | |
| 237 | + goto out_sysfs_remove_group; | |
| 238 | + } | |
| 239 | + | |
| 240 | + return 0; | |
| 241 | + | |
| 242 | +out_sysfs_remove_group: | |
| 243 | + sysfs_remove_group(&dev->dev.kobj, &cmodio_sysfs_attr_group); | |
| 244 | +out_unmap_ctrl: | |
| 245 | + iounmap(priv->ctrl); | |
| 246 | +out_pci_release_regions: | |
| 247 | + pci_release_regions(dev); | |
| 248 | +out_pci_disable_device: | |
| 249 | + pci_disable_device(dev); | |
| 250 | +out_free_priv: | |
| 251 | + kfree(priv); | |
| 252 | +out_return: | |
| 253 | + return ret; | |
| 254 | +} | |
| 255 | + | |
| 256 | +static void __devexit cmodio_pci_remove(struct pci_dev *dev) | |
| 257 | +{ | |
| 258 | + struct cmodio_device *priv = pci_get_drvdata(dev); | |
| 259 | + | |
| 260 | + mfd_remove_devices(&dev->dev); | |
| 261 | + sysfs_remove_group(&dev->dev.kobj, &cmodio_sysfs_attr_group); | |
| 262 | + iounmap(priv->ctrl); | |
| 263 | + pci_release_regions(dev); | |
| 264 | + pci_disable_device(dev); | |
| 265 | + kfree(priv); | |
| 266 | +} | |
| 267 | + | |
| 268 | +#define PCI_VENDOR_ID_JANZ 0x13c3 | |
| 269 | + | |
| 270 | +/* The list of devices that this module will support */ | |
| 271 | +static DEFINE_PCI_DEVICE_TABLE(cmodio_pci_ids) = { | |
| 272 | + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0101 }, | |
| 273 | + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0100 }, | |
| 274 | + { 0, } | |
| 275 | +}; | |
| 276 | +MODULE_DEVICE_TABLE(pci, cmodio_pci_ids); | |
| 277 | + | |
| 278 | +static struct pci_driver cmodio_pci_driver = { | |
| 279 | + .name = DRV_NAME, | |
| 280 | + .id_table = cmodio_pci_ids, | |
| 281 | + .probe = cmodio_pci_probe, | |
| 282 | + .remove = __devexit_p(cmodio_pci_remove), | |
| 283 | +}; | |
| 284 | + | |
| 285 | +/* | |
| 286 | + * Module Init / Exit | |
| 287 | + */ | |
| 288 | + | |
| 289 | +static int __init cmodio_init(void) | |
| 290 | +{ | |
| 291 | + return pci_register_driver(&cmodio_pci_driver); | |
| 292 | +} | |
| 293 | + | |
| 294 | +static void __exit cmodio_exit(void) | |
| 295 | +{ | |
| 296 | + pci_unregister_driver(&cmodio_pci_driver); | |
| 297 | +} | |
| 298 | + | |
| 299 | +MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>"); | |
| 300 | +MODULE_DESCRIPTION("Janz CMOD-IO PCI MODULbus Carrier Board Driver"); | |
| 301 | +MODULE_LICENSE("GPL"); | |
| 302 | + | |
| 303 | +module_init(cmodio_init); | |
| 304 | +module_exit(cmodio_exit); | |
| @@ -508,7 +508,7 @@ static int max8925_irq_init(struct max8925_chip *chip, int irq, · 507 unmodified lines | ||
| 508 | 508 | max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2); |
| 509 | 509 | max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ); |
| 510 | 510 | max8925_reg_read(chip->adc, MAX8925_TSC_IRQ); |
| 511 | − /* mask all interrupts */ | |
| 511 | + /* mask all interrupts except for TSC */ | |
| 512 | 512 | max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0); |
| 513 | 513 | max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0); |
| 514 | 514 | max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff); |
| @@ -516,7 +516,6 @@ static int max8925_irq_init(struct max8925_chip *chip, int irq, · 1 unmodified line | ||
| 516 | 516 | max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff); |
| 517 | 517 | max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff); |
| 518 | 518 | max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff); |
| 519 | − max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0xff); | |
| 520 | 519 | |
| 521 | 520 | mutex_init(&chip->irq_lock); |
| 522 | 521 | chip->core_irq = irq; |
| @@ -547,7 +546,11 @@ static int max8925_irq_init(struct max8925_chip *chip, int irq, · 24 unmodified lines | ||
| 547 | 546 | dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret); |
| 548 | 547 | chip->core_irq = 0; |
| 549 | 548 | } |
| 549 | + | |
| 550 | 550 | tsc_irq: |
| 551 | + /* mask TSC interrupt */ | |
| 552 | + max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f); | |
| 553 | + | |
| 551 | 554 | if (!pdata->tsc_irq) { |
| 552 | 555 | dev_warn(chip->dev, "No interrupt support on TSC IRQ\n"); |
| 553 | 556 | return 0; |
| @@ -173,8 +173,6 @@ static int __devexit max8925_remove(struct i2c_client *client) · 172 unmodified lines | ||
| 173 | 173 | max8925_device_exit(chip); |
| 174 | 174 | i2c_unregister_device(chip->adc); |
| 175 | 175 | i2c_unregister_device(chip->rtc); |
| 176 | − i2c_set_clientdata(chip->adc, NULL); | |
| 177 | − i2c_set_clientdata(chip->rtc, NULL); | |
| 178 | 176 | i2c_set_clientdata(chip->i2c, NULL); |
| 179 | 177 | kfree(chip); |
| 180 | 178 | return 0; |
| @@ -1228,6 +1228,7 @@ fail2: · 1227 unmodified lines | ||
| 1228 | 1228 | free_irq(client->irq, menelaus); |
| 1229 | 1229 | flush_scheduled_work(); |
| 1230 | 1230 | fail1: |
| 1231 | + i2c_set_clientdata(client, NULL); | |
| 1231 | 1232 | kfree(menelaus); |
| 1232 | 1233 | return err; |
| 1233 | 1234 | } |
| @@ -1237,8 +1238,8 @@ static int __exit menelaus_remove(struct i2c_client *client) · 3 unmodified lines | ||
| 1237 | 1238 | struct menelaus_chip *menelaus = i2c_get_clientdata(client); |
| 1238 | 1239 | |
| 1239 | 1240 | free_irq(client->irq, menelaus); |
| 1240 | − kfree(menelaus); | |
| 1241 | 1241 | i2c_set_clientdata(client, NULL); |
| 1242 | + kfree(menelaus); | |
| 1242 | 1243 | the_menelaus = NULL; |
| 1243 | 1244 | return 0; |
| 1244 | 1245 | } |
| @@ -48,7 +48,7 @@ static int mfd_add_device(struct device *parent, int id, · 47 unmodified lines | ||
| 48 | 48 | res[r].flags = cell->resources[r].flags; |
| 49 | 49 | |
| 50 | 50 | /* Find out base to use */ |
| 51 | − if (cell->resources[r].flags & IORESOURCE_MEM) { | |
| 51 | + if ((cell->resources[r].flags & IORESOURCE_MEM) && mem_base) { | |
| 52 | 52 | res[r].parent = mem_base; |
| 53 | 53 | res[r].start = mem_base->start + |
| 54 | 54 | cell->resources[r].start; |
| @@ -30,13 +30,13 @@ · 29 unmodified lines | ||
| 30 | 30 | struct pcf50633_adc_request { |
| 31 | 31 | int mux; |
| 32 | 32 | int avg; |
| 33 | − int result; | |
| 34 | 33 | void (*callback)(struct pcf50633 *, void *, int); |
| 35 | 34 | void *callback_param; |
| 35 | +}; | |
| 36 | 36 | |
| 37 | − /* Used in case of sync requests */ | |
| 37 | +struct pcf50633_adc_sync_request { | |
| 38 | + int result; | |
| 38 | 39 | struct completion completion; |
| 39 | − | |
| 40 | 40 | }; |
| 41 | 41 | |
| 42 | 42 | #define PCF50633_MAX_ADC_FIFO_DEPTH 8 |
| @@ -109,10 +109,10 @@ adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req) · 66 unmodified lines | ||
| 109 | 109 | return 0; |
| 110 | 110 | } |
| 111 | 111 | |
| 112 | −static void | |
| 113 | −pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result) | |
| 112 | +static void pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, | |
| 113 | + int result) | |
| 114 | 114 | { |
| 115 | − struct pcf50633_adc_request *req = param; | |
| 115 | + struct pcf50633_adc_sync_request *req = param; | |
| 116 | 116 | |
| 117 | 117 | req->result = result; |
| 118 | 118 | complete(&req->completion); |
| @@ -120,28 +120,19 @@ pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result) · 1 unmodified line | ||
| 120 | 120 | |
| 121 | 121 | int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg) |
| 122 | 122 | { |
| 123 | − struct pcf50633_adc_request *req; | |
| 124 | − int err; | |
| 123 | + struct pcf50633_adc_sync_request req; | |
| 124 | + int ret; | |
| 125 | 125 | |
| 126 | − /* req is freed when the result is ready, in interrupt handler */ | |
| 127 | − req = kzalloc(sizeof(*req), GFP_KERNEL); | |
| 128 | − if (!req) | |
| 129 | − return -ENOMEM; | |
| 130 | − | |
| 131 | − req->mux = mux; | |
| 132 | − req->avg = avg; | |
| 133 | − req->callback = pcf50633_adc_sync_read_callback; | |
| 134 | − req->callback_param = req; | |
| 126 | + init_completion(&req.completion); | |
| 135 | 127 | |
| 136 | − init_completion(&req->completion); | |
| 137 | − err = adc_enqueue_request(pcf, req); | |
| 138 | − if (err) | |
| 139 | − return err; | |
| 128 | + ret = pcf50633_adc_async_read(pcf, mux, avg, | |
| 129 | + pcf50633_adc_sync_read_callback, &req); | |
| 130 | + if (ret) | |
| 131 | + return ret; | |
| 140 | 132 | |
| 141 | − wait_for_completion(&req->completion); | |
| 133 | + wait_for_completion(&req.completion); | |
| 142 | 134 | |
| 143 | − /* FIXME by this time req might be already freed */ | |
| 144 | − return req->result; | |
| 135 | + return req.result; | |
| 145 | 136 | } |
| 146 | 137 | EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read); |
| 147 | 138 | |
| @@ -21,16 +21,16 @@ · 20 unmodified lines | ||
| 21 | 21 | #include <linux/workqueue.h> |
| 22 | 22 | #include <linux/platform_device.h> |
| 23 | 23 | #include <linux/i2c.h> |
| 24 | −#include <linux/irq.h> | |
| 25 | 24 | #include <linux/slab.h> |
| 26 | 25 | |
| 27 | 26 | #include <linux/mfd/pcf50633/core.h> |
| 28 | 27 | |
| 29 | −/* Two MBCS registers used during cold start */ | |
| 30 | −#define PCF50633_REG_MBCS1 0x4b | |
| 31 | −#define PCF50633_REG_MBCS2 0x4c | |
| 32 | −#define PCF50633_MBCS1_USBPRES 0x01 | |
| 33 | −#define PCF50633_MBCS1_ADAPTPRES 0x01 | |
| 28 | +int pcf50633_irq_init(struct pcf50633 *pcf, int irq); | |
| 29 | +void pcf50633_irq_free(struct pcf50633 *pcf); | |
| 30 | +#ifdef CONFIG_PM | |
| 31 | +int pcf50633_irq_suspend(struct pcf50633 *pcf); | |
| 32 | +int pcf50633_irq_resume(struct pcf50633 *pcf); | |
| 33 | +#endif | |
| 34 | 34 | |
| 35 | 35 | static int __pcf50633_read(struct pcf50633 *pcf, u8 reg, int num, u8 *data) |
| 36 | 36 | { |
| @@ -215,244 +215,6 @@ static struct attribute_group pcf_attr_group = { · 178 unmodified lines | ||
| 215 | 215 | .attrs = pcf_sysfs_entries, |
| 216 | 216 | }; |
| 217 | 217 | |
| 218 | −int pcf50633_register_irq(struct pcf50633 *pcf, int irq, | |
| 219 | − void (*handler) (int, void *), void *data) | |
| 220 | −{ | |
| 221 | − if (irq < 0 || irq > PCF50633_NUM_IRQ || !handler) | |
| 222 | − return -EINVAL; | |
| 223 | − | |
| 224 | − if (WARN_ON(pcf->irq_handler[irq].handler)) | |
| 225 | − return -EBUSY; | |
| 226 | − | |
| 227 | − mutex_lock(&pcf->lock); | |
| 228 | − pcf->irq_handler[irq].handler = handler; | |
| 229 | − pcf->irq_handler[irq].data = data; | |
| 230 | − mutex_unlock(&pcf->lock); | |
| 231 | − | |
| 232 | − return 0; | |
| 233 | −} | |
| 234 | −EXPORT_SYMBOL_GPL(pcf50633_register_irq); | |
| 235 | − | |
| 236 | −int pcf50633_free_irq(struct pcf50633 *pcf, int irq) | |
| 237 | −{ | |
| 238 | − if (irq < 0 || irq > PCF50633_NUM_IRQ) | |
| 239 | − return -EINVAL; | |
| 240 | − | |
| 241 | − mutex_lock(&pcf->lock); | |
| 242 | − pcf->irq_handler[irq].handler = NULL; | |
| 243 | − mutex_unlock(&pcf->lock); | |
| 244 | − | |
| 245 | − return 0; | |
| 246 | −} | |
| 247 | −EXPORT_SYMBOL_GPL(pcf50633_free_irq); | |
| 248 | − | |
| 249 | −static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask) | |
| 250 | −{ | |
| 251 | − u8 reg, bits, tmp; | |
| 252 | − int ret = 0, idx; | |
| 253 | − | |
| 254 | − idx = irq >> 3; | |
| 255 | − reg = PCF50633_REG_INT1M + idx; | |
| 256 | − bits = 1 << (irq & 0x07); | |
| 257 | − | |
| 258 | − mutex_lock(&pcf->lock); | |
| 259 | − | |
| 260 | − if (mask) { | |
| 261 | − ret = __pcf50633_read(pcf, reg, 1, &tmp); | |
| 262 | − if (ret < 0) | |
| 263 | − goto out; | |
| 264 | − | |
| 265 | − tmp |= bits; | |
| 266 | − | |
| 267 | − ret = __pcf50633_write(pcf, reg, 1, &tmp); | |
| 268 | − if (ret < 0) | |
| 269 | − goto out; | |
| 270 | − | |
| 271 | − pcf->mask_regs[idx] &= ~bits; | |
| 272 | − pcf->mask_regs[idx] |= bits; | |
| 273 | − } else { | |
| 274 | − ret = __pcf50633_read(pcf, reg, 1, &tmp); | |
| 275 | − if (ret < 0) | |
| 276 | − goto out; | |
| 277 | − | |
| 278 | − tmp &= ~bits; | |
| 279 | − | |
| 280 | − ret = __pcf50633_write(pcf, reg, 1, &tmp); | |
| 281 | − if (ret < 0) | |
| 282 | − goto out; | |
| 283 | − | |
| 284 | − pcf->mask_regs[idx] &= ~bits; | |
| 285 | − } | |
| 286 | −out: | |
| 287 | − mutex_unlock(&pcf->lock); | |
| 288 | − | |
| 289 | − return ret; | |
| 290 | −} | |
| 291 | − | |
| 292 | −int pcf50633_irq_mask(struct pcf50633 *pcf, int irq) | |
| 293 | −{ | |
| 294 | − dev_dbg(pcf->dev, "Masking IRQ %d\n", irq); | |
| 295 | − | |
| 296 | − return __pcf50633_irq_mask_set(pcf, irq, 1); | |
| 297 | −} | |
| 298 | −EXPORT_SYMBOL_GPL(pcf50633_irq_mask); | |
| 299 | − | |
| 300 | −int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq) | |
| 301 | −{ | |
| 302 | − dev_dbg(pcf->dev, "Unmasking IRQ %d\n", irq); | |
| 303 | − | |
| 304 | − return __pcf50633_irq_mask_set(pcf, irq, 0); | |
| 305 | −} | |
| 306 | −EXPORT_SYMBOL_GPL(pcf50633_irq_unmask); | |
| 307 | − | |
| 308 | −int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq) | |
| 309 | −{ | |
| 310 | − u8 reg, bits; | |
| 311 | − | |
| 312 | − reg = irq >> 3; | |
| 313 | − bits = 1 << (irq & 0x07); | |
| 314 | − | |
| 315 | − return pcf->mask_regs[reg] & bits; | |
| 316 | −} | |
| 317 | −EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get); | |
| 318 | − | |
| 319 | −static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq) | |
| 320 | −{ | |
| 321 | − if (pcf->irq_handler[irq].handler) | |
| 322 | − pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data); | |
| 323 | −} | |
| 324 | − | |
| 325 | −/* Maximum amount of time ONKEY is held before emergency action is taken */ | |
| 326 | −#define PCF50633_ONKEY1S_TIMEOUT 8 | |
| 327 | − | |
| 328 | −static void pcf50633_irq_worker(struct work_struct *work) | |
| 329 | −{ | |
| 330 | − struct pcf50633 *pcf; | |
| 331 | − int ret, i, j; | |
| 332 | − u8 pcf_int[5], chgstat; | |
| 333 | − | |
| 334 | − pcf = container_of(work, struct pcf50633, irq_work); | |
| 335 | − | |
| 336 | − /* Read the 5 INT regs in one transaction */ | |
| 337 | − ret = pcf50633_read_block(pcf, PCF50633_REG_INT1, | |
| 338 | − ARRAY_SIZE(pcf_int), pcf_int); | |
| 339 | − if (ret != ARRAY_SIZE(pcf_int)) { | |
| 340 | − dev_err(pcf->dev, "Error reading INT registers\n"); | |
| 341 | − | |
| 342 | − /* | |
| 343 | − * If this doesn't ACK the interrupt to the chip, we'll be | |
| 344 | − * called once again as we're level triggered. | |
| 345 | − */ | |
| 346 | − goto out; | |
| 347 | − } | |
| 348 | − | |
| 349 | − /* defeat 8s death from lowsys on A5 */ | |
| 350 | − pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04); | |
| 351 | − | |
| 352 | − /* We immediately read the usb and adapter status. We thus make sure | |
| 353 | − * only of USBINS/USBREM IRQ handlers are called */ | |
| 354 | − if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) { | |
| 355 | − chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | |
| 356 | − if (chgstat & (0x3 << 4)) | |
| 357 | − pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM); | |
| 358 | − else | |
| 359 | − pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS); | |
| 360 | − } | |
| 361 | − | |
| 362 | − /* Make sure only one of ADPINS or ADPREM is set */ | |
| 363 | − if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) { | |
| 364 | − chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | |
| 365 | − if (chgstat & (0x3 << 4)) | |
| 366 | − pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM); | |
| 367 | − else | |
| 368 | − pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS); | |
| 369 | − } | |
| 370 | − | |
| 371 | − dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x " | |
| 372 | − "INT4=0x%02x INT5=0x%02x\n", pcf_int[0], | |
| 373 | − pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]); | |
| 374 | − | |
| 375 | − /* Some revisions of the chip don't have a 8s standby mode on | |
| 376 | − * ONKEY1S press. We try to manually do it in such cases. */ | |
| 377 | − if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) { | |
| 378 | − dev_info(pcf->dev, "ONKEY1S held for %d secs\n", | |
| 379 | − pcf->onkey1s_held); | |
| 380 | − if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT) | |
| 381 | − if (pcf->pdata->force_shutdown) | |
| 382 | − pcf->pdata->force_shutdown(pcf); | |
| 383 | − } | |
| 384 | − | |
| 385 | − if (pcf_int[2] & PCF50633_INT3_ONKEY1S) { | |
| 386 | − dev_info(pcf->dev, "ONKEY1S held\n"); | |
| 387 | − pcf->onkey1s_held = 1 ; | |
| 388 | − | |
| 389 | − /* Unmask IRQ_SECOND */ | |
| 390 | − pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, | |
| 391 | − PCF50633_INT1_SECOND); | |
| 392 | − | |
| 393 | − /* Unmask IRQ_ONKEYR */ | |
| 394 | − pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M, | |
| 395 | − PCF50633_INT2_ONKEYR); | |
| 396 | − } | |
| 397 | − | |
| 398 | − if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) { | |
| 399 | − pcf->onkey1s_held = 0; | |
| 400 | − | |
| 401 | − /* Mask SECOND and ONKEYR interrupts */ | |
| 402 | − if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) | |
| 403 | − pcf50633_reg_set_bit_mask(pcf, | |
| 404 | − PCF50633_REG_INT1M, | |
| 405 | − PCF50633_INT1_SECOND, | |
| 406 | − PCF50633_INT1_SECOND); | |
| 407 | − | |
| 408 | − if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) | |
| 409 | − pcf50633_reg_set_bit_mask(pcf, | |
| 410 | − PCF50633_REG_INT2M, | |
| 411 | − PCF50633_INT2_ONKEYR, | |
| 412 | − PCF50633_INT2_ONKEYR); | |
| 413 | − } | |
| 414 | − | |
| 415 | − /* Have we just resumed ? */ | |
| 416 | − if (pcf->is_suspended) { | |
| 417 | − pcf->is_suspended = 0; | |
| 418 | − | |
| 419 | − /* Set the resume reason filtering out non resumers */ | |
| 420 | − for (i = 0; i < ARRAY_SIZE(pcf_int); i++) | |
| 421 | − pcf->resume_reason[i] = pcf_int[i] & | |
| 422 | − pcf->pdata->resumers[i]; | |
| 423 | − | |
| 424 | − /* Make sure we don't pass on any ONKEY events to | |
| 425 | − * userspace now */ | |
| 426 | − pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF); | |
| 427 | − } | |
| 428 | − | |
| 429 | − for (i = 0; i < ARRAY_SIZE(pcf_int); i++) { | |
| 430 | − /* Unset masked interrupts */ | |
| 431 | − pcf_int[i] &= ~pcf->mask_regs[i]; | |
| 432 | − | |
| 433 | − for (j = 0; j < 8 ; j++) | |
| 434 | − if (pcf_int[i] & (1 << j)) | |
| 435 | − pcf50633_irq_call_handler(pcf, (i * 8) + j); | |
| 436 | − } | |
| 437 | − | |
| 438 | −out: | |
| 439 | − put_device(pcf->dev); | |
| 440 | − enable_irq(pcf->irq); | |
| 441 | −} | |
| 442 | − | |
| 443 | −static irqreturn_t pcf50633_irq(int irq, void *data) | |
| 444 | −{ | |
| 445 | − struct pcf50633 *pcf = data; | |
| 446 | − | |
| 447 | − dev_dbg(pcf->dev, "pcf50633_irq\n"); | |
| 448 | − | |
| 449 | − get_device(pcf->dev); | |
| 450 | − disable_irq_nosync(pcf->irq); | |
| 451 | − queue_work(pcf->work_queue, &pcf->irq_work); | |
| 452 | − | |
| 453 | − return IRQ_HANDLED; | |
| 454 | −} | |
| 455 | − | |
| 456 | 218 | static void |
| 457 | 219 | pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name, |
| 458 | 220 | struct platform_device **pdev) |
| @@ -479,70 +241,17 @@ pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name, · 20 unmodified lines | ||
| 479 | 241 | static int pcf50633_suspend(struct i2c_client *client, pm_message_t state) |
| 480 | 242 | { |
| 481 | 243 | struct pcf50633 *pcf; |
| 482 | − int ret = 0, i; | |
| 483 | − u8 res[5]; | |
| 484 | − | |
| 485 | 244 | pcf = i2c_get_clientdata(client); |
| 486 | 245 | |
| 487 | − /* Make sure our interrupt handlers are not called | |
| 488 | − * henceforth */ | |
| 489 | − disable_irq(pcf->irq); | |
| 490 | − | |
| 491 | − /* Make sure that any running IRQ worker has quit */ | |
| 492 | − cancel_work_sync(&pcf->irq_work); | |
| 493 | − | |
| 494 | − /* Save the masks */ | |
| 495 | − ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M, | |
| 496 | − ARRAY_SIZE(pcf->suspend_irq_masks), | |
| 497 | − pcf->suspend_irq_masks); | |
| 498 | − if (ret < 0) { | |
| 499 | − dev_err(pcf->dev, "error saving irq masks\n"); | |
| 500 | − goto out; | |
| 501 | − } | |
| 502 | − | |
| 503 | − /* Write wakeup irq masks */ | |
| 504 | − for (i = 0; i < ARRAY_SIZE(res); i++) | |
| 505 | − res[i] = ~pcf->pdata->resumers[i]; | |
| 506 | − | |
| 507 | − ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | |
| 508 | − ARRAY_SIZE(res), &res[0]); | |
| 509 | − if (ret < 0) { | |
| 510 | − dev_err(pcf->dev, "error writing wakeup irq masks\n"); | |
| 511 | − goto out; | |
| 512 | − } | |
| 513 | − | |
| 514 | − pcf->is_suspended = 1; | |
| 515 | − | |
| 516 | −out: | |
| 517 | − return ret; | |
| 246 | + return pcf50633_irq_suspend(pcf); | |
| 518 | 247 | } |
| 519 | 248 | |
| 520 | 249 | static int pcf50633_resume(struct i2c_client *client) |
| 521 | 250 | { |
| 522 | 251 | struct pcf50633 *pcf; |
| 523 | − int ret; | |
| 524 | − | |
| 525 | 252 | pcf = i2c_get_clientdata(client); |
| 526 | 253 | |
| 527 | − /* Write the saved mask registers */ | |
| 528 | − ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | |
| 529 | − ARRAY_SIZE(pcf->suspend_irq_masks), | |
| 530 | − pcf->suspend_irq_masks); | |
| 531 | − if (ret < 0) | |
| 532 | − dev_err(pcf->dev, "Error restoring saved suspend masks\n"); | |
| 533 | − | |
| 534 | − /* Restore regulators' state */ | |
| 535 | − | |
| 536 | − | |
| 537 | − get_device(pcf->dev); | |
| 538 | − | |
| 539 | − /* | |
| 540 | − * Clear any pending interrupts and set resume reason if any. | |
| 541 | − * This will leave with enable_irq() | |
| 542 | − */ | |
| 543 | − pcf50633_irq_worker(&pcf->irq_work); | |
| 544 | − | |
| 545 | − return 0; | |
| 254 | + return pcf50633_irq_resume(pcf); | |
| 546 | 255 | } |
| 547 | 256 | #else |
| 548 | 257 | #define pcf50633_suspend NULL |
| @@ -573,43 +282,19 @@ static int __devinit pcf50633_probe(struct i2c_client *client, · 24 unmodified lines | ||
| 573 | 282 | i2c_set_clientdata(client, pcf); |
| 574 | 283 | pcf->dev = &client->dev; |
| 575 | 284 | pcf->i2c_client = client; |
| 576 | − pcf->irq = client->irq; | |
| 577 | − pcf->work_queue = create_singlethread_workqueue("pcf50633"); | |
| 578 | − | |
| 579 | − if (!pcf->work_queue) { | |
| 580 | − dev_err(&client->dev, "Failed to alloc workqueue\n"); | |
| 581 | − ret = -ENOMEM; | |
| 582 | − goto err_free; | |
| 583 | − } | |
| 584 | − | |
| 585 | − INIT_WORK(&pcf->irq_work, pcf50633_irq_worker); | |
| 586 | 285 | |
| 587 | 286 | version = pcf50633_reg_read(pcf, 0); |
| 588 | 287 | variant = pcf50633_reg_read(pcf, 1); |
| 589 | 288 | if (version < 0 || variant < 0) { |
| 590 | 289 | dev_err(pcf->dev, "Unable to probe pcf50633\n"); |
| 591 | 290 | ret = -ENODEV; |
| 592 | − goto err_destroy_workqueue; | |
| 291 | + goto err_free; | |
| 593 | 292 | } |
| 594 | 293 | |
| 595 | 294 | dev_info(pcf->dev, "Probed device version %d variant %d\n", |
| 596 | 295 | version, variant); |
| 597 | 296 | |
| 598 | − /* Enable all interrupts except RTC SECOND */ | |
| 599 | − pcf->mask_regs[0] = 0x80; | |
| 600 | − pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); | |
| 601 | − pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00); | |
| 602 | − pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00); | |
| 603 | − pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00); | |
| 604 | − pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00); | |
| 605 | − | |
| 606 | − ret = request_irq(client->irq, pcf50633_irq, | |
| 607 | − IRQF_TRIGGER_LOW, "pcf50633", pcf); | |
| 608 | − | |
| 609 | − if (ret) { | |
| 610 | − dev_err(pcf->dev, "Failed to request IRQ %d\n", ret); | |
| 611 | − goto err_destroy_workqueue; | |
| 612 | − } | |
| 297 | + pcf50633_irq_init(pcf, client->irq); | |
| 613 | 298 | |
| 614 | 299 | /* Create sub devices */ |
| 615 | 300 | pcf50633_client_dev_register(pcf, "pcf50633-input", |
| @@ -641,10 +326,6 @@ static int __devinit pcf50633_probe(struct i2c_client *client, · 25 unmodified lines | ||
| 641 | 326 | platform_device_add(pdev); |
| 642 | 327 | } |
| 643 | 328 | |
| 644 | − if (enable_irq_wake(client->irq) < 0) | |
| 645 | − dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source" | |
| 646 | − "in this hardware revision", client->irq); | |
| 647 | − | |
| 648 | 329 | ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group); |
| 649 | 330 | if (ret) |
| 650 | 331 | dev_err(pcf->dev, "error creating sysfs entries\n"); |
| @@ -654,8 +335,6 @@ static int __devinit pcf50633_probe(struct i2c_client *client, · 3 unmodified lines | ||
| 654 | 335 | |
| 655 | 336 | return 0; |
| 656 | 337 | |
| 657 | −err_destroy_workqueue: | |
| 658 | − destroy_workqueue(pcf->work_queue); | |
| 659 | 338 | err_free: |
| 660 | 339 | i2c_set_clientdata(client, NULL); |
| 661 | 340 | kfree(pcf); |
| @@ -668,8 +347,7 @@ static int __devexit pcf50633_remove(struct i2c_client *client) · 6 unmodified lines | ||
| 668 | 347 | struct pcf50633 *pcf = i2c_get_clientdata(client); |
| 669 | 348 | int i; |
| 670 | 349 | |
| 671 | − free_irq(pcf->irq, pcf); | |
| 672 | − destroy_workqueue(pcf->work_queue); | |
| 350 | + pcf50633_irq_free(pcf); | |
| 673 | 351 | |
| 674 | 352 | platform_device_unregister(pcf->input_pdev); |
| 675 | 353 | platform_device_unregister(pcf->rtc_pdev); |
| @@ -679,6 +357,7 @@ static int __devexit pcf50633_remove(struct i2c_client *client) · 3 unmodified lines | ||
| 679 | 357 | for (i = 0; i < PCF50633_NUM_REGULATORS; i++) |
| 680 | 358 | platform_device_unregister(pcf->regulator_pdev[i]); |
| 681 | 359 | |
| 360 | + i2c_set_clientdata(client, NULL); | |
| 682 | 361 | kfree(pcf); |
| 683 | 362 | |
| 684 | 363 | return 0; |
| @@ -0,0 +1,318 @@ | ||
| 1 | +/* NXP PCF50633 Power Management Unit (PMU) driver | |
| 2 | + * | |
| 3 | + * (C) 2006-2008 by Openmoko, Inc. | |
| 4 | + * Author: Harald Welte <laforge@openmoko.org> | |
| 5 | + * Balaji Rao <balajirrao@openmoko.org> | |
| 6 | + * All rights reserved. | |
| 7 | + * | |
| 8 | + * This program is free software; you can redistribute it and/or modify it | |
| 9 | + * under the terms of the GNU General Public License as published by the | |
| 10 | + * Free Software Foundation; either version 2 of the License, or (at your | |
| 11 | + * option) any later version. | |
| 12 | + * | |
| 13 | + */ | |
| 14 | + | |
| 15 | +#include <linux/interrupt.h> | |
| 16 | +#include <linux/kernel.h> | |
| 17 | +#include <linux/mutex.h> | |
| 18 | +#include <linux/slab.h> | |
| 19 | + | |
| 20 | +#include <linux/mfd/pcf50633/core.h> | |
| 21 | + | |
| 22 | +/* Two MBCS registers used during cold start */ | |
| 23 | +#define PCF50633_REG_MBCS1 0x4b | |
| 24 | +#define PCF50633_REG_MBCS2 0x4c | |
| 25 | +#define PCF50633_MBCS1_USBPRES 0x01 | |
| 26 | +#define PCF50633_MBCS1_ADAPTPRES 0x01 | |
| 27 | + | |
| 28 | +int pcf50633_register_irq(struct pcf50633 *pcf, int irq, | |
| 29 | + void (*handler) (int, void *), void *data) | |
| 30 | +{ | |
| 31 | + if (irq < 0 || irq >= PCF50633_NUM_IRQ || !handler) | |
| 32 | + return -EINVAL; | |
| 33 | + | |
| 34 | + if (WARN_ON(pcf->irq_handler[irq].handler)) | |
| 35 | + return -EBUSY; | |
| 36 | + | |
| 37 | + mutex_lock(&pcf->lock); | |
| 38 | + pcf->irq_handler[irq].handler = handler; | |
| 39 | + pcf->irq_handler[irq].data = data; | |
| 40 | + mutex_unlock(&pcf->lock); | |
| 41 | + | |
| 42 | + return 0; | |
| 43 | +} | |
| 44 | +EXPORT_SYMBOL_GPL(pcf50633_register_irq); | |
| 45 | + | |
| 46 | +int pcf50633_free_irq(struct pcf50633 *pcf, int irq) | |
| 47 | +{ | |
| 48 | + if (irq < 0 || irq >= PCF50633_NUM_IRQ) | |
| 49 | + return -EINVAL; | |
| 50 | + | |
| 51 | + mutex_lock(&pcf->lock); | |
| 52 | + pcf->irq_handler[irq].handler = NULL; | |
| 53 | + mutex_unlock(&pcf->lock); | |
| 54 | + | |
| 55 | + return 0; | |
| 56 | +} | |
| 57 | +EXPORT_SYMBOL_GPL(pcf50633_free_irq); | |
| 58 | + | |
| 59 | +static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask) | |
| 60 | +{ | |
| 61 | + u8 reg, bit; | |
| 62 | + int ret = 0, idx; | |
| 63 | + | |
| 64 | + idx = irq >> 3; | |
| 65 | + reg = PCF50633_REG_INT1M + idx; | |
| 66 | + bit = 1 << (irq & 0x07); | |
| 67 | + | |
| 68 | + pcf50633_reg_set_bit_mask(pcf, reg, bit, mask ? bit : 0); | |
| 69 | + | |
| 70 | + mutex_lock(&pcf->lock); | |
| 71 | + | |
| 72 | + if (mask) | |
| 73 | + pcf->mask_regs[idx] |= bit; | |
| 74 | + else | |
| 75 | + pcf->mask_regs[idx] &= ~bit; | |
| 76 | + | |
| 77 | + mutex_unlock(&pcf->lock); | |
| 78 | + | |
| 79 | + return ret; | |
| 80 | +} | |
| 81 | + | |
| 82 | +int pcf50633_irq_mask(struct pcf50633 *pcf, int irq) | |
| 83 | +{ | |
| 84 | + dev_dbg(pcf->dev, "Masking IRQ %d\n", irq); | |
| 85 | + | |
| 86 | + return __pcf50633_irq_mask_set(pcf, irq, 1); | |
| 87 | +} | |
| 88 | +EXPORT_SYMBOL_GPL(pcf50633_irq_mask); | |
| 89 | + | |
| 90 | +int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq) | |
| 91 | +{ | |
| 92 | + dev_dbg(pcf->dev, "Unmasking IRQ %d\n", irq); | |
| 93 | + | |
| 94 | + return __pcf50633_irq_mask_set(pcf, irq, 0); | |
| 95 | +} | |
| 96 | +EXPORT_SYMBOL_GPL(pcf50633_irq_unmask); | |
| 97 | + | |
| 98 | +int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq) | |
| 99 | +{ | |
| 100 | + u8 reg, bits; | |
| 101 | + | |
| 102 | + reg = irq >> 3; | |
| 103 | + bits = 1 << (irq & 0x07); | |
| 104 | + | |
| 105 | + return pcf->mask_regs[reg] & bits; | |
| 106 | +} | |
| 107 | +EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get); | |
| 108 | + | |
| 109 | +static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq) | |
| 110 | +{ | |
| 111 | + if (pcf->irq_handler[irq].handler) | |
| 112 | + pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data); | |
| 113 | +} | |
| 114 | + | |
| 115 | +/* Maximum amount of time ONKEY is held before emergency action is taken */ | |
| 116 | +#define PCF50633_ONKEY1S_TIMEOUT 8 | |
| 117 | + | |
| 118 | +static irqreturn_t pcf50633_irq(int irq, void *data) | |
| 119 | +{ | |
| 120 | + struct pcf50633 *pcf = data; | |
| 121 | + int ret, i, j; | |
| 122 | + u8 pcf_int[5], chgstat; | |
| 123 | + | |
| 124 | + /* Read the 5 INT regs in one transaction */ | |
| 125 | + ret = pcf50633_read_block(pcf, PCF50633_REG_INT1, | |
| 126 | + ARRAY_SIZE(pcf_int), pcf_int); | |
| 127 | + if (ret != ARRAY_SIZE(pcf_int)) { | |
| 128 | + dev_err(pcf->dev, "Error reading INT registers\n"); | |
| 129 | + | |
| 130 | + /* | |
| 131 | + * If this doesn't ACK the interrupt to the chip, we'll be | |
| 132 | + * called once again as we're level triggered. | |
| 133 | + */ | |
| 134 | + goto out; | |
| 135 | + } | |
| 136 | + | |
| 137 | + /* defeat 8s death from lowsys on A5 */ | |
| 138 | + pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04); | |
| 139 | + | |
| 140 | + /* We immediately read the usb and adapter status. We thus make sure | |
| 141 | + * only of USBINS/USBREM IRQ handlers are called */ | |
| 142 | + if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) { | |
| 143 | + chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | |
| 144 | + if (chgstat & (0x3 << 4)) | |
| 145 | + pcf_int[0] &= ~PCF50633_INT1_USBREM; | |
| 146 | + else | |
| 147 | + pcf_int[0] &= ~PCF50633_INT1_USBINS; | |
| 148 | + } | |
| 149 | + | |
| 150 | + /* Make sure only one of ADPINS or ADPREM is set */ | |
| 151 | + if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) { | |
| 152 | + chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | |
| 153 | + if (chgstat & (0x3 << 4)) | |
| 154 | + pcf_int[0] &= ~PCF50633_INT1_ADPREM; | |
| 155 | + else | |
| 156 | + pcf_int[0] &= ~PCF50633_INT1_ADPINS; | |
| 157 | + } | |
| 158 | + | |
| 159 | + dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x " | |
| 160 | + "INT4=0x%02x INT5=0x%02x\n", pcf_int[0], | |
| 161 | + pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]); | |
| 162 | + | |
| 163 | + /* Some revisions of the chip don't have a 8s standby mode on | |
| 164 | + * ONKEY1S press. We try to manually do it in such cases. */ | |
| 165 | + if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) { | |
| 166 | + dev_info(pcf->dev, "ONKEY1S held for %d secs\n", | |
| 167 | + pcf->onkey1s_held); | |
| 168 | + if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT) | |
| 169 | + if (pcf->pdata->force_shutdown) | |
| 170 | + pcf->pdata->force_shutdown(pcf); | |
| 171 | + } | |
| 172 | + | |
| 173 | + if (pcf_int[2] & PCF50633_INT3_ONKEY1S) { | |
| 174 | + dev_info(pcf->dev, "ONKEY1S held\n"); | |
| 175 | + pcf->onkey1s_held = 1 ; | |
| 176 | + | |
| 177 | + /* Unmask IRQ_SECOND */ | |
| 178 | + pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, | |
| 179 | + PCF50633_INT1_SECOND); | |
| 180 | + | |
| 181 | + /* Unmask IRQ_ONKEYR */ | |
| 182 | + pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M, | |
| 183 | + PCF50633_INT2_ONKEYR); | |
| 184 | + } | |
| 185 | + | |
| 186 | + if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) { | |
| 187 | + pcf->onkey1s_held = 0; | |
| 188 | + | |
| 189 | + /* Mask SECOND and ONKEYR interrupts */ | |
| 190 | + if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) | |
| 191 | + pcf50633_reg_set_bit_mask(pcf, | |
| 192 | + PCF50633_REG_INT1M, | |
| 193 | + PCF50633_INT1_SECOND, | |
| 194 | + PCF50633_INT1_SECOND); | |
| 195 | + | |
| 196 | + if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) | |
| 197 | + pcf50633_reg_set_bit_mask(pcf, | |
| 198 | + PCF50633_REG_INT2M, | |
| 199 | + PCF50633_INT2_ONKEYR, | |
| 200 | + PCF50633_INT2_ONKEYR); | |
| 201 | + } | |
| 202 | + | |
| 203 | + /* Have we just resumed ? */ | |
| 204 | + if (pcf->is_suspended) { | |
| 205 | + pcf->is_suspended = 0; | |
| 206 | + | |
| 207 | + /* Set the resume reason filtering out non resumers */ | |
| 208 | + for (i = 0; i < ARRAY_SIZE(pcf_int); i++) | |
| 209 | + pcf->resume_reason[i] = pcf_int[i] & | |
| 210 | + pcf->pdata->resumers[i]; | |
| 211 | + | |
| 212 | + /* Make sure we don't pass on any ONKEY events to | |
| 213 | + * userspace now */ | |
| 214 | + pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF); | |
| 215 | + } | |
| 216 | + | |
| 217 | + for (i = 0; i < ARRAY_SIZE(pcf_int); i++) { | |
| 218 | + /* Unset masked interrupts */ | |
| 219 | + pcf_int[i] &= ~pcf->mask_regs[i]; | |
| 220 | + | |
| 221 | + for (j = 0; j < 8 ; j++) | |
| 222 | + if (pcf_int[i] & (1 << j)) | |
| 223 | + pcf50633_irq_call_handler(pcf, (i * 8) + j); | |
| 224 | + } | |
| 225 | + | |
| 226 | +out: | |
| 227 | + return IRQ_HANDLED; | |
| 228 | +} | |
| 229 | + | |
| 230 | +#ifdef CONFIG_PM | |
| 231 | + | |
| 232 | +int pcf50633_irq_suspend(struct pcf50633 *pcf) | |
| 233 | +{ | |
| 234 | + int ret; | |
| 235 | + int i; | |
| 236 | + u8 res[5]; | |
| 237 | + | |
| 238 | + | |
| 239 | + /* Make sure our interrupt handlers are not called | |
| 240 | + * henceforth */ | |
| 241 | + disable_irq(pcf->irq); | |
| 242 | + | |
| 243 | + /* Save the masks */ | |
| 244 | + ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M, | |
| 245 | + ARRAY_SIZE(pcf->suspend_irq_masks), | |
| 246 | + pcf->suspend_irq_masks); | |
| 247 | + if (ret < 0) { | |
| 248 | + dev_err(pcf->dev, "error saving irq masks\n"); | |
| 249 | + goto out; | |
| 250 | + } | |
| 251 | + | |
| 252 | + /* Write wakeup irq masks */ | |
| 253 | + for (i = 0; i < ARRAY_SIZE(res); i++) | |
| 254 | + res[i] = ~pcf->pdata->resumers[i]; | |
| 255 | + | |
| 256 | + ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | |
| 257 | + ARRAY_SIZE(res), &res[0]); | |
| 258 | + if (ret < 0) { | |
| 259 | + dev_err(pcf->dev, "error writing wakeup irq masks\n"); | |
| 260 | + goto out; | |
| 261 | + } | |
| 262 | + | |
| 263 | + pcf->is_suspended = 1; | |
| 264 | + | |
| 265 | +out: | |
| 266 | + return ret; | |
| 267 | +} | |
| 268 | + | |
| 269 | +int pcf50633_irq_resume(struct pcf50633 *pcf) | |
| 270 | +{ | |
| 271 | + int ret; | |
| 272 | + | |
| 273 | + /* Write the saved mask registers */ | |
| 274 | + ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | |
| 275 | + ARRAY_SIZE(pcf->suspend_irq_masks), | |
| 276 | + pcf->suspend_irq_masks); | |
| 277 | + if (ret < 0) | |
| 278 | + dev_err(pcf->dev, "Error restoring saved suspend masks\n"); | |
| 279 | + | |
| 280 | + enable_irq(pcf->irq); | |
| 281 | + | |
| 282 | + return ret; | |
| 283 | +} | |
| 284 | + | |
| 285 | +#endif | |
| 286 | + | |
| 287 | +int pcf50633_irq_init(struct pcf50633 *pcf, int irq) | |
| 288 | +{ | |
| 289 | + int ret; | |
| 290 | + | |
| 291 | + pcf->irq = irq; | |
| 292 | + | |
| 293 | + /* Enable all interrupts except RTC SECOND */ | |
| 294 | + pcf->mask_regs[0] = 0x80; | |
| 295 | + pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); | |
| 296 | + pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00); | |
| 297 | + pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00); | |
| 298 | + pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00); | |
| 299 | + pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00); | |
| 300 | + | |
| 301 | + ret = request_threaded_irq(irq, NULL, pcf50633_irq, | |
| 302 | + IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
| 303 | + "pcf50633", pcf); | |
| 304 | + | |
| 305 | + if (ret) | |
| 306 | + dev_err(pcf->dev, "Failed to request IRQ %d\n", ret); | |
| 307 | + | |
| 308 | + if (enable_irq_wake(irq) < 0) | |
| 309 | + dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source" | |
| 310 | + "in this hardware revision", irq); | |
| 311 | + | |
| 312 | + return ret; | |
| 313 | +} | |
| 314 | + | |
| 315 | +void pcf50633_irq_free(struct pcf50633 *pcf) | |
| 316 | +{ | |
| 317 | + free_irq(pcf->irq, pcf); | |
| 318 | +} | |
| @@ -0,0 +1,123 @@ | ||
| 1 | +/* | |
| 2 | + * RDC321x MFD southbrige driver | |
| 3 | + * | |
| 4 | + * Copyright (C) 2007-2010 Florian Fainelli <florian@openwrt.org> | |
| 5 | + * Copyright (C) 2010 Bernhard Loos <bernhardloos@googlemail.com> | |
| 6 | + * | |
| 7 | + * This program is free software; you can redistribute it and/or modify | |
| 8 | + * it under the terms of the GNU General Public License as published by | |
| 9 | + * the Free Software Foundation; either version 2 of the License, or | |
| 10 | + * (at your option) any later version. | |
| 11 | + * | |
| 12 | + * This program is distributed in the hope that it will be useful, | |
| 13 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | + * GNU General Public License for more details. | |
| 16 | + * | |
| 17 | + * You should have received a copy of the GNU General Public License | |
| 18 | + * along with this program; if not, write to the Free Software | |
| 19 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 20 | + * | |
| 21 | + */ | |
| 22 | +#include <linux/init.h> | |
| 23 | +#include <linux/module.h> | |
| 24 | +#include <linux/kernel.h> | |
| 25 | +#include <linux/platform_device.h> | |
| 26 | +#include <linux/pci.h> | |
| 27 | +#include <linux/mfd/core.h> | |
| 28 | +#include <linux/mfd/rdc321x.h> | |
| 29 | + | |
| 30 | +static struct rdc321x_wdt_pdata rdc321x_wdt_pdata; | |
| 31 | + | |
| 32 | +static struct resource rdc321x_wdt_resource[] = { | |
| 33 | + { | |
| 34 | + .name = "wdt-reg", | |
| 35 | + .start = RDC321X_WDT_CTRL, | |
| 36 | + .end = RDC321X_WDT_CTRL + 0x3, | |
| 37 | + .flags = IORESOURCE_IO, | |
| 38 | + } | |
| 39 | +}; | |
| 40 | + | |
| 41 | +static struct rdc321x_gpio_pdata rdc321x_gpio_pdata = { | |
| 42 | + .max_gpios = RDC321X_MAX_GPIO, | |
| 43 | +}; | |
| 44 | + | |
| 45 | +static struct resource rdc321x_gpio_resources[] = { | |
| 46 | + { | |
| 47 | + .name = "gpio-reg1", | |
| 48 | + .start = RDC321X_GPIO_CTRL_REG1, | |
| 49 | + .end = RDC321X_GPIO_CTRL_REG1 + 0x7, | |
| 50 | + .flags = IORESOURCE_IO, | |
| 51 | + }, { | |
| 52 | + .name = "gpio-reg2", | |
| 53 | + .start = RDC321X_GPIO_CTRL_REG2, | |
| 54 | + .end = RDC321X_GPIO_CTRL_REG2 + 0x7, | |
| 55 | + .flags = IORESOURCE_IO, | |
| 56 | + } | |
| 57 | +}; | |
| 58 | + | |
| 59 | +static struct mfd_cell rdc321x_sb_cells[] = { | |
| 60 | + { | |
| 61 | + .name = "rdc321x-wdt", | |
| 62 | + .resources = rdc321x_wdt_resource, | |
| 63 | + .num_resources = ARRAY_SIZE(rdc321x_wdt_resource), | |
| 64 | + .driver_data = &rdc321x_wdt_pdata, | |
| 65 | + }, { | |
| 66 | + .name = "rdc321x-gpio", | |
| 67 | + .resources = rdc321x_gpio_resources, | |
| 68 | + .num_resources = ARRAY_SIZE(rdc321x_gpio_resources), | |
| 69 | + .driver_data = &rdc321x_gpio_pdata, | |
| 70 | + }, | |
| 71 | +}; | |
| 72 | + | |
| 73 | +static int __devinit rdc321x_sb_probe(struct pci_dev *pdev, | |
| 74 | + const struct pci_device_id *ent) | |
| 75 | +{ | |
| 76 | + int err; | |
| 77 | + | |
| 78 | + err = pci_enable_device(pdev); | |
| 79 | + if (err) { | |
| 80 | + dev_err(&pdev->dev, "failed to enable device\n"); | |
| 81 | + return err; | |
| 82 | + } | |
| 83 | + | |
| 84 | + rdc321x_gpio_pdata.sb_pdev = pdev; | |
| 85 | + rdc321x_wdt_pdata.sb_pdev = pdev; | |
| 86 | + | |
| 87 | + return mfd_add_devices(&pdev->dev, -1, | |
| 88 | + rdc321x_sb_cells, ARRAY_SIZE(rdc321x_sb_cells), NULL, 0); | |
| 89 | +} | |
| 90 | + | |
| 91 | +static void __devexit rdc321x_sb_remove(struct pci_dev *pdev) | |
| 92 | +{ | |
| 93 | + mfd_remove_devices(&pdev->dev); | |
| 94 | +} | |
| 95 | + | |
| 96 | +static DEFINE_PCI_DEVICE_TABLE(rdc321x_sb_table) = { | |
| 97 | + { PCI_DEVICE(PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030) }, | |
| 98 | + {} | |
| 99 | +}; | |
| 100 | + | |
| 101 | +static struct pci_driver rdc321x_sb_driver = { | |
| 102 | + .name = "RDC321x Southbridge", | |
| 103 | + .id_table = rdc321x_sb_table, | |
| 104 | + .probe = rdc321x_sb_probe, | |
| 105 | + .remove = __devexit_p(rdc321x_sb_remove), | |
| 106 | +}; | |
| 107 | + | |
| 108 | +static int __init rdc321x_sb_init(void) | |
| 109 | +{ | |
| 110 | + return pci_register_driver(&rdc321x_sb_driver); | |
| 111 | +} | |
| 112 | + | |
| 113 | +static void __exit rdc321x_sb_exit(void) | |
| 114 | +{ | |
| 115 | + pci_unregister_driver(&rdc321x_sb_driver); | |
| 116 | +} | |
| 117 | + | |
| 118 | +module_init(rdc321x_sb_init); | |
| 119 | +module_exit(rdc321x_sb_exit); | |
| 120 | + | |
| 121 | +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); | |
| 122 | +MODULE_LICENSE("GPL"); | |
| 123 | +MODULE_DESCRIPTION("RDC R-321x MFD southbridge driver"); | |
| @@ -318,6 +318,9 @@ static int t7l66xb_probe(struct platform_device *dev) · 317 unmodified lines | ||
| 318 | 318 | struct resource *iomem, *rscr; |
| 319 | 319 | int ret; |
| 320 | 320 | |
| 321 | + if (pdata == NULL) | |
| 322 | + return -EINVAL; | |
| 323 | + | |
| 321 | 324 | iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); |
| 322 | 325 | if (!iomem) |
| 323 | 326 | return -EINVAL; |
| @@ -0,0 +1,347 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | + * | |
| 4 | + * License Terms: GNU General Public License, version 2 | |
| 5 | + * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson | |
| 6 | + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
| 7 | + */ | |
| 8 | + | |
| 9 | +#include <linux/module.h> | |
| 10 | +#include <linux/interrupt.h> | |
| 11 | +#include <linux/irq.h> | |
| 12 | +#include <linux/slab.h> | |
| 13 | +#include <linux/i2c.h> | |
| 14 | +#include <linux/mfd/core.h> | |
| 15 | +#include <linux/mfd/tc35892.h> | |
| 16 | + | |
| 17 | +/** | |
| 18 | + * tc35892_reg_read() - read a single TC35892 register | |
| 19 | + * @tc35892: Device to read from | |
| 20 | + * @reg: Register to read | |
| 21 | + */ | |
| 22 | +int tc35892_reg_read(struct tc35892 *tc35892, u8 reg) | |
| 23 | +{ | |
| 24 | + int ret; | |
| 25 | + | |
| 26 | + ret = i2c_smbus_read_byte_data(tc35892->i2c, reg); | |
| 27 | + if (ret < 0) | |
| 28 | + dev_err(tc35892->dev, "failed to read reg %#x: %d\n", | |
| 29 | + reg, ret); | |
| 30 | + | |
| 31 | + return ret; | |
| 32 | +} | |
| 33 | +EXPORT_SYMBOL_GPL(tc35892_reg_read); | |
| 34 | + | |
| 35 | +/** | |
| 36 | + * tc35892_reg_read() - write a single TC35892 register | |
| 37 | + * @tc35892: Device to write to | |
| 38 | + * @reg: Register to read | |
| 39 | + * @data: Value to write | |
| 40 | + */ | |
| 41 | +int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data) | |
| 42 | +{ | |
| 43 | + int ret; | |
| 44 | + | |
| 45 | + ret = i2c_smbus_write_byte_data(tc35892->i2c, reg, data); | |
| 46 | + if (ret < 0) | |
| 47 | + dev_err(tc35892->dev, "failed to write reg %#x: %d\n", | |
| 48 | + reg, ret); | |
| 49 | + | |
| 50 | + return ret; | |
| 51 | +} | |
| 52 | +EXPORT_SYMBOL_GPL(tc35892_reg_write); | |
| 53 | + | |
| 54 | +/** | |
| 55 | + * tc35892_block_read() - read multiple TC35892 registers | |
| 56 | + * @tc35892: Device to read from | |
| 57 | + * @reg: First register | |
| 58 | + * @length: Number of registers | |
| 59 | + * @values: Buffer to write to | |
| 60 | + */ | |
| 61 | +int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length, u8 *values) | |
| 62 | +{ | |
| 63 | + int ret; | |
| 64 | + | |
| 65 | + ret = i2c_smbus_read_i2c_block_data(tc35892->i2c, reg, length, values); | |
| 66 | + if (ret < 0) | |
| 67 | + dev_err(tc35892->dev, "failed to read regs %#x: %d\n", | |
| 68 | + reg, ret); | |
| 69 | + | |
| 70 | + return ret; | |
| 71 | +} | |
| 72 | +EXPORT_SYMBOL_GPL(tc35892_block_read); | |
| 73 | + | |
| 74 | +/** | |
| 75 | + * tc35892_block_write() - write multiple TC35892 registers | |
| 76 | + * @tc35892: Device to write to | |
| 77 | + * @reg: First register | |
| 78 | + * @length: Number of registers | |
| 79 | + * @values: Values to write | |
| 80 | + */ | |
| 81 | +int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length, | |
| 82 | + const u8 *values) | |
| 83 | +{ | |
| 84 | + int ret; | |
| 85 | + | |
| 86 | + ret = i2c_smbus_write_i2c_block_data(tc35892->i2c, reg, length, | |
| 87 | + values); | |
| 88 | + if (ret < 0) | |
| 89 | + dev_err(tc35892->dev, "failed to write regs %#x: %d\n", | |
| 90 | + reg, ret); | |
| 91 | + | |
| 92 | + return ret; | |
| 93 | +} | |
| 94 | +EXPORT_SYMBOL_GPL(tc35892_block_write); | |
| 95 | + | |
| 96 | +/** | |
| 97 | + * tc35892_set_bits() - set the value of a bitfield in a TC35892 register | |
| 98 | + * @tc35892: Device to write to | |
| 99 | + * @reg: Register to write | |
| 100 | + * @mask: Mask of bits to set | |
| 101 | + * @values: Value to set | |
| 102 | + */ | |
| 103 | +int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val) | |
| 104 | +{ | |
| 105 | + int ret; | |
| 106 | + | |
| 107 | + mutex_lock(&tc35892->lock); | |
| 108 | + | |
| 109 | + ret = tc35892_reg_read(tc35892, reg); | |
| 110 | + if (ret < 0) | |
| 111 | + goto out; | |
| 112 | + | |
| 113 | + ret &= ~mask; | |
| 114 | + ret |= val; | |
| 115 | + | |
| 116 | + ret = tc35892_reg_write(tc35892, reg, ret); | |
| 117 | + | |
| 118 | +out: | |
| 119 | + mutex_unlock(&tc35892->lock); | |
| 120 | + return ret; | |
| 121 | +} | |
| 122 | +EXPORT_SYMBOL_GPL(tc35892_set_bits); | |
| 123 | + | |
| 124 | +static struct resource gpio_resources[] = { | |
| 125 | + { | |
| 126 | + .start = TC35892_INT_GPIIRQ, | |
| 127 | + .end = TC35892_INT_GPIIRQ, | |
| 128 | + .flags = IORESOURCE_IRQ, | |
| 129 | + }, | |
| 130 | +}; | |
| 131 | + | |
| 132 | +static struct mfd_cell tc35892_devs[] = { | |
| 133 | + { | |
| 134 | + .name = "tc35892-gpio", | |
| 135 | + .num_resources = ARRAY_SIZE(gpio_resources), | |
| 136 | + .resources = &gpio_resources[0], | |
| 137 | + }, | |
| 138 | +}; | |
| 139 | + | |
| 140 | +static irqreturn_t tc35892_irq(int irq, void *data) | |
| 141 | +{ | |
| 142 | + struct tc35892 *tc35892 = data; | |
| 143 | + int status; | |
| 144 | + | |
| 145 | + status = tc35892_reg_read(tc35892, TC35892_IRQST); | |
| 146 | + if (status < 0) | |
| 147 | + return IRQ_NONE; | |
| 148 | + | |
| 149 | + while (status) { | |
| 150 | + int bit = __ffs(status); | |
| 151 | + | |
| 152 | + handle_nested_irq(tc35892->irq_base + bit); | |
| 153 | + status &= ~(1 << bit); | |
| 154 | + } | |
| 155 | + | |
| 156 | + /* | |
| 157 | + * A dummy read or write (to any register) appears to be necessary to | |
| 158 | + * have the last interrupt clear (for example, GPIO IC write) take | |
| 159 | + * effect. | |
| 160 | + */ | |
| 161 | + tc35892_reg_read(tc35892, TC35892_IRQST); | |
| 162 | + | |
| 163 | + return IRQ_HANDLED; | |
| 164 | +} | |
| 165 | + | |
| 166 | +static void tc35892_irq_dummy(unsigned int irq) | |
| 167 | +{ | |
| 168 | + /* No mask/unmask at this level */ | |
| 169 | +} | |
| 170 | + | |
| 171 | +static struct irq_chip tc35892_irq_chip = { | |
| 172 | + .name = "tc35892", | |
| 173 | + .mask = tc35892_irq_dummy, | |
| 174 | + .unmask = tc35892_irq_dummy, | |
| 175 | +}; | |
| 176 | + | |
| 177 | +static int tc35892_irq_init(struct tc35892 *tc35892) | |
| 178 | +{ | |
| 179 | + int base = tc35892->irq_base; | |
| 180 | + int irq; | |
| 181 | + | |
| 182 | + for (irq = base; irq < base + TC35892_NR_INTERNAL_IRQS; irq++) { | |
| 183 | + set_irq_chip_data(irq, tc35892); | |
| 184 | + set_irq_chip_and_handler(irq, &tc35892_irq_chip, | |
| 185 | + handle_edge_irq); | |
| 186 | + set_irq_nested_thread(irq, 1); | |
| 187 | +#ifdef CONFIG_ARM | |
| 188 | + set_irq_flags(irq, IRQF_VALID); | |
| 189 | +#else | |
| 190 | + set_irq_noprobe(irq); | |
| 191 | +#endif | |
| 192 | + } | |
| 193 | + | |
| 194 | + return 0; | |
| 195 | +} | |
| 196 | + | |
| 197 | +static void tc35892_irq_remove(struct tc35892 *tc35892) | |
| 198 | +{ | |
| 199 | + int base = tc35892->irq_base; | |
| 200 | + int irq; | |
| 201 | + | |
| 202 | + for (irq = base; irq < base + TC35892_NR_INTERNAL_IRQS; irq++) { | |
| 203 | +#ifdef CONFIG_ARM | |
| 204 | + set_irq_flags(irq, 0); | |
| 205 | +#endif | |
| 206 | + set_irq_chip_and_handler(irq, NULL, NULL); | |
| 207 | + set_irq_chip_data(irq, NULL); | |
| 208 | + } | |
| 209 | +} | |
| 210 | + | |
| 211 | +static int tc35892_chip_init(struct tc35892 *tc35892) | |
| 212 | +{ | |
| 213 | + int manf, ver, ret; | |
| 214 | + | |
| 215 | + manf = tc35892_reg_read(tc35892, TC35892_MANFCODE); | |
| 216 | + if (manf < 0) | |
| 217 | + return manf; | |
| 218 | + | |
| 219 | + ver = tc35892_reg_read(tc35892, TC35892_VERSION); | |
| 220 | + if (ver < 0) | |
| 221 | + return ver; | |
| 222 | + | |
| 223 | + if (manf != TC35892_MANFCODE_MAGIC) { | |
| 224 | + dev_err(tc35892->dev, "unknown manufacturer: %#x\n", manf); | |
| 225 | + return -EINVAL; | |
| 226 | + } | |
| 227 | + | |
| 228 | + dev_info(tc35892->dev, "manufacturer: %#x, version: %#x\n", manf, ver); | |
| 229 | + | |
| 230 | + /* Put everything except the IRQ module into reset */ | |
| 231 | + ret = tc35892_reg_write(tc35892, TC35892_RSTCTRL, | |
| 232 | + TC35892_RSTCTRL_TIMRST | |
| 233 | + | TC35892_RSTCTRL_ROTRST | |
| 234 | + | TC35892_RSTCTRL_KBDRST | |
| 235 | + | TC35892_RSTCTRL_GPIRST); | |
| 236 | + if (ret < 0) | |
| 237 | + return ret; | |
| 238 | + | |
| 239 | + /* Clear the reset interrupt. */ | |
| 240 | + return tc35892_reg_write(tc35892, TC35892_RSTINTCLR, 0x1); | |
| 241 | +} | |
| 242 | + | |
| 243 | +static int __devinit tc35892_probe(struct i2c_client *i2c, | |
| 244 | + const struct i2c_device_id *id) | |
| 245 | +{ | |
| 246 | + struct tc35892_platform_data *pdata = i2c->dev.platform_data; | |
| 247 | + struct tc35892 *tc35892; | |
| 248 | + int ret; | |
| 249 | + | |
| 250 | + if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA | |
| 251 | + | I2C_FUNC_SMBUS_I2C_BLOCK)) | |
| 252 | + return -EIO; | |
| 253 | + | |
| 254 | + tc35892 = kzalloc(sizeof(struct tc35892), GFP_KERNEL); | |
| 255 | + if (!tc35892) | |
| 256 | + return -ENOMEM; | |
| 257 | + | |
| 258 | + mutex_init(&tc35892->lock); | |
| 259 | + | |
| 260 | + tc35892->dev = &i2c->dev; | |
| 261 | + tc35892->i2c = i2c; | |
| 262 | + tc35892->pdata = pdata; | |
| 263 | + tc35892->irq_base = pdata->irq_base; | |
| 264 | + tc35892->num_gpio = id->driver_data; | |
| 265 | + | |
| 266 | + i2c_set_clientdata(i2c, tc35892); | |
| 267 | + | |
| 268 | + ret = tc35892_chip_init(tc35892); | |
| 269 | + if (ret) | |
| 270 | + goto out_free; | |
| 271 | + | |
| 272 | + ret = tc35892_irq_init(tc35892); | |
| 273 | + if (ret) | |
| 274 | + goto out_free; | |
| 275 | + | |
| 276 | + ret = request_threaded_irq(tc35892->i2c->irq, NULL, tc35892_irq, | |
| 277 | + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
| 278 | + "tc35892", tc35892); | |
| 279 | + if (ret) { | |
| 280 | + dev_err(tc35892->dev, "failed to request IRQ: %d\n", ret); | |
| 281 | + goto out_removeirq; | |
| 282 | + } | |
| 283 | + | |
| 284 | + ret = mfd_add_devices(tc35892->dev, -1, tc35892_devs, | |
| 285 | + ARRAY_SIZE(tc35892_devs), NULL, | |
| 286 | + tc35892->irq_base); | |
| 287 | + if (ret) { | |
| 288 | + dev_err(tc35892->dev, "failed to add children\n"); | |
| 289 | + goto out_freeirq; | |
| 290 | + } | |
| 291 | + | |
| 292 | + return 0; | |
| 293 | + | |
| 294 | +out_freeirq: | |
| 295 | + free_irq(tc35892->i2c->irq, tc35892); | |
| 296 | +out_removeirq: | |
| 297 | + tc35892_irq_remove(tc35892); | |
| 298 | +out_free: | |
| 299 | + i2c_set_clientdata(i2c, NULL); | |
| 300 | + kfree(tc35892); | |
| 301 | + return ret; | |
| 302 | +} | |
| 303 | + | |
| 304 | +static int __devexit tc35892_remove(struct i2c_client *client) | |
| 305 | +{ | |
| 306 | + struct tc35892 *tc35892 = i2c_get_clientdata(client); | |
| 307 | + | |
| 308 | + mfd_remove_devices(tc35892->dev); | |
| 309 | + | |
| 310 | + free_irq(tc35892->i2c->irq, tc35892); | |
| 311 | + tc35892_irq_remove(tc35892); | |
| 312 | + | |
| 313 | + i2c_set_clientdata(client, NULL); | |
| 314 | + kfree(tc35892); | |
| 315 | + | |
| 316 | + return 0; | |
| 317 | +} | |
| 318 | + | |
| 319 | +static const struct i2c_device_id tc35892_id[] = { | |
| 320 | + { "tc35892", 24 }, | |
| 321 | + { } | |
| 322 | +}; | |
| 323 | +MODULE_DEVICE_TABLE(i2c, tc35892_id); | |
| 324 | + | |
| 325 | +static struct i2c_driver tc35892_driver = { | |
| 326 | + .driver.name = "tc35892", | |
| 327 | + .driver.owner = THIS_MODULE, | |
| 328 | + .probe = tc35892_probe, | |
| 329 | + .remove = __devexit_p(tc35892_remove), | |
| 330 | + .id_table = tc35892_id, | |
| 331 | +}; | |
| 332 | + | |
| 333 | +static int __init tc35892_init(void) | |
| 334 | +{ | |
| 335 | + return i2c_add_driver(&tc35892_driver); | |
| 336 | +} | |
| 337 | +subsys_initcall(tc35892_init); | |
| 338 | + | |
| 339 | +static void __exit tc35892_exit(void) | |
| 340 | +{ | |
| 341 | + i2c_del_driver(&tc35892_driver); | |
| 342 | +} | |
| 343 | +module_exit(tc35892_exit); | |
| 344 | + | |
| 345 | +MODULE_LICENSE("GPL v2"); | |
| 346 | +MODULE_DESCRIPTION("TC35892 MFD core driver"); | |
| 347 | +MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); | |
| @@ -31,6 +31,7 @@ · 30 unmodified lines | ||
| 31 | 31 | |
| 32 | 32 | #include <linux/i2c.h> |
| 33 | 33 | #include <linux/i2c-ocores.h> |
| 34 | +#include <linux/i2c-xiic.h> | |
| 34 | 35 | #include <linux/i2c/tsc2007.h> |
| 35 | 36 | |
| 36 | 37 | #include <linux/spi/spi.h> |
| @@ -40,6 +41,8 @@ · 3 unmodified lines | ||
| 40 | 41 | |
| 41 | 42 | #include <media/timb_radio.h> |
| 42 | 43 | |
| 44 | +#include <linux/timb_dma.h> | |
| 45 | + | |
| 43 | 46 | #include "timberdale.h" |
| 44 | 47 | |
| 45 | 48 | #define DRIVER_NAME "timberdale" |
| @@ -69,6 +72,12 @@ static struct i2c_board_info timberdale_i2c_board_info[] = { · 23 unmodified lines | ||
| 69 | 72 | }, |
| 70 | 73 | }; |
| 71 | 74 | |
| 75 | +static __devinitdata struct xiic_i2c_platform_data | |
| 76 | +timberdale_xiic_platform_data = { | |
| 77 | + .devices = timberdale_i2c_board_info, | |
| 78 | + .num_devices = ARRAY_SIZE(timberdale_i2c_board_info) | |
| 79 | +}; | |
| 80 | + | |
| 72 | 81 | static __devinitdata struct ocores_i2c_platform_data |
| 73 | 82 | timberdale_ocores_platform_data = { |
| 74 | 83 | .regstep = 4, |
| @@ -77,7 +86,20 @@ timberdale_ocores_platform_data = { · 2 unmodified lines | ||
| 77 | 86 | .num_devices = ARRAY_SIZE(timberdale_i2c_board_info) |
| 78 | 87 | }; |
| 79 | 88 | |
| 80 | −const static __devinitconst struct resource timberdale_ocores_resources[] = { | |
| 89 | +static const __devinitconst struct resource timberdale_xiic_resources[] = { | |
| 90 | + { | |
| 91 | + .start = XIICOFFSET, | |
| 92 | + .end = XIICEND, | |
| 93 | + .flags = IORESOURCE_MEM, | |
| 94 | + }, | |
| 95 | + { | |
| 96 | + .start = IRQ_TIMBERDALE_I2C, | |
| 97 | + .end = IRQ_TIMBERDALE_I2C, | |
| 98 | + .flags = IORESOURCE_IRQ, | |
| 99 | + }, | |
| 100 | +}; | |
| 101 | + | |
| 102 | +static const __devinitconst struct resource timberdale_ocores_resources[] = { | |
| 81 | 103 | { |
| 82 | 104 | .start = OCORESOFFSET, |
| 83 | 105 | .end = OCORESEND, |
| @@ -126,7 +148,7 @@ static __devinitdata struct xspi_platform_data timberdale_xspi_platform_data = { · 42 unmodified lines | ||
| 126 | 148 | */ |
| 127 | 149 | }; |
| 128 | 150 | |
| 129 | −const static __devinitconst struct resource timberdale_spi_resources[] = { | |
| 151 | +static const __devinitconst struct resource timberdale_spi_resources[] = { | |
| 130 | 152 | { |
| 131 | 153 | .start = SPIOFFSET, |
| 132 | 154 | .end = SPIEND, |
| @@ -139,7 +161,7 @@ const static __devinitconst struct resource timberdale_spi_resources[] = { · 6 unmodified lines | ||
| 139 | 161 | }, |
| 140 | 162 | }; |
| 141 | 163 | |
| 142 | −const static __devinitconst struct resource timberdale_eth_resources[] = { | |
| 164 | +static const __devinitconst struct resource timberdale_eth_resources[] = { | |
| 143 | 165 | { |
| 144 | 166 | .start = ETHOFFSET, |
| 145 | 167 | .end = ETHEND, |
| @@ -159,7 +181,7 @@ static __devinitdata struct timbgpio_platform_data · 13 unmodified lines | ||
| 159 | 181 | .irq_base = 200, |
| 160 | 182 | }; |
| 161 | 183 | |
| 162 | −const static __devinitconst struct resource timberdale_gpio_resources[] = { | |
| 184 | +static const __devinitconst struct resource timberdale_gpio_resources[] = { | |
| 163 | 185 | { |
| 164 | 186 | .start = GPIOOFFSET, |
| 165 | 187 | .end = GPIOEND, |
| @@ -172,7 +194,7 @@ const static __devinitconst struct resource timberdale_gpio_resources[] = { · 6 unmodified lines | ||
| 172 | 194 | }, |
| 173 | 195 | }; |
| 174 | 196 | |
| 175 | −const static __devinitconst struct resource timberdale_mlogicore_resources[] = { | |
| 197 | +static const __devinitconst struct resource timberdale_mlogicore_resources[] = { | |
| 176 | 198 | { |
| 177 | 199 | .start = MLCOREOFFSET, |
| 178 | 200 | .end = MLCOREEND, |
| @@ -190,7 +212,7 @@ const static __devinitconst struct resource timberdale_mlogicore_resources[] = { · 11 unmodified lines | ||
| 190 | 212 | }, |
| 191 | 213 | }; |
| 192 | 214 | |
| 193 | −const static __devinitconst struct resource timberdale_uart_resources[] = { | |
| 215 | +static const __devinitconst struct resource timberdale_uart_resources[] = { | |
| 194 | 216 | { |
| 195 | 217 | .start = UARTOFFSET, |
| 196 | 218 | .end = UARTEND, |
| @@ -203,7 +225,7 @@ const static __devinitconst struct resource timberdale_uart_resources[] = { · 6 unmodified lines | ||
| 203 | 225 | }, |
| 204 | 226 | }; |
| 205 | 227 | |
| 206 | −const static __devinitconst struct resource timberdale_uartlite_resources[] = { | |
| 228 | +static const __devinitconst struct resource timberdale_uartlite_resources[] = { | |
| 207 | 229 | { |
| 208 | 230 | .start = UARTLITEOFFSET, |
| 209 | 231 | .end = UARTLITEEND, |
| @@ -216,7 +238,7 @@ const static __devinitconst struct resource timberdale_uartlite_resources[] = { · 6 unmodified lines | ||
| 216 | 238 | }, |
| 217 | 239 | }; |
| 218 | 240 | |
| 219 | −const static __devinitconst struct resource timberdale_radio_resources[] = { | |
| 241 | +static const __devinitconst struct resource timberdale_radio_resources[] = { | |
| 220 | 242 | { |
| 221 | 243 | .start = RDSOFFSET, |
| 222 | 244 | .end = RDSEND, |
| @@ -250,7 +272,66 @@ static __devinitdata struct timb_radio_platform_data · 27 unmodified lines | ||
| 250 | 272 | } |
| 251 | 273 | }; |
| 252 | 274 | |
| 253 | −const static __devinitconst struct resource timberdale_dma_resources[] = { | |
| 275 | +static __devinitdata struct timb_dma_platform_data timb_dma_platform_data = { | |
| 276 | + .nr_channels = 10, | |
| 277 | + .channels = { | |
| 278 | + { | |
| 279 | + /* UART RX */ | |
| 280 | + .rx = true, | |
| 281 | + .descriptors = 2, | |
| 282 | + .descriptor_elements = 1 | |
| 283 | + }, | |
| 284 | + { | |
| 285 | + /* UART TX */ | |
| 286 | + .rx = false, | |
| 287 | + .descriptors = 2, | |
| 288 | + .descriptor_elements = 1 | |
| 289 | + }, | |
| 290 | + { | |
| 291 | + /* MLB RX */ | |
| 292 | + .rx = true, | |
| 293 | + .descriptors = 2, | |
| 294 | + .descriptor_elements = 1 | |
| 295 | + }, | |
| 296 | + { | |
| 297 | + /* MLB TX */ | |
| 298 | + .rx = false, | |
| 299 | + .descriptors = 2, | |
| 300 | + .descriptor_elements = 1 | |
| 301 | + }, | |
| 302 | + { | |
| 303 | + /* Video RX */ | |
| 304 | + .rx = true, | |
| 305 | + .bytes_per_line = 1440, | |
| 306 | + .descriptors = 2, | |
| 307 | + .descriptor_elements = 16 | |
| 308 | + }, | |
| 309 | + { | |
| 310 | + /* Video framedrop */ | |
| 311 | + }, | |
| 312 | + { | |
| 313 | + /* SDHCI RX */ | |
| 314 | + .rx = true, | |
| 315 | + }, | |
| 316 | + { | |
| 317 | + /* SDHCI TX */ | |
| 318 | + }, | |
| 319 | + { | |
| 320 | + /* ETH RX */ | |
| 321 | + .rx = true, | |
| 322 | + .descriptors = 2, | |
| 323 | + .descriptor_elements = 1 | |
| 324 | + }, | |
| 325 | + { | |
| 326 | + /* ETH TX */ | |
| 327 | + .rx = false, | |
| 328 | + .descriptors = 2, | |
| 329 | + .descriptor_elements = 1 | |
| 330 | + }, | |
| 331 | + } | |
| 332 | +}; | |
| 333 | + | |
| 334 | +static const __devinitconst struct resource timberdale_dma_resources[] = { | |
| 254 | 335 | { |
| 255 | 336 | .start = DMAOFFSET, |
| 256 | 337 | .end = DMAEND, |
| @@ -264,11 +345,25 @@ const static __devinitconst struct resource timberdale_dma_resources[] = { · 7 unmodified lines | ||
| 264 | 345 | }; |
| 265 | 346 | |
| 266 | 347 | static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg0[] = { |
| 348 | + { | |
| 349 | + .name = "timb-dma", | |
| 350 | + .num_resources = ARRAY_SIZE(timberdale_dma_resources), | |
| 351 | + .resources = timberdale_dma_resources, | |
| 352 | + .platform_data = &timb_dma_platform_data, | |
| 353 | + .data_size = sizeof(timb_dma_platform_data), | |
| 354 | + }, | |
| 267 | 355 | { |
| 268 | 356 | .name = "timb-uart", |
| 269 | 357 | .num_resources = ARRAY_SIZE(timberdale_uart_resources), |
| 270 | 358 | .resources = timberdale_uart_resources, |
| 271 | 359 | }, |
| 360 | + { | |
| 361 | + .name = "xiic-i2c", | |
| 362 | + .num_resources = ARRAY_SIZE(timberdale_xiic_resources), | |
| 363 | + .resources = timberdale_xiic_resources, | |
| 364 | + .platform_data = &timberdale_xiic_platform_data, | |
| 365 | + .data_size = sizeof(timberdale_xiic_platform_data), | |
| 366 | + }, | |
| 272 | 367 | { |
| 273 | 368 | .name = "timb-gpio", |
| 274 | 369 | .num_resources = ARRAY_SIZE(timberdale_gpio_resources), |
| @@ -295,14 +390,16 @@ static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg0[] = { · 20 unmodified lines | ||
| 295 | 390 | .num_resources = ARRAY_SIZE(timberdale_eth_resources), |
| 296 | 391 | .resources = timberdale_eth_resources, |
| 297 | 392 | }, |
| 393 | +}; | |
| 394 | + | |
| 395 | +static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg1[] = { | |
| 298 | 396 | { |
| 299 | 397 | .name = "timb-dma", |
| 300 | 398 | .num_resources = ARRAY_SIZE(timberdale_dma_resources), |
| 301 | 399 | .resources = timberdale_dma_resources, |
| 400 | + .platform_data = &timb_dma_platform_data, | |
| 401 | + .data_size = sizeof(timb_dma_platform_data), | |
| 302 | 402 | }, |
| 303 | −}; | |
| 304 | − | |
| 305 | −static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg1[] = { | |
| 306 | 403 | { |
| 307 | 404 | .name = "timb-uart", |
| 308 | 405 | .num_resources = ARRAY_SIZE(timberdale_uart_resources), |
| @@ -313,6 +410,13 @@ static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg1[] = { · 4 unmodified lines | ||
| 313 | 410 | .num_resources = ARRAY_SIZE(timberdale_uartlite_resources), |
| 314 | 411 | .resources = timberdale_uartlite_resources, |
| 315 | 412 | }, |
| 413 | + { | |
| 414 | + .name = "xiic-i2c", | |
| 415 | + .num_resources = ARRAY_SIZE(timberdale_xiic_resources), | |
| 416 | + .resources = timberdale_xiic_resources, | |
| 417 | + .platform_data = &timberdale_xiic_platform_data, | |
| 418 | + .data_size = sizeof(timberdale_xiic_platform_data), | |
| 419 | + }, | |
| 316 | 420 | { |
| 317 | 421 | .name = "timb-gpio", |
| 318 | 422 | .num_resources = ARRAY_SIZE(timberdale_gpio_resources), |
| @@ -344,19 +448,28 @@ static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg1[] = { · 25 unmodified lines | ||
| 344 | 448 | .num_resources = ARRAY_SIZE(timberdale_eth_resources), |
| 345 | 449 | .resources = timberdale_eth_resources, |
| 346 | 450 | }, |
| 451 | +}; | |
| 452 | + | |
| 453 | +static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg2[] = { | |
| 347 | 454 | { |
| 348 | 455 | .name = "timb-dma", |
| 349 | 456 | .num_resources = ARRAY_SIZE(timberdale_dma_resources), |
| 350 | 457 | .resources = timberdale_dma_resources, |
| 458 | + .platform_data = &timb_dma_platform_data, | |
| 459 | + .data_size = sizeof(timb_dma_platform_data), | |
| 351 | 460 | }, |
| 352 | −}; | |
| 353 | − | |
| 354 | −static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg2[] = { | |
| 355 | 461 | { |
| 356 | 462 | .name = "timb-uart", |
| 357 | 463 | .num_resources = ARRAY_SIZE(timberdale_uart_resources), |
| 358 | 464 | .resources = timberdale_uart_resources, |
| 359 | 465 | }, |
| 466 | + { | |
| 467 | + .name = "xiic-i2c", | |
| 468 | + .num_resources = ARRAY_SIZE(timberdale_xiic_resources), | |
| 469 | + .resources = timberdale_xiic_resources, | |
| 470 | + .platform_data = &timberdale_xiic_platform_data, | |
| 471 | + .data_size = sizeof(timberdale_xiic_platform_data), | |
| 472 | + }, | |
| 360 | 473 | { |
| 361 | 474 | .name = "timb-gpio", |
| 362 | 475 | .num_resources = ARRAY_SIZE(timberdale_gpio_resources), |
| @@ -378,14 +491,16 @@ static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg2[] = { · 15 unmodified lines | ||
| 378 | 491 | .platform_data = &timberdale_xspi_platform_data, |
| 379 | 492 | .data_size = sizeof(timberdale_xspi_platform_data), |
| 380 | 493 | }, |
| 494 | +}; | |
| 495 | + | |
| 496 | +static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg3[] = { | |
| 381 | 497 | { |
| 382 | 498 | .name = "timb-dma", |
| 383 | 499 | .num_resources = ARRAY_SIZE(timberdale_dma_resources), |
| 384 | 500 | .resources = timberdale_dma_resources, |
| 501 | + .platform_data = &timb_dma_platform_data, | |
| 502 | + .data_size = sizeof(timb_dma_platform_data), | |
| 385 | 503 | }, |
| 386 | −}; | |
| 387 | − | |
| 388 | −static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg3[] = { | |
| 389 | 504 | { |
| 390 | 505 | .name = "timb-uart", |
| 391 | 506 | .num_resources = ARRAY_SIZE(timberdale_uart_resources), |
| @@ -424,11 +539,6 @@ static __devinitdata struct mfd_cell timberdale_cells_bar0_cfg3[] = { · 32 unmodified lines | ||
| 424 | 539 | .num_resources = ARRAY_SIZE(timberdale_eth_resources), |
| 425 | 540 | .resources = timberdale_eth_resources, |
| 426 | 541 | }, |
| 427 | − { | |
| 428 | − .name = "timb-dma", | |
| 429 | − .num_resources = ARRAY_SIZE(timberdale_dma_resources), | |
| 430 | − .resources = timberdale_dma_resources, | |
| 431 | − }, | |
| 432 | 542 | }; |
| 433 | 543 | |
| 434 | 544 | static const __devinitconst struct resource timberdale_sdhc_resources[] = { |
| @@ -23,7 +23,7 @@ · 22 unmodified lines | ||
| 23 | 23 | #ifndef MFD_TIMBERDALE_H |
| 24 | 24 | #define MFD_TIMBERDALE_H |
| 25 | 25 | |
| 26 | −#define DRV_VERSION "0.1" | |
| 26 | +#define DRV_VERSION "0.2" | |
| 27 | 27 | |
| 28 | 28 | /* This driver only support versions >= 3.8 and < 4.0 */ |
| 29 | 29 | #define TIMB_SUPPORTED_MAJOR 3 |
| @@ -66,7 +66,7 @@ · 36 unmodified lines | ||
| 66 | 66 | |
| 67 | 67 | #define CHIPCTLOFFSET 0x800 |
| 68 | 68 | #define CHIPCTLEND 0x8ff |
| 69 | −#define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET) | |
| 69 | +#define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1) | |
| 70 | 70 | |
| 71 | 71 | #define INTCOFFSET 0xc00 |
| 72 | 72 | #define INTCEND 0xfff |
| @@ -127,4 +127,16 @@ · 54 unmodified lines | ||
| 127 | 127 | #define GPIO_PIN_BT_RST 15 |
| 128 | 128 | #define GPIO_NR_PINS 16 |
| 129 | 129 | |
| 130 | +/* DMA Channels */ | |
| 131 | +#define DMA_UART_RX 0 | |
| 132 | +#define DMA_UART_TX 1 | |
| 133 | +#define DMA_MLB_RX 2 | |
| 134 | +#define DMA_MLB_TX 3 | |
| 135 | +#define DMA_VIDEO_RX 4 | |
| 136 | +#define DMA_VIDEO_DROP 5 | |
| 137 | +#define DMA_SDHCI_RX 6 | |
| 138 | +#define DMA_SDHCI_TX 7 | |
| 139 | +#define DMA_ETH_RX 8 | |
| 140 | +#define DMA_ETH_TX 9 | |
| 141 | + | |
| 130 | 142 | #endif |
| @@ -530,8 +530,8 @@ static int __exit tps65010_remove(struct i2c_client *client) · 529 unmodified lines | ||
| 530 | 530 | cancel_delayed_work(&tps->work); |
| 531 | 531 | flush_scheduled_work(); |
| 532 | 532 | debugfs_remove(tps->file); |
| 533 | − kfree(tps); | |
| 534 | 533 | i2c_set_clientdata(client, NULL); |
| 534 | + kfree(tps); | |
| 535 | 535 | the_tps = NULL; |
| 536 | 536 | return 0; |
| 537 | 537 | } |
| @@ -0,0 +1,159 @@ | ||
| 1 | +/* | |
| 2 | + * tps6507x.c -- TPS6507x chip family multi-function driver | |
| 3 | + * | |
| 4 | + * Copyright (c) 2010 RidgeRun (todd.fischer@ridgerun.com) | |
| 5 | + * | |
| 6 | + * Author: Todd Fischer | |
| 7 | + * todd.fischer@ridgerun.com | |
| 8 | + * | |
| 9 | + * Credits: | |
| 10 | + * | |
| 11 | + * Using code from wm831x-*.c, wm8400-core, Wolfson Microelectronics PLC. | |
| 12 | + * | |
| 13 | + * For licencing details see kernel-base/COPYING | |
| 14 | + * | |
| 15 | + */ | |
| 16 | + | |
| 17 | +#include <linux/module.h> | |
| 18 | +#include <linux/moduleparam.h> | |
| 19 | +#include <linux/init.h> | |
| 20 | +#include <linux/slab.h> | |
| 21 | +#include <linux/i2c.h> | |
| 22 | +#include <linux/mfd/core.h> | |
| 23 | +#include <linux/mfd/tps6507x.h> | |
| 24 | + | |
| 25 | +static struct mfd_cell tps6507x_devs[] = { | |
| 26 | + { | |
| 27 | + .name = "tps6507x-pmic", | |
| 28 | + }, | |
| 29 | + { | |
| 30 | + .name = "tps6507x-ts", | |
| 31 | + }, | |
| 32 | +}; | |
| 33 | + | |
| 34 | + | |
| 35 | +static int tps6507x_i2c_read_device(struct tps6507x_dev *tps6507x, char reg, | |
| 36 | + int bytes, void *dest) | |
| 37 | +{ | |
| 38 | + struct i2c_client *i2c = tps6507x->i2c_client; | |
| 39 | + struct i2c_msg xfer[2]; | |
| 40 | + int ret; | |
| 41 | + | |
| 42 | + /* Write register */ | |
| 43 | + xfer[0].addr = i2c->addr; | |
| 44 | + xfer[0].flags = 0; | |
| 45 | + xfer[0].len = 1; | |
| 46 | + xfer[0].buf = ® | |
| 47 | + | |
| 48 | + /* Read data */ | |
| 49 | + xfer[1].addr = i2c->addr; | |
| 50 | + xfer[1].flags = I2C_M_RD; | |
| 51 | + xfer[1].len = bytes; | |
| 52 | + xfer[1].buf = dest; | |
| 53 | + | |
| 54 | + ret = i2c_transfer(i2c->adapter, xfer, 2); | |
| 55 | + if (ret == 2) | |
| 56 | + ret = 0; | |
| 57 | + else if (ret >= 0) | |
| 58 | + ret = -EIO; | |
| 59 | + | |
| 60 | + return ret; | |
| 61 | +} | |
| 62 | + | |
| 63 | +static int tps6507x_i2c_write_device(struct tps6507x_dev *tps6507x, char reg, | |
| 64 | + int bytes, void *src) | |
| 65 | +{ | |
| 66 | + struct i2c_client *i2c = tps6507x->i2c_client; | |
| 67 | + /* we add 1 byte for device register */ | |
| 68 | + u8 msg[TPS6507X_MAX_REGISTER + 1]; | |
| 69 | + int ret; | |
| 70 | + | |
| 71 | + if (bytes > (TPS6507X_MAX_REGISTER + 1)) | |
| 72 | + return -EINVAL; | |
| 73 | + | |
| 74 | + msg[0] = reg; | |
| 75 | + memcpy(&msg[1], src, bytes); | |
| 76 | + | |
| 77 | + ret = i2c_master_send(i2c, msg, bytes + 1); | |
| 78 | + if (ret < 0) | |
| 79 | + return ret; | |
| 80 | + if (ret != bytes + 1) | |
| 81 | + return -EIO; | |
| 82 | + return 0; | |
| 83 | +} | |
| 84 | + | |
| 85 | +static int tps6507x_i2c_probe(struct i2c_client *i2c, | |
| 86 | + const struct i2c_device_id *id) | |
| 87 | +{ | |
| 88 | + struct tps6507x_dev *tps6507x; | |
| 89 | + int ret = 0; | |
| 90 | + | |
| 91 | + tps6507x = kzalloc(sizeof(struct tps6507x_dev), GFP_KERNEL); | |
| 92 | + if (tps6507x == NULL) { | |
| 93 | + kfree(i2c); | |
| 94 | + return -ENOMEM; | |
| 95 | + } | |
| 96 | + | |
| 97 | + i2c_set_clientdata(i2c, tps6507x); | |
| 98 | + tps6507x->dev = &i2c->dev; | |
| 99 | + tps6507x->i2c_client = i2c; | |
| 100 | + tps6507x->read_dev = tps6507x_i2c_read_device; | |
| 101 | + tps6507x->write_dev = tps6507x_i2c_write_device; | |
| 102 | + | |
| 103 | + ret = mfd_add_devices(tps6507x->dev, -1, | |
| 104 | + tps6507x_devs, ARRAY_SIZE(tps6507x_devs), | |
| 105 | + NULL, 0); | |
| 106 | + | |
| 107 | + if (ret < 0) | |
| 108 | + goto err; | |
| 109 | + | |
| 110 | + return ret; | |
| 111 | + | |
| 112 | +err: | |
| 113 | + mfd_remove_devices(tps6507x->dev); | |
| 114 | + kfree(tps6507x); | |
| 115 | + return ret; | |
| 116 | +} | |
| 117 | + | |
| 118 | +static int tps6507x_i2c_remove(struct i2c_client *i2c) | |
| 119 | +{ | |
| 120 | + struct tps6507x_dev *tps6507x = i2c_get_clientdata(i2c); | |
| 121 | + | |
| 122 | + mfd_remove_devices(tps6507x->dev); | |
| 123 | + kfree(tps6507x); | |
| 124 | + | |
| 125 | + return 0; | |
| 126 | +} | |
| 127 | + | |
| 128 | +static const struct i2c_device_id tps6507x_i2c_id[] = { | |
| 129 | + { "tps6507x", 0 }, | |
| 130 | + { } | |
| 131 | +}; | |
| 132 | +MODULE_DEVICE_TABLE(i2c, tps6507x_i2c_id); | |
| 133 | + | |
| 134 | + | |
| 135 | +static struct i2c_driver tps6507x_i2c_driver = { | |
| 136 | + .driver = { | |
| 137 | + .name = "tps6507x", | |
| 138 | + .owner = THIS_MODULE, | |
| 139 | + }, | |
| 140 | + .probe = tps6507x_i2c_probe, | |
| 141 | + .remove = tps6507x_i2c_remove, | |
| 142 | + .id_table = tps6507x_i2c_id, | |
| 143 | +}; | |
| 144 | + | |
| 145 | +static int __init tps6507x_i2c_init(void) | |
| 146 | +{ | |
| 147 | + return i2c_add_driver(&tps6507x_i2c_driver); | |
| 148 | +} | |
| 149 | +/* init early so consumer devices can complete system boot */ | |
| 150 | +subsys_initcall(tps6507x_i2c_init); | |
| 151 | + | |
| 152 | +static void __exit tps6507x_i2c_exit(void) | |
| 153 | +{ | |
| 154 | + i2c_del_driver(&tps6507x_i2c_driver); | |
| 155 | +} | |
| 156 | +module_exit(tps6507x_i2c_exit); | |
| 157 | + | |
| 158 | +MODULE_DESCRIPTION("TPS6507x chip family multi-function driver"); | |
| 159 | +MODULE_LICENSE("GPL"); | |
| @@ -232,10 +232,11 @@ static const struct sih sih_modules_twl5031[8] = { · 231 unmodified lines | ||
| 232 | 232 | }, |
| 233 | 233 | [6] = { |
| 234 | 234 | /* |
| 235 | − * ACI doesn't use the same SIH organization. | |
| 236 | − * For example, it supports only one interrupt line | |
| 235 | + * ECI/DBI doesn't use the same SIH organization. | |
| 236 | + * For example, it supports only one interrupt output line. | |
| 237 | + * That is, the interrupts are seen on both INT1 and INT2 lines. | |
| 237 | 238 | */ |
| 238 | − .name = "aci", | |
| 239 | + .name = "eci_dbi", | |
| 239 | 240 | .module = TWL5031_MODULE_ACCESSORY, |
| 240 | 241 | .bits = 9, |
| 241 | 242 | .bytes_ixr = 2, |
| @@ -247,8 +248,8 @@ static const struct sih sih_modules_twl5031[8] = { · 5 unmodified lines | ||
| 247 | 248 | |
| 248 | 249 | }, |
| 249 | 250 | [7] = { |
| 250 | − /* Accessory */ | |
| 251 | − .name = "acc", | |
| 251 | + /* Audio accessory */ | |
| 252 | + .name = "audio", | |
| 252 | 253 | .module = TWL5031_MODULE_ACCESSORY, |
| 253 | 254 | .control_offset = TWL5031_ACCSIHCTRL, |
| 254 | 255 | .bits = 2, |
| @@ -322,7 +322,11 @@ EXPORT_SYMBOL_GPL(wm831x_set_bits); · 321 unmodified lines | ||
| 322 | 322 | */ |
| 323 | 323 | int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input) |
| 324 | 324 | { |
| 325 | − int ret, src; | |
| 325 | + int ret, src, irq_masked, timeout; | |
| 326 | + | |
| 327 | + /* Are we using the interrupt? */ | |
| 328 | + irq_masked = wm831x_reg_read(wm831x, WM831X_INTERRUPT_STATUS_1_MASK); | |
| 329 | + irq_masked &= WM831X_AUXADC_DATA_EINT; | |
| 326 | 330 | |
| 327 | 331 | mutex_lock(&wm831x->auxadc_lock); |
| 328 | 332 | |
| @@ -342,6 +346,9 @@ int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input) · 13 unmodified lines | ||
| 342 | 346 | goto out; |
| 343 | 347 | } |
| 344 | 348 | |
| 349 | + /* Clear any notification from a very late arriving interrupt */ | |
| 350 | + try_wait_for_completion(&wm831x->auxadc_done); | |
| 351 | + | |
| 345 | 352 | ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL, |
| 346 | 353 | WM831X_AUX_CVT_ENA, WM831X_AUX_CVT_ENA); |
| 347 | 354 | if (ret < 0) { |
| @@ -349,22 +356,46 @@ int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input) · 1 unmodified line | ||
| 349 | 356 | goto disable; |
| 350 | 357 | } |
| 351 | 358 | |
| 352 | − /* If an interrupt arrived late clean up after it */ | |
| 353 | − try_wait_for_completion(&wm831x->auxadc_done); | |
| 354 | − | |
| 355 | − /* Ignore the result to allow us to soldier on without IRQ hookup */ | |
| 356 | − wait_for_completion_timeout(&wm831x->auxadc_done, msecs_to_jiffies(5)); | |
| 357 | − | |
| 358 | − ret = wm831x_reg_read(wm831x, WM831X_AUXADC_CONTROL); | |
| 359 | − if (ret < 0) { | |
| 360 | − dev_err(wm831x->dev, "AUXADC status read failed: %d\n", ret); | |
| 361 | − goto disable; | |
| 362 | − } | |
| 363 | − | |
| 364 | − if (ret & WM831X_AUX_CVT_ENA) { | |
| 365 | − dev_err(wm831x->dev, "Timed out reading AUXADC\n"); | |
| 366 | − ret = -EBUSY; | |
| 367 | − goto disable; | |
| 359 | + if (irq_masked) { | |
| 360 | + /* If we're not using interrupts then poll the | |
| 361 | + * interrupt status register */ | |
| 362 | + timeout = 5; | |
| 363 | + while (timeout) { | |
| 364 | + msleep(1); | |
| 365 | + | |
| 366 | + ret = wm831x_reg_read(wm831x, | |
| 367 | + WM831X_INTERRUPT_STATUS_1); | |
| 368 | + if (ret < 0) { | |
| 369 | + dev_err(wm831x->dev, | |
| 370 | + "ISR 1 read failed: %d\n", ret); | |
| 371 | + goto disable; | |
| 372 | + } | |
| 373 | + | |
| 374 | + /* Did it complete? */ | |
| 375 | + if (ret & WM831X_AUXADC_DATA_EINT) { | |
| 376 | + wm831x_reg_write(wm831x, | |
| 377 | + WM831X_INTERRUPT_STATUS_1, | |
| 378 | + WM831X_AUXADC_DATA_EINT); | |
| 379 | + break; | |
| 380 | + } else { | |
| 381 | + dev_err(wm831x->dev, | |
| 382 | + "AUXADC conversion timeout\n"); | |
| 383 | + ret = -EBUSY; | |
| 384 | + goto disable; | |
| 385 | + } | |
| 386 | + } | |
| 387 | + } else { | |
| 388 | + /* If we are using interrupts then wait for the | |
| 389 | + * interrupt to complete. Use an extremely long | |
| 390 | + * timeout to handle situations with heavy load where | |
| 391 | + * the notification of the interrupt may be delayed by | |
| 392 | + * threaded IRQ handling. */ | |
| 393 | + if (!wait_for_completion_timeout(&wm831x->auxadc_done, | |
| 394 | + msecs_to_jiffies(500))) { | |
| 395 | + dev_err(wm831x->dev, "Timed out waiting for AUXADC\n"); | |
| 396 | + ret = -EBUSY; | |
| 397 | + goto disable; | |
| 398 | + } | |
| 368 | 399 | } |
| 369 | 400 | |
| 370 | 401 | ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA); |
| @@ -1463,6 +1494,7 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq) · 1092 unmodified lines | ||
| 1463 | 1494 | case WM8310: |
| 1464 | 1495 | parent = WM8310; |
| 1465 | 1496 | wm831x->num_gpio = 16; |
| 1497 | + wm831x->charger_irq_wake = 1; | |
| 1466 | 1498 | if (rev > 0) { |
| 1467 | 1499 | wm831x->has_gpio_ena = 1; |
| 1468 | 1500 | wm831x->has_cs_sts = 1; |
| @@ -1474,6 +1506,7 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq) · 5 unmodified lines | ||
| 1474 | 1506 | case WM8311: |
| 1475 | 1507 | parent = WM8311; |
| 1476 | 1508 | wm831x->num_gpio = 16; |
| 1509 | + wm831x->charger_irq_wake = 1; | |
| 1477 | 1510 | if (rev > 0) { |
| 1478 | 1511 | wm831x->has_gpio_ena = 1; |
| 1479 | 1512 | wm831x->has_cs_sts = 1; |
| @@ -1485,6 +1518,7 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq) · 5 unmodified lines | ||
| 1485 | 1518 | case WM8312: |
| 1486 | 1519 | parent = WM8312; |
| 1487 | 1520 | wm831x->num_gpio = 16; |
| 1521 | + wm831x->charger_irq_wake = 1; | |
| 1488 | 1522 | if (rev > 0) { |
| 1489 | 1523 | wm831x->has_gpio_ena = 1; |
| 1490 | 1524 | wm831x->has_cs_sts = 1; |
| @@ -1623,6 +1657,42 @@ static void wm831x_device_exit(struct wm831x *wm831x) · 132 unmodified lines | ||
| 1623 | 1657 | kfree(wm831x); |
| 1624 | 1658 | } |
| 1625 | 1659 | |
| 1660 | +static int wm831x_device_suspend(struct wm831x *wm831x) | |
| 1661 | +{ | |
| 1662 | + int reg, mask; | |
| 1663 | + | |
| 1664 | + /* If the charger IRQs are a wake source then make sure we ack | |
| 1665 | + * them even if they're not actively being used (eg, no power | |
| 1666 | + * driver or no IRQ line wired up) then acknowledge the | |
| 1667 | + * interrupts otherwise suspend won't last very long. | |
| 1668 | + */ | |
| 1669 | + if (wm831x->charger_irq_wake) { | |
| 1670 | + reg = wm831x_reg_read(wm831x, WM831X_INTERRUPT_STATUS_2_MASK); | |
| 1671 | + | |
| 1672 | + mask = WM831X_CHG_BATT_HOT_EINT | | |
| 1673 | + WM831X_CHG_BATT_COLD_EINT | | |
| 1674 | + WM831X_CHG_BATT_FAIL_EINT | | |
| 1675 | + WM831X_CHG_OV_EINT | WM831X_CHG_END_EINT | | |
| 1676 | + WM831X_CHG_TO_EINT | WM831X_CHG_MODE_EINT | | |
| 1677 | + WM831X_CHG_START_EINT; | |
| 1678 | + | |
| 1679 | + /* If any of the interrupts are masked read the statuses */ | |
| 1680 | + if (reg & mask) | |
| 1681 | + reg = wm831x_reg_read(wm831x, | |
| 1682 | + WM831X_INTERRUPT_STATUS_2); | |
| 1683 | + | |
| 1684 | + if (reg & mask) { | |
| 1685 | + dev_info(wm831x->dev, | |
| 1686 | + "Acknowledging masked charger IRQs: %x\n", | |
| 1687 | + reg & mask); | |
| 1688 | + wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_2, | |
| 1689 | + reg & mask); | |
| 1690 | + } | |
| 1691 | + } | |
| 1692 | + | |
| 1693 | + return 0; | |
| 1694 | +} | |
| 1695 | + | |
| 1626 | 1696 | static int wm831x_i2c_read_device(struct wm831x *wm831x, unsigned short reg, |
| 1627 | 1697 | int bytes, void *dest) |
| 1628 | 1698 | { |
| @@ -1697,6 +1767,13 @@ static int wm831x_i2c_remove(struct i2c_client *i2c) · 68 unmodified lines | ||
| 1697 | 1767 | return 0; |
| 1698 | 1768 | } |
| 1699 | 1769 | |
| 1770 | +static int wm831x_i2c_suspend(struct i2c_client *i2c, pm_message_t mesg) | |
| 1771 | +{ | |
| 1772 | + struct wm831x *wm831x = i2c_get_clientdata(i2c); | |
| 1773 | + | |
| 1774 | + return wm831x_device_suspend(wm831x); | |
| 1775 | +} | |
| 1776 | + | |
| 1700 | 1777 | static const struct i2c_device_id wm831x_i2c_id[] = { |
| 1701 | 1778 | { "wm8310", WM8310 }, |
| 1702 | 1779 | { "wm8311", WM8311 }, |
| @@ -1714,6 +1791,7 @@ static struct i2c_driver wm831x_i2c_driver = { · 11 unmodified lines | ||
| 1714 | 1791 | }, |
| 1715 | 1792 | .probe = wm831x_i2c_probe, |
| 1716 | 1793 | .remove = wm831x_i2c_remove, |
| 1794 | + .suspend = wm831x_i2c_suspend, | |
| 1717 | 1795 | .id_table = wm831x_i2c_id, |
| 1718 | 1796 | }; |
| 1719 | 1797 | |
| @@ -39,8 +39,6 @@ struct wm831x_irq_data { · 38 unmodified lines | ||
| 39 | 39 | int primary; |
| 40 | 40 | int reg; |
| 41 | 41 | int mask; |
| 42 | − irq_handler_t handler; | |
| 43 | − void *handler_data; | |
| 44 | 42 | }; |
| 45 | 43 | |
| 46 | 44 | static struct wm831x_irq_data wm831x_irqs[] = { |
| @@ -492,6 +490,14 @@ int wm831x_irq_init(struct wm831x *wm831x, int irq) · 445 unmodified lines | ||
| 492 | 490 | |
| 493 | 491 | mutex_init(&wm831x->irq_lock); |
| 494 | 492 | |
| 493 | + /* Mask the individual interrupt sources */ | |
| 494 | + for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { | |
| 495 | + wm831x->irq_masks_cur[i] = 0xffff; | |
| 496 | + wm831x->irq_masks_cache[i] = 0xffff; | |
| 497 | + wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i, | |
| 498 | + 0xffff); | |
| 499 | + } | |
| 500 | + | |
| 495 | 501 | if (!irq) { |
| 496 | 502 | dev_warn(wm831x->dev, |
| 497 | 503 | "No interrupt specified - functionality limited\n"); |
| @@ -507,14 +513,6 @@ int wm831x_irq_init(struct wm831x *wm831x, int irq) · 9 unmodified lines | ||
| 507 | 513 | wm831x->irq = irq; |
| 508 | 514 | wm831x->irq_base = pdata->irq_base; |
| 509 | 515 | |
| 510 | − /* Mask the individual interrupt sources */ | |
| 511 | − for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) { | |
| 512 | − wm831x->irq_masks_cur[i] = 0xffff; | |
| 513 | − wm831x->irq_masks_cache[i] = 0xffff; | |
| 514 | − wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i, | |
| 515 | − 0xffff); | |
| 516 | − } | |
| 517 | − | |
| 518 | 516 | /* Register them with genirq */ |
| 519 | 517 | for (cur_irq = wm831x->irq_base; |
| 520 | 518 | cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base; |
| @@ -64,10 +64,8 @@ static int wm8350_i2c_probe(struct i2c_client *i2c, · 63 unmodified lines | ||
| 64 | 64 | int ret = 0; |
| 65 | 65 | |
| 66 | 66 | wm8350 = kzalloc(sizeof(struct wm8350), GFP_KERNEL); |
| 67 | − if (wm8350 == NULL) { | |
| 68 | − kfree(i2c); | |
| 67 | + if (wm8350 == NULL) | |
| 69 | 68 | return -ENOMEM; |
| 70 | − } | |
| 71 | 69 | |
| 72 | 70 | i2c_set_clientdata(i2c, wm8350); |
| 73 | 71 | wm8350->dev = &i2c->dev; |
| @@ -82,6 +80,7 @@ static int wm8350_i2c_probe(struct i2c_client *i2c, · 8 unmodified lines | ||
| 82 | 80 | return ret; |
| 83 | 81 | |
| 84 | 82 | err: |
| 83 | + i2c_set_clientdata(i2c, NULL); | |
| 85 | 84 | kfree(wm8350); |
| 86 | 85 | return ret; |
| 87 | 86 | } |
| @@ -91,6 +90,7 @@ static int wm8350_i2c_remove(struct i2c_client *i2c) · 3 unmodified lines | ||
| 91 | 90 | struct wm8350 *wm8350 = i2c_get_clientdata(i2c); |
| 92 | 91 | |
| 93 | 92 | wm8350_device_exit(wm8350); |
| 93 | + i2c_set_clientdata(i2c, NULL); | |
| 94 | 94 | kfree(wm8350); |
| 95 | 95 | |
| 96 | 96 | return 0; |
| @@ -118,7 +118,7 @@ static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest) · 117 unmodified lines | ||
| 118 | 118 | { |
| 119 | 119 | int i, ret = 0; |
| 120 | 120 | |
| 121 | − BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache)); | |
| 121 | + BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache)); | |
| 122 | 122 | |
| 123 | 123 | /* If there are any volatile reads then read back the entire block */ |
| 124 | 124 | for (i = reg; i < reg + num_regs; i++) |
| @@ -144,7 +144,7 @@ static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs, · 19 unmodified lines | ||
| 144 | 144 | { |
| 145 | 145 | int ret, i; |
| 146 | 146 | |
| 147 | − BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache)); | |
| 147 | + BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache)); | |
| 148 | 148 | |
| 149 | 149 | for (i = 0; i < num_regs; i++) { |
| 150 | 150 | BUG_ON(!reg_data[reg + i].writable); |
| @@ -63,6 +63,16 @@ config CAN_BFIN · 62 unmodified lines | ||
| 63 | 63 | To compile this driver as a module, choose M here: the |
| 64 | 64 | module will be called bfin_can. |
| 65 | 65 | |
| 66 | +config CAN_JANZ_ICAN3 | |
| 67 | + tristate "Janz VMOD-ICAN3 Intelligent CAN controller" | |
| 68 | + depends on CAN_DEV && MFD_JANZ_CMODIO | |
| 69 | + ---help--- | |
| 70 | + Driver for Janz VMOD-ICAN3 Intelligent CAN controller module, which | |
| 71 | + connects to a MODULbus carrier board. | |
| 72 | + | |
| 73 | + This driver can also be built as a module. If so, the module will be | |
| 74 | + called janz-ican3.ko. | |
| 75 | + | |
| 66 | 76 | source "drivers/net/can/mscan/Kconfig" |
| 67 | 77 | |
| 68 | 78 | source "drivers/net/can/sja1000/Kconfig" |
| @@ -15,5 +15,6 @@ obj-$(CONFIG_CAN_AT91) += at91_can.o · 14 unmodified lines | ||
| 15 | 15 | obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o |
| 16 | 16 | obj-$(CONFIG_CAN_MCP251X) += mcp251x.o |
| 17 | 17 | obj-$(CONFIG_CAN_BFIN) += bfin_can.o |
| 18 | +obj-$(CONFIG_CAN_JANZ_ICAN3) += janz-ican3.o | |
| 18 | 19 | |
| 19 | 20 | ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG |
| @@ -0,0 +1,1830 @@ | ||
| 1 | +/* | |
| 2 | + * Janz MODULbus VMOD-ICAN3 CAN Interface Driver | |
| 3 | + * | |
| 4 | + * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu> | |
| 5 | + * | |
| 6 | + * This program is free software; you can redistribute it and/or modify it | |
| 7 | + * under the terms of the GNU General Public License as published by the | |
| 8 | + * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | + * option) any later version. | |
| 10 | + */ | |
| 11 | + | |
| 12 | +#include <linux/kernel.h> | |
| 13 | +#include <linux/module.h> | |
| 14 | +#include <linux/init.h> | |
| 15 | +#include <linux/interrupt.h> | |
| 16 | +#include <linux/delay.h> | |
| 17 | +#include <linux/platform_device.h> | |
| 18 | + | |
| 19 | +#include <linux/netdevice.h> | |
| 20 | +#include <linux/can.h> | |
| 21 | +#include <linux/can/dev.h> | |
| 22 | +#include <linux/can/error.h> | |
| 23 | + | |
| 24 | +#include <linux/mfd/janz.h> | |
| 25 | + | |
| 26 | +/* the DPM has 64k of memory, organized into 256x 256 byte pages */ | |
| 27 | +#define DPM_NUM_PAGES 256 | |
| 28 | +#define DPM_PAGE_SIZE 256 | |
| 29 | +#define DPM_PAGE_ADDR(p) ((p) * DPM_PAGE_SIZE) | |
| 30 | + | |
| 31 | +/* JANZ ICAN3 "old-style" host interface queue page numbers */ | |
| 32 | +#define QUEUE_OLD_CONTROL 0 | |
| 33 | +#define QUEUE_OLD_RB0 1 | |
| 34 | +#define QUEUE_OLD_RB1 2 | |
| 35 | +#define QUEUE_OLD_WB0 3 | |
| 36 | +#define QUEUE_OLD_WB1 4 | |
| 37 | + | |
| 38 | +/* Janz ICAN3 "old-style" host interface control registers */ | |
| 39 | +#define MSYNC_PEER 0x00 /* ICAN only */ | |
| 40 | +#define MSYNC_LOCL 0x01 /* host only */ | |
| 41 | +#define TARGET_RUNNING 0x02 | |
| 42 | + | |
| 43 | +#define MSYNC_RB0 0x01 | |
| 44 | +#define MSYNC_RB1 0x02 | |
| 45 | +#define MSYNC_RBLW 0x04 | |
| 46 | +#define MSYNC_RB_MASK (MSYNC_RB0 | MSYNC_RB1) | |
| 47 | + | |
| 48 | +#define MSYNC_WB0 0x10 | |
| 49 | +#define MSYNC_WB1 0x20 | |
| 50 | +#define MSYNC_WBLW 0x40 | |
| 51 | +#define MSYNC_WB_MASK (MSYNC_WB0 | MSYNC_WB1) | |
| 52 | + | |
| 53 | +/* Janz ICAN3 "new-style" host interface queue page numbers */ | |
| 54 | +#define QUEUE_TOHOST 5 | |
| 55 | +#define QUEUE_FROMHOST_MID 6 | |
| 56 | +#define QUEUE_FROMHOST_HIGH 7 | |
| 57 | +#define QUEUE_FROMHOST_LOW 8 | |
| 58 | + | |
| 59 | +/* The first free page in the DPM is #9 */ | |
| 60 | +#define DPM_FREE_START 9 | |
| 61 | + | |
| 62 | +/* Janz ICAN3 "new-style" and "fast" host interface descriptor flags */ | |
| 63 | +#define DESC_VALID 0x80 | |
| 64 | +#define DESC_WRAP 0x40 | |
| 65 | +#define DESC_INTERRUPT 0x20 | |
| 66 | +#define DESC_IVALID 0x10 | |
| 67 | +#define DESC_LEN(len) (len) | |
| 68 | + | |
| 69 | +/* Janz ICAN3 Firmware Messages */ | |
| 70 | +#define MSG_CONNECTI 0x02 | |
| 71 | +#define MSG_DISCONNECT 0x03 | |
| 72 | +#define MSG_IDVERS 0x04 | |
| 73 | +#define MSG_MSGLOST 0x05 | |
| 74 | +#define MSG_NEWHOSTIF 0x08 | |
| 75 | +#define MSG_INQUIRY 0x0a | |
| 76 | +#define MSG_SETAFILMASK 0x10 | |
| 77 | +#define MSG_INITFDPMQUEUE 0x11 | |
| 78 | +#define MSG_HWCONF 0x12 | |
| 79 | +#define MSG_FMSGLOST 0x15 | |
| 80 | +#define MSG_CEVTIND 0x37 | |
| 81 | +#define MSG_CBTRREQ 0x41 | |
| 82 | +#define MSG_COFFREQ 0x42 | |
| 83 | +#define MSG_CONREQ 0x43 | |
| 84 | +#define MSG_CCONFREQ 0x47 | |
| 85 | + | |
| 86 | +/* | |
| 87 | + * Janz ICAN3 CAN Inquiry Message Types | |
| 88 | + * | |
| 89 | + * NOTE: there appears to be a firmware bug here. You must send | |
| 90 | + * NOTE: INQUIRY_STATUS and expect to receive an INQUIRY_EXTENDED | |
| 91 | + * NOTE: response. The controller never responds to a message with | |
| 92 | + * NOTE: the INQUIRY_EXTENDED subspec :( | |
| 93 | + */ | |
| 94 | +#define INQUIRY_STATUS 0x00 | |
| 95 | +#define INQUIRY_TERMINATION 0x01 | |
| 96 | +#define INQUIRY_EXTENDED 0x04 | |
| 97 | + | |
| 98 | +/* Janz ICAN3 CAN Set Acceptance Filter Mask Message Types */ | |
| 99 | +#define SETAFILMASK_REJECT 0x00 | |
| 100 | +#define SETAFILMASK_FASTIF 0x02 | |
| 101 | + | |
| 102 | +/* Janz ICAN3 CAN Hardware Configuration Message Types */ | |
| 103 | +#define HWCONF_TERMINATE_ON 0x01 | |
| 104 | +#define HWCONF_TERMINATE_OFF 0x00 | |
| 105 | + | |
| 106 | +/* Janz ICAN3 CAN Event Indication Message Types */ | |
| 107 | +#define CEVTIND_EI 0x01 | |
| 108 | +#define CEVTIND_DOI 0x02 | |
| 109 | +#define CEVTIND_LOST 0x04 | |
| 110 | +#define CEVTIND_FULL 0x08 | |
| 111 | +#define CEVTIND_BEI 0x10 | |
| 112 | + | |
| 113 | +#define CEVTIND_CHIP_SJA1000 0x02 | |
| 114 | + | |
| 115 | +#define ICAN3_BUSERR_QUOTA_MAX 255 | |
| 116 | + | |
| 117 | +/* Janz ICAN3 CAN Frame Conversion */ | |
| 118 | +#define ICAN3_ECHO 0x10 | |
| 119 | +#define ICAN3_EFF_RTR 0x40 | |
| 120 | +#define ICAN3_SFF_RTR 0x10 | |
| 121 | +#define ICAN3_EFF 0x80 | |
| 122 | + | |
| 123 | +#define ICAN3_CAN_TYPE_MASK 0x0f | |
| 124 | +#define ICAN3_CAN_TYPE_SFF 0x00 | |
| 125 | +#define ICAN3_CAN_TYPE_EFF 0x01 | |
| 126 | + | |
| 127 | +#define ICAN3_CAN_DLC_MASK 0x0f | |
| 128 | + | |
| 129 | +/* | |
| 130 | + * SJA1000 Status and Error Register Definitions | |
| 131 | + * | |
| 132 | + * Copied from drivers/net/can/sja1000/sja1000.h | |
| 133 | + */ | |
| 134 | + | |
| 135 | +/* status register content */ | |
| 136 | +#define SR_BS 0x80 | |
| 137 | +#define SR_ES 0x40 | |
| 138 | +#define SR_TS 0x20 | |
| 139 | +#define SR_RS 0x10 | |
| 140 | +#define SR_TCS 0x08 | |
| 141 | +#define SR_TBS 0x04 | |
| 142 | +#define SR_DOS 0x02 | |
| 143 | +#define SR_RBS 0x01 | |
| 144 | + | |
| 145 | +#define SR_CRIT (SR_BS|SR_ES) | |
| 146 | + | |
| 147 | +/* ECC register */ | |
| 148 | +#define ECC_SEG 0x1F | |
| 149 | +#define ECC_DIR 0x20 | |
| 150 | +#define ECC_ERR 6 | |
| 151 | +#define ECC_BIT 0x00 | |
| 152 | +#define ECC_FORM 0x40 | |
| 153 | +#define ECC_STUFF 0x80 | |
| 154 | +#define ECC_MASK 0xc0 | |
| 155 | + | |
| 156 | +/* Number of buffers for use in the "new-style" host interface */ | |
| 157 | +#define ICAN3_NEW_BUFFERS 16 | |
| 158 | + | |
| 159 | +/* Number of buffers for use in the "fast" host interface */ | |
| 160 | +#define ICAN3_TX_BUFFERS 512 | |
| 161 | +#define ICAN3_RX_BUFFERS 1024 | |
| 162 | + | |
| 163 | +/* SJA1000 Clock Input */ | |
| 164 | +#define ICAN3_CAN_CLOCK 8000000 | |
| 165 | + | |
| 166 | +/* Driver Name */ | |
| 167 | +#define DRV_NAME "janz-ican3" | |
| 168 | + | |
| 169 | +/* DPM Control Registers -- starts at offset 0x100 in the MODULbus registers */ | |
| 170 | +struct ican3_dpm_control { | |
| 171 | + /* window address register */ | |
| 172 | + u8 window_address; | |
| 173 | + u8 unused1; | |
| 174 | + | |
| 175 | + /* | |
| 176 | + * Read access: clear interrupt from microcontroller | |
| 177 | + * Write access: send interrupt to microcontroller | |
| 178 | + */ | |
| 179 | + u8 interrupt; | |
| 180 | + u8 unused2; | |
| 181 | + | |
| 182 | + /* write-only: reset all hardware on the module */ | |
| 183 | + u8 hwreset; | |
| 184 | + u8 unused3; | |
| 185 | + | |
| 186 | + /* write-only: generate an interrupt to the TPU */ | |
| 187 | + u8 tpuinterrupt; | |
| 188 | +}; | |
| 189 | + | |
| 190 | +struct ican3_dev { | |
| 191 | + | |
| 192 | + /* must be the first member */ | |
| 193 | + struct can_priv can; | |
| 194 | + | |
| 195 | + /* CAN network device */ | |
| 196 | + struct net_device *ndev; | |
| 197 | + struct napi_struct napi; | |
| 198 | + | |
| 199 | + /* Device for printing */ | |
| 200 | + struct device *dev; | |
| 201 | + | |
| 202 | + /* module number */ | |
| 203 | + unsigned int num; | |
| 204 | + | |
| 205 | + /* base address of registers and IRQ */ | |
| 206 | + struct janz_cmodio_onboard_regs __iomem *ctrl; | |
| 207 | + struct ican3_dpm_control __iomem *dpmctrl; | |
| 208 | + void __iomem *dpm; | |
| 209 | + int irq; | |
| 210 | + | |
| 211 | + /* CAN bus termination status */ | |
| 212 | + struct completion termination_comp; | |
| 213 | + bool termination_enabled; | |
| 214 | + | |
| 215 | + /* CAN bus error status registers */ | |
| 216 | + struct completion buserror_comp; | |
| 217 | + struct can_berr_counter bec; | |
| 218 | + | |
| 219 | + /* old and new style host interface */ | |
| 220 | + unsigned int iftype; | |
| 221 | + | |
| 222 | + /* | |
| 223 | + * Any function which changes the current DPM page must hold this | |
| 224 | + * lock while it is performing data accesses. This ensures that the | |
| 225 | + * function will not be preempted and end up reading data from a | |
| 226 | + * different DPM page than it expects. | |
| 227 | + */ | |
| 228 | + spinlock_t lock; | |
| 229 | + | |
| 230 | + /* new host interface */ | |
| 231 | + unsigned int rx_int; | |
| 232 | + unsigned int rx_num; | |
| 233 | + unsigned int tx_num; | |
| 234 | + | |
| 235 | + /* fast host interface */ | |
| 236 | + unsigned int fastrx_start; | |
| 237 | + unsigned int fastrx_int; | |
| 238 | + unsigned int fastrx_num; | |
| 239 | + unsigned int fasttx_start; | |
| 240 | + unsigned int fasttx_num; | |
| 241 | + | |
| 242 | + /* first free DPM page */ | |
| 243 | + unsigned int free_page; | |
| 244 | +}; | |
| 245 | + | |
| 246 | +struct ican3_msg { | |
| 247 | + u8 control; | |
| 248 | + u8 spec; | |
| 249 | + __le16 len; | |
| 250 | + u8 data[252]; | |
| 251 | +}; | |
| 252 | + | |
| 253 | +struct ican3_new_desc { | |
| 254 | + u8 control; | |
| 255 | + u8 pointer; | |
| 256 | +}; | |
| 257 | + | |
| 258 | +struct ican3_fast_desc { | |
| 259 | + u8 control; | |
| 260 | + u8 command; | |
| 261 | + u8 data[14]; | |
| 262 | +}; | |
| 263 | + | |
| 264 | +/* write to the window basic address register */ | |
| 265 | +static inline void ican3_set_page(struct ican3_dev *mod, unsigned int page) | |
| 266 | +{ | |
| 267 | + BUG_ON(page >= DPM_NUM_PAGES); | |
| 268 | + iowrite8(page, &mod->dpmctrl->window_address); | |
| 269 | +} | |
| 270 | + | |
| 271 | +/* | |
| 272 | + * ICAN3 "old-style" host interface | |
| 273 | + */ | |
| 274 | + | |
| 275 | +/* | |
| 276 | + * Recieve a message from the ICAN3 "old-style" firmware interface | |
| 277 | + * | |
| 278 | + * LOCKING: must hold mod->lock | |
| 279 | + * | |
| 280 | + * returns 0 on success, -ENOMEM when no message exists | |
| 281 | + */ | |
| 282 | +static int ican3_old_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 283 | +{ | |
| 284 | + unsigned int mbox, mbox_page; | |
| 285 | + u8 locl, peer, xord; | |
| 286 | + | |
| 287 | + /* get the MSYNC registers */ | |
| 288 | + ican3_set_page(mod, QUEUE_OLD_CONTROL); | |
| 289 | + peer = ioread8(mod->dpm + MSYNC_PEER); | |
| 290 | + locl = ioread8(mod->dpm + MSYNC_LOCL); | |
| 291 | + xord = locl ^ peer; | |
| 292 | + | |
| 293 | + if ((xord & MSYNC_RB_MASK) == 0x00) { | |
| 294 | + dev_dbg(mod->dev, "no mbox for reading\n"); | |
| 295 | + return -ENOMEM; | |
| 296 | + } | |
| 297 | + | |
| 298 | + /* find the first free mbox to read */ | |
| 299 | + if ((xord & MSYNC_RB_MASK) == MSYNC_RB_MASK) | |
| 300 | + mbox = (xord & MSYNC_RBLW) ? MSYNC_RB0 : MSYNC_RB1; | |
| 301 | + else | |
| 302 | + mbox = (xord & MSYNC_RB0) ? MSYNC_RB0 : MSYNC_RB1; | |
| 303 | + | |
| 304 | + /* copy the message */ | |
| 305 | + mbox_page = (mbox == MSYNC_RB0) ? QUEUE_OLD_RB0 : QUEUE_OLD_RB1; | |
| 306 | + ican3_set_page(mod, mbox_page); | |
| 307 | + memcpy_fromio(msg, mod->dpm, sizeof(*msg)); | |
| 308 | + | |
| 309 | + /* | |
| 310 | + * notify the firmware that the read buffer is available | |
| 311 | + * for it to fill again | |
| 312 | + */ | |
| 313 | + locl ^= mbox; | |
| 314 | + | |
| 315 | + ican3_set_page(mod, QUEUE_OLD_CONTROL); | |
| 316 | + iowrite8(locl, mod->dpm + MSYNC_LOCL); | |
| 317 | + return 0; | |
| 318 | +} | |
| 319 | + | |
| 320 | +/* | |
| 321 | + * Send a message through the "old-style" firmware interface | |
| 322 | + * | |
| 323 | + * LOCKING: must hold mod->lock | |
| 324 | + * | |
| 325 | + * returns 0 on success, -ENOMEM when no free space exists | |
| 326 | + */ | |
| 327 | +static int ican3_old_send_msg(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 328 | +{ | |
| 329 | + unsigned int mbox, mbox_page; | |
| 330 | + u8 locl, peer, xord; | |
| 331 | + | |
| 332 | + /* get the MSYNC registers */ | |
| 333 | + ican3_set_page(mod, QUEUE_OLD_CONTROL); | |
| 334 | + peer = ioread8(mod->dpm + MSYNC_PEER); | |
| 335 | + locl = ioread8(mod->dpm + MSYNC_LOCL); | |
| 336 | + xord = locl ^ peer; | |
| 337 | + | |
| 338 | + if ((xord & MSYNC_WB_MASK) == MSYNC_WB_MASK) { | |
| 339 | + dev_err(mod->dev, "no mbox for writing\n"); | |
| 340 | + return -ENOMEM; | |
| 341 | + } | |
| 342 | + | |
| 343 | + /* calculate a free mbox to use */ | |
| 344 | + mbox = (xord & MSYNC_WB0) ? MSYNC_WB1 : MSYNC_WB0; | |
| 345 | + | |
| 346 | + /* copy the message to the DPM */ | |
| 347 | + mbox_page = (mbox == MSYNC_WB0) ? QUEUE_OLD_WB0 : QUEUE_OLD_WB1; | |
| 348 | + ican3_set_page(mod, mbox_page); | |
| 349 | + memcpy_toio(mod->dpm, msg, sizeof(*msg)); | |
| 350 | + | |
| 351 | + locl ^= mbox; | |
| 352 | + if (mbox == MSYNC_WB1) | |
| 353 | + locl |= MSYNC_WBLW; | |
| 354 | + | |
| 355 | + ican3_set_page(mod, QUEUE_OLD_CONTROL); | |
| 356 | + iowrite8(locl, mod->dpm + MSYNC_LOCL); | |
| 357 | + return 0; | |
| 358 | +} | |
| 359 | + | |
| 360 | +/* | |
| 361 | + * ICAN3 "new-style" Host Interface Setup | |
| 362 | + */ | |
| 363 | + | |
| 364 | +static void __devinit ican3_init_new_host_interface(struct ican3_dev *mod) | |
| 365 | +{ | |
| 366 | + struct ican3_new_desc desc; | |
| 367 | + unsigned long flags; | |
| 368 | + void __iomem *dst; | |
| 369 | + int i; | |
| 370 | + | |
| 371 | + spin_lock_irqsave(&mod->lock, flags); | |
| 372 | + | |
| 373 | + /* setup the internal datastructures for RX */ | |
| 374 | + mod->rx_num = 0; | |
| 375 | + mod->rx_int = 0; | |
| 376 | + | |
| 377 | + /* tohost queue descriptors are in page 5 */ | |
| 378 | + ican3_set_page(mod, QUEUE_TOHOST); | |
| 379 | + dst = mod->dpm; | |
| 380 | + | |
| 381 | + /* initialize the tohost (rx) queue descriptors: pages 9-24 */ | |
| 382 | + for (i = 0; i < ICAN3_NEW_BUFFERS; i++) { | |
| 383 | + desc.control = DESC_INTERRUPT | DESC_LEN(1); /* I L=1 */ | |
| 384 | + desc.pointer = mod->free_page; | |
| 385 | + | |
| 386 | + /* set wrap flag on last buffer */ | |
| 387 | + if (i == ICAN3_NEW_BUFFERS - 1) | |
| 388 | + desc.control |= DESC_WRAP; | |
| 389 | + | |
| 390 | + memcpy_toio(dst, &desc, sizeof(desc)); | |
| 391 | + dst += sizeof(desc); | |
| 392 | + mod->free_page++; | |
| 393 | + } | |
| 394 | + | |
| 395 | + /* fromhost (tx) mid queue descriptors are in page 6 */ | |
| 396 | + ican3_set_page(mod, QUEUE_FROMHOST_MID); | |
| 397 | + dst = mod->dpm; | |
| 398 | + | |
| 399 | + /* setup the internal datastructures for TX */ | |
| 400 | + mod->tx_num = 0; | |
| 401 | + | |
| 402 | + /* initialize the fromhost mid queue descriptors: pages 25-40 */ | |
| 403 | + for (i = 0; i < ICAN3_NEW_BUFFERS; i++) { | |
| 404 | + desc.control = DESC_VALID | DESC_LEN(1); /* V L=1 */ | |
| 405 | + desc.pointer = mod->free_page; | |
| 406 | + | |
| 407 | + /* set wrap flag on last buffer */ | |
| 408 | + if (i == ICAN3_NEW_BUFFERS - 1) | |
| 409 | + desc.control |= DESC_WRAP; | |
| 410 | + | |
| 411 | + memcpy_toio(dst, &desc, sizeof(desc)); | |
| 412 | + dst += sizeof(desc); | |
| 413 | + mod->free_page++; | |
| 414 | + } | |
| 415 | + | |
| 416 | + /* fromhost hi queue descriptors are in page 7 */ | |
| 417 | + ican3_set_page(mod, QUEUE_FROMHOST_HIGH); | |
| 418 | + dst = mod->dpm; | |
| 419 | + | |
| 420 | + /* initialize only a single buffer in the fromhost hi queue (unused) */ | |
| 421 | + desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */ | |
| 422 | + desc.pointer = mod->free_page; | |
| 423 | + memcpy_toio(dst, &desc, sizeof(desc)); | |
| 424 | + mod->free_page++; | |
| 425 | + | |
| 426 | + /* fromhost low queue descriptors are in page 8 */ | |
| 427 | + ican3_set_page(mod, QUEUE_FROMHOST_LOW); | |
| 428 | + dst = mod->dpm; | |
| 429 | + | |
| 430 | + /* initialize only a single buffer in the fromhost low queue (unused) */ | |
| 431 | + desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */ | |
| 432 | + desc.pointer = mod->free_page; | |
| 433 | + memcpy_toio(dst, &desc, sizeof(desc)); | |
| 434 | + mod->free_page++; | |
| 435 | + | |
| 436 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 437 | +} | |
| 438 | + | |
| 439 | +/* | |
| 440 | + * ICAN3 Fast Host Interface Setup | |
| 441 | + */ | |
| 442 | + | |
| 443 | +static void __devinit ican3_init_fast_host_interface(struct ican3_dev *mod) | |
| 444 | +{ | |
| 445 | + struct ican3_fast_desc desc; | |
| 446 | + unsigned long flags; | |
| 447 | + unsigned int addr; | |
| 448 | + void __iomem *dst; | |
| 449 | + int i; | |
| 450 | + | |
| 451 | + spin_lock_irqsave(&mod->lock, flags); | |
| 452 | + | |
| 453 | + /* save the start recv page */ | |
| 454 | + mod->fastrx_start = mod->free_page; | |
| 455 | + mod->fastrx_num = 0; | |
| 456 | + mod->fastrx_int = 0; | |
| 457 | + | |
| 458 | + /* build a single fast tohost queue descriptor */ | |
| 459 | + memset(&desc, 0, sizeof(desc)); | |
| 460 | + desc.control = 0x00; | |
| 461 | + desc.command = 1; | |
| 462 | + | |
| 463 | + /* build the tohost queue descriptor ring in memory */ | |
| 464 | + addr = 0; | |
| 465 | + for (i = 0; i < ICAN3_RX_BUFFERS; i++) { | |
| 466 | + | |
| 467 | + /* set the wrap bit on the last buffer */ | |
| 468 | + if (i == ICAN3_RX_BUFFERS - 1) | |
| 469 | + desc.control |= DESC_WRAP; | |
| 470 | + | |
| 471 | + /* switch to the correct page */ | |
| 472 | + ican3_set_page(mod, mod->free_page); | |
| 473 | + | |
| 474 | + /* copy the descriptor to the DPM */ | |
| 475 | + dst = mod->dpm + addr; | |
| 476 | + memcpy_toio(dst, &desc, sizeof(desc)); | |
| 477 | + addr += sizeof(desc); | |
| 478 | + | |
| 479 | + /* move to the next page if necessary */ | |
| 480 | + if (addr >= DPM_PAGE_SIZE) { | |
| 481 | + addr = 0; | |
| 482 | + mod->free_page++; | |
| 483 | + } | |
| 484 | + } | |
| 485 | + | |
| 486 | + /* make sure we page-align the next queue */ | |
| 487 | + if (addr != 0) | |
| 488 | + mod->free_page++; | |
| 489 | + | |
| 490 | + /* save the start xmit page */ | |
| 491 | + mod->fasttx_start = mod->free_page; | |
| 492 | + mod->fasttx_num = 0; | |
| 493 | + | |
| 494 | + /* build a single fast fromhost queue descriptor */ | |
| 495 | + memset(&desc, 0, sizeof(desc)); | |
| 496 | + desc.control = DESC_VALID; | |
| 497 | + desc.command = 1; | |
| 498 | + | |
| 499 | + /* build the fromhost queue descriptor ring in memory */ | |
| 500 | + addr = 0; | |
| 501 | + for (i = 0; i < ICAN3_TX_BUFFERS; i++) { | |
| 502 | + | |
| 503 | + /* set the wrap bit on the last buffer */ | |
| 504 | + if (i == ICAN3_TX_BUFFERS - 1) | |
| 505 | + desc.control |= DESC_WRAP; | |
| 506 | + | |
| 507 | + /* switch to the correct page */ | |
| 508 | + ican3_set_page(mod, mod->free_page); | |
| 509 | + | |
| 510 | + /* copy the descriptor to the DPM */ | |
| 511 | + dst = mod->dpm + addr; | |
| 512 | + memcpy_toio(dst, &desc, sizeof(desc)); | |
| 513 | + addr += sizeof(desc); | |
| 514 | + | |
| 515 | + /* move to the next page if necessary */ | |
| 516 | + if (addr >= DPM_PAGE_SIZE) { | |
| 517 | + addr = 0; | |
| 518 | + mod->free_page++; | |
| 519 | + } | |
| 520 | + } | |
| 521 | + | |
| 522 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 523 | +} | |
| 524 | + | |
| 525 | +/* | |
| 526 | + * ICAN3 "new-style" Host Interface Message Helpers | |
| 527 | + */ | |
| 528 | + | |
| 529 | +/* | |
| 530 | + * LOCKING: must hold mod->lock | |
| 531 | + */ | |
| 532 | +static int ican3_new_send_msg(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 533 | +{ | |
| 534 | + struct ican3_new_desc desc; | |
| 535 | + void __iomem *desc_addr = mod->dpm + (mod->tx_num * sizeof(desc)); | |
| 536 | + | |
| 537 | + /* switch to the fromhost mid queue, and read the buffer descriptor */ | |
| 538 | + ican3_set_page(mod, QUEUE_FROMHOST_MID); | |
| 539 | + memcpy_fromio(&desc, desc_addr, sizeof(desc)); | |
| 540 | + | |
| 541 | + if (!(desc.control & DESC_VALID)) { | |
| 542 | + dev_dbg(mod->dev, "%s: no free buffers\n", __func__); | |
| 543 | + return -ENOMEM; | |
| 544 | + } | |
| 545 | + | |
| 546 | + /* switch to the data page, copy the data */ | |
| 547 | + ican3_set_page(mod, desc.pointer); | |
| 548 | + memcpy_toio(mod->dpm, msg, sizeof(*msg)); | |
| 549 | + | |
| 550 | + /* switch back to the descriptor, set the valid bit, write it back */ | |
| 551 | + ican3_set_page(mod, QUEUE_FROMHOST_MID); | |
| 552 | + desc.control ^= DESC_VALID; | |
| 553 | + memcpy_toio(desc_addr, &desc, sizeof(desc)); | |
| 554 | + | |
| 555 | + /* update the tx number */ | |
| 556 | + mod->tx_num = (desc.control & DESC_WRAP) ? 0 : (mod->tx_num + 1); | |
| 557 | + return 0; | |
| 558 | +} | |
| 559 | + | |
| 560 | +/* | |
| 561 | + * LOCKING: must hold mod->lock | |
| 562 | + */ | |
| 563 | +static int ican3_new_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 564 | +{ | |
| 565 | + struct ican3_new_desc desc; | |
| 566 | + void __iomem *desc_addr = mod->dpm + (mod->rx_num * sizeof(desc)); | |
| 567 | + | |
| 568 | + /* switch to the tohost queue, and read the buffer descriptor */ | |
| 569 | + ican3_set_page(mod, QUEUE_TOHOST); | |
| 570 | + memcpy_fromio(&desc, desc_addr, sizeof(desc)); | |
| 571 | + | |
| 572 | + if (!(desc.control & DESC_VALID)) { | |
| 573 | + dev_dbg(mod->dev, "%s: no buffers to recv\n", __func__); | |
| 574 | + return -ENOMEM; | |
| 575 | + } | |
| 576 | + | |
| 577 | + /* switch to the data page, copy the data */ | |
| 578 | + ican3_set_page(mod, desc.pointer); | |
| 579 | + memcpy_fromio(msg, mod->dpm, sizeof(*msg)); | |
| 580 | + | |
| 581 | + /* switch back to the descriptor, toggle the valid bit, write it back */ | |
| 582 | + ican3_set_page(mod, QUEUE_TOHOST); | |
| 583 | + desc.control ^= DESC_VALID; | |
| 584 | + memcpy_toio(desc_addr, &desc, sizeof(desc)); | |
| 585 | + | |
| 586 | + /* update the rx number */ | |
| 587 | + mod->rx_num = (desc.control & DESC_WRAP) ? 0 : (mod->rx_num + 1); | |
| 588 | + return 0; | |
| 589 | +} | |
| 590 | + | |
| 591 | +/* | |
| 592 | + * Message Send / Recv Helpers | |
| 593 | + */ | |
| 594 | + | |
| 595 | +static int ican3_send_msg(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 596 | +{ | |
| 597 | + unsigned long flags; | |
| 598 | + int ret; | |
| 599 | + | |
| 600 | + spin_lock_irqsave(&mod->lock, flags); | |
| 601 | + | |
| 602 | + if (mod->iftype == 0) | |
| 603 | + ret = ican3_old_send_msg(mod, msg); | |
| 604 | + else | |
| 605 | + ret = ican3_new_send_msg(mod, msg); | |
| 606 | + | |
| 607 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 608 | + return ret; | |
| 609 | +} | |
| 610 | + | |
| 611 | +static int ican3_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 612 | +{ | |
| 613 | + unsigned long flags; | |
| 614 | + int ret; | |
| 615 | + | |
| 616 | + spin_lock_irqsave(&mod->lock, flags); | |
| 617 | + | |
| 618 | + if (mod->iftype == 0) | |
| 619 | + ret = ican3_old_recv_msg(mod, msg); | |
| 620 | + else | |
| 621 | + ret = ican3_new_recv_msg(mod, msg); | |
| 622 | + | |
| 623 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 624 | + return ret; | |
| 625 | +} | |
| 626 | + | |
| 627 | +/* | |
| 628 | + * Quick Pre-constructed Messages | |
| 629 | + */ | |
| 630 | + | |
| 631 | +static int __devinit ican3_msg_connect(struct ican3_dev *mod) | |
| 632 | +{ | |
| 633 | + struct ican3_msg msg; | |
| 634 | + | |
| 635 | + memset(&msg, 0, sizeof(msg)); | |
| 636 | + msg.spec = MSG_CONNECTI; | |
| 637 | + msg.len = cpu_to_le16(0); | |
| 638 | + | |
| 639 | + return ican3_send_msg(mod, &msg); | |
| 640 | +} | |
| 641 | + | |
| 642 | +static int __devexit ican3_msg_disconnect(struct ican3_dev *mod) | |
| 643 | +{ | |
| 644 | + struct ican3_msg msg; | |
| 645 | + | |
| 646 | + memset(&msg, 0, sizeof(msg)); | |
| 647 | + msg.spec = MSG_DISCONNECT; | |
| 648 | + msg.len = cpu_to_le16(0); | |
| 649 | + | |
| 650 | + return ican3_send_msg(mod, &msg); | |
| 651 | +} | |
| 652 | + | |
| 653 | +static int __devinit ican3_msg_newhostif(struct ican3_dev *mod) | |
| 654 | +{ | |
| 655 | + struct ican3_msg msg; | |
| 656 | + int ret; | |
| 657 | + | |
| 658 | + memset(&msg, 0, sizeof(msg)); | |
| 659 | + msg.spec = MSG_NEWHOSTIF; | |
| 660 | + msg.len = cpu_to_le16(0); | |
| 661 | + | |
| 662 | + /* If we're not using the old interface, switching seems bogus */ | |
| 663 | + WARN_ON(mod->iftype != 0); | |
| 664 | + | |
| 665 | + ret = ican3_send_msg(mod, &msg); | |
| 666 | + if (ret) | |
| 667 | + return ret; | |
| 668 | + | |
| 669 | + /* mark the module as using the new host interface */ | |
| 670 | + mod->iftype = 1; | |
| 671 | + return 0; | |
| 672 | +} | |
| 673 | + | |
| 674 | +static int __devinit ican3_msg_fasthostif(struct ican3_dev *mod) | |
| 675 | +{ | |
| 676 | + struct ican3_msg msg; | |
| 677 | + unsigned int addr; | |
| 678 | + | |
| 679 | + memset(&msg, 0, sizeof(msg)); | |
| 680 | + msg.spec = MSG_INITFDPMQUEUE; | |
| 681 | + msg.len = cpu_to_le16(8); | |
| 682 | + | |
| 683 | + /* write the tohost queue start address */ | |
| 684 | + addr = DPM_PAGE_ADDR(mod->fastrx_start); | |
| 685 | + msg.data[0] = addr & 0xff; | |
| 686 | + msg.data[1] = (addr >> 8) & 0xff; | |
| 687 | + msg.data[2] = (addr >> 16) & 0xff; | |
| 688 | + msg.data[3] = (addr >> 24) & 0xff; | |
| 689 | + | |
| 690 | + /* write the fromhost queue start address */ | |
| 691 | + addr = DPM_PAGE_ADDR(mod->fasttx_start); | |
| 692 | + msg.data[4] = addr & 0xff; | |
| 693 | + msg.data[5] = (addr >> 8) & 0xff; | |
| 694 | + msg.data[6] = (addr >> 16) & 0xff; | |
| 695 | + msg.data[7] = (addr >> 24) & 0xff; | |
| 696 | + | |
| 697 | + /* If we're not using the new interface yet, we cannot do this */ | |
| 698 | + WARN_ON(mod->iftype != 1); | |
| 699 | + | |
| 700 | + return ican3_send_msg(mod, &msg); | |
| 701 | +} | |
| 702 | + | |
| 703 | +/* | |
| 704 | + * Setup the CAN filter to either accept or reject all | |
| 705 | + * messages from the CAN bus. | |
| 706 | + */ | |
| 707 | +static int __devinit ican3_set_id_filter(struct ican3_dev *mod, bool accept) | |
| 708 | +{ | |
| 709 | + struct ican3_msg msg; | |
| 710 | + int ret; | |
| 711 | + | |
| 712 | + /* Standard Frame Format */ | |
| 713 | + memset(&msg, 0, sizeof(msg)); | |
| 714 | + msg.spec = MSG_SETAFILMASK; | |
| 715 | + msg.len = cpu_to_le16(5); | |
| 716 | + msg.data[0] = 0x00; /* IDLo LSB */ | |
| 717 | + msg.data[1] = 0x00; /* IDLo MSB */ | |
| 718 | + msg.data[2] = 0xff; /* IDHi LSB */ | |
| 719 | + msg.data[3] = 0x07; /* IDHi MSB */ | |
| 720 | + | |
| 721 | + /* accept all frames for fast host if, or reject all frames */ | |
| 722 | + msg.data[4] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT; | |
| 723 | + | |
| 724 | + ret = ican3_send_msg(mod, &msg); | |
| 725 | + if (ret) | |
| 726 | + return ret; | |
| 727 | + | |
| 728 | + /* Extended Frame Format */ | |
| 729 | + memset(&msg, 0, sizeof(msg)); | |
| 730 | + msg.spec = MSG_SETAFILMASK; | |
| 731 | + msg.len = cpu_to_le16(13); | |
| 732 | + msg.data[0] = 0; /* MUX = 0 */ | |
| 733 | + msg.data[1] = 0x00; /* IDLo LSB */ | |
| 734 | + msg.data[2] = 0x00; | |
| 735 | + msg.data[3] = 0x00; | |
| 736 | + msg.data[4] = 0x20; /* IDLo MSB */ | |
| 737 | + msg.data[5] = 0xff; /* IDHi LSB */ | |
| 738 | + msg.data[6] = 0xff; | |
| 739 | + msg.data[7] = 0xff; | |
| 740 | + msg.data[8] = 0x3f; /* IDHi MSB */ | |
| 741 | + | |
| 742 | + /* accept all frames for fast host if, or reject all frames */ | |
| 743 | + msg.data[9] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT; | |
| 744 | + | |
| 745 | + return ican3_send_msg(mod, &msg); | |
| 746 | +} | |
| 747 | + | |
| 748 | +/* | |
| 749 | + * Bring the CAN bus online or offline | |
| 750 | + */ | |
| 751 | +static int ican3_set_bus_state(struct ican3_dev *mod, bool on) | |
| 752 | +{ | |
| 753 | + struct ican3_msg msg; | |
| 754 | + | |
| 755 | + memset(&msg, 0, sizeof(msg)); | |
| 756 | + msg.spec = on ? MSG_CONREQ : MSG_COFFREQ; | |
| 757 | + msg.len = cpu_to_le16(0); | |
| 758 | + | |
| 759 | + return ican3_send_msg(mod, &msg); | |
| 760 | +} | |
| 761 | + | |
| 762 | +static int ican3_set_termination(struct ican3_dev *mod, bool on) | |
| 763 | +{ | |
| 764 | + struct ican3_msg msg; | |
| 765 | + | |
| 766 | + memset(&msg, 0, sizeof(msg)); | |
| 767 | + msg.spec = MSG_HWCONF; | |
| 768 | + msg.len = cpu_to_le16(2); | |
| 769 | + msg.data[0] = 0x00; | |
| 770 | + msg.data[1] = on ? HWCONF_TERMINATE_ON : HWCONF_TERMINATE_OFF; | |
| 771 | + | |
| 772 | + return ican3_send_msg(mod, &msg); | |
| 773 | +} | |
| 774 | + | |
| 775 | +static int ican3_send_inquiry(struct ican3_dev *mod, u8 subspec) | |
| 776 | +{ | |
| 777 | + struct ican3_msg msg; | |
| 778 | + | |
| 779 | + memset(&msg, 0, sizeof(msg)); | |
| 780 | + msg.spec = MSG_INQUIRY; | |
| 781 | + msg.len = cpu_to_le16(2); | |
| 782 | + msg.data[0] = subspec; | |
| 783 | + msg.data[1] = 0x00; | |
| 784 | + | |
| 785 | + return ican3_send_msg(mod, &msg); | |
| 786 | +} | |
| 787 | + | |
| 788 | +static int ican3_set_buserror(struct ican3_dev *mod, u8 quota) | |
| 789 | +{ | |
| 790 | + struct ican3_msg msg; | |
| 791 | + | |
| 792 | + memset(&msg, 0, sizeof(msg)); | |
| 793 | + msg.spec = MSG_CCONFREQ; | |
| 794 | + msg.len = cpu_to_le16(2); | |
| 795 | + msg.data[0] = 0x00; | |
| 796 | + msg.data[1] = quota; | |
| 797 | + | |
| 798 | + return ican3_send_msg(mod, &msg); | |
| 799 | +} | |
| 800 | + | |
| 801 | +/* | |
| 802 | + * ICAN3 to Linux CAN Frame Conversion | |
| 803 | + */ | |
| 804 | + | |
| 805 | +static void ican3_to_can_frame(struct ican3_dev *mod, | |
| 806 | + struct ican3_fast_desc *desc, | |
| 807 | + struct can_frame *cf) | |
| 808 | +{ | |
| 809 | + if ((desc->command & ICAN3_CAN_TYPE_MASK) == ICAN3_CAN_TYPE_SFF) { | |
| 810 | + if (desc->data[1] & ICAN3_SFF_RTR) | |
| 811 | + cf->can_id |= CAN_RTR_FLAG; | |
| 812 | + | |
| 813 | + cf->can_id |= desc->data[0] << 3; | |
| 814 | + cf->can_id |= (desc->data[1] & 0xe0) >> 5; | |
| 815 | + cf->can_dlc = desc->data[1] & ICAN3_CAN_DLC_MASK; | |
| 816 | + memcpy(cf->data, &desc->data[2], sizeof(cf->data)); | |
| 817 | + } else { | |
| 818 | + cf->can_dlc = desc->data[0] & ICAN3_CAN_DLC_MASK; | |
| 819 | + if (desc->data[0] & ICAN3_EFF_RTR) | |
| 820 | + cf->can_id |= CAN_RTR_FLAG; | |
| 821 | + | |
| 822 | + if (desc->data[0] & ICAN3_EFF) { | |
| 823 | + cf->can_id |= CAN_EFF_FLAG; | |
| 824 | + cf->can_id |= desc->data[2] << 21; /* 28-21 */ | |
| 825 | + cf->can_id |= desc->data[3] << 13; /* 20-13 */ | |
| 826 | + cf->can_id |= desc->data[4] << 5; /* 12-5 */ | |
| 827 | + cf->can_id |= (desc->data[5] & 0xf8) >> 3; | |
| 828 | + } else { | |
| 829 | + cf->can_id |= desc->data[2] << 3; /* 10-3 */ | |
| 830 | + cf->can_id |= desc->data[3] >> 5; /* 2-0 */ | |
| 831 | + } | |
| 832 | + | |
| 833 | + memcpy(cf->data, &desc->data[6], sizeof(cf->data)); | |
| 834 | + } | |
| 835 | +} | |
| 836 | + | |
| 837 | +static void can_frame_to_ican3(struct ican3_dev *mod, | |
| 838 | + struct can_frame *cf, | |
| 839 | + struct ican3_fast_desc *desc) | |
| 840 | +{ | |
| 841 | + /* clear out any stale data in the descriptor */ | |
| 842 | + memset(desc->data, 0, sizeof(desc->data)); | |
| 843 | + | |
| 844 | + /* we always use the extended format, with the ECHO flag set */ | |
| 845 | + desc->command = ICAN3_CAN_TYPE_EFF; | |
| 846 | + desc->data[0] |= cf->can_dlc; | |
| 847 | + desc->data[1] |= ICAN3_ECHO; | |
| 848 | + | |
| 849 | + if (cf->can_id & CAN_RTR_FLAG) | |
| 850 | + desc->data[0] |= ICAN3_EFF_RTR; | |
| 851 | + | |
| 852 | + /* pack the id into the correct places */ | |
| 853 | + if (cf->can_id & CAN_EFF_FLAG) { | |
| 854 | + desc->data[0] |= ICAN3_EFF; | |
| 855 | + desc->data[2] = (cf->can_id & 0x1fe00000) >> 21; /* 28-21 */ | |
| 856 | + desc->data[3] = (cf->can_id & 0x001fe000) >> 13; /* 20-13 */ | |
| 857 | + desc->data[4] = (cf->can_id & 0x00001fe0) >> 5; /* 12-5 */ | |
| 858 | + desc->data[5] = (cf->can_id & 0x0000001f) << 3; /* 4-0 */ | |
| 859 | + } else { | |
| 860 | + desc->data[2] = (cf->can_id & 0x7F8) >> 3; /* bits 10-3 */ | |
| 861 | + desc->data[3] = (cf->can_id & 0x007) << 5; /* bits 2-0 */ | |
| 862 | + } | |
| 863 | + | |
| 864 | + /* copy the data bits into the descriptor */ | |
| 865 | + memcpy(&desc->data[6], cf->data, sizeof(cf->data)); | |
| 866 | +} | |
| 867 | + | |
| 868 | +/* | |
| 869 | + * Interrupt Handling | |
| 870 | + */ | |
| 871 | + | |
| 872 | +/* | |
| 873 | + * Handle an ID + Version message response from the firmware. We never generate | |
| 874 | + * this message in production code, but it is very useful when debugging to be | |
| 875 | + * able to display this message. | |
| 876 | + */ | |
| 877 | +static void ican3_handle_idvers(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 878 | +{ | |
| 879 | + dev_dbg(mod->dev, "IDVERS response: %s\n", msg->data); | |
| 880 | +} | |
| 881 | + | |
| 882 | +static void ican3_handle_msglost(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 883 | +{ | |
| 884 | + struct net_device *dev = mod->ndev; | |
| 885 | + struct net_device_stats *stats = &dev->stats; | |
| 886 | + struct can_frame *cf; | |
| 887 | + struct sk_buff *skb; | |
| 888 | + | |
| 889 | + /* | |
| 890 | + * Report that communication messages with the microcontroller firmware | |
| 891 | + * are being lost. These are never CAN frames, so we do not generate an | |
| 892 | + * error frame for userspace | |
| 893 | + */ | |
| 894 | + if (msg->spec == MSG_MSGLOST) { | |
| 895 | + dev_err(mod->dev, "lost %d control messages\n", msg->data[0]); | |
| 896 | + return; | |
| 897 | + } | |
| 898 | + | |
| 899 | + /* | |
| 900 | + * Oops, this indicates that we have lost messages in the fast queue, | |
| 901 | + * which are exclusively CAN messages. Our driver isn't reading CAN | |
| 902 | + * frames fast enough. | |
| 903 | + * | |
| 904 | + * We'll pretend that the SJA1000 told us that it ran out of buffer | |
| 905 | + * space, because there is not a better message for this. | |
| 906 | + */ | |
| 907 | + skb = alloc_can_err_skb(dev, &cf); | |
| 908 | + if (skb) { | |
| 909 | + cf->can_id |= CAN_ERR_CRTL; | |
| 910 | + cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
| 911 | + stats->rx_errors++; | |
| 912 | + stats->rx_bytes += cf->can_dlc; | |
| 913 | + netif_rx(skb); | |
| 914 | + } | |
| 915 | +} | |
| 916 | + | |
| 917 | +/* | |
| 918 | + * Handle CAN Event Indication Messages from the firmware | |
| 919 | + * | |
| 920 | + * The ICAN3 firmware provides the values of some SJA1000 registers when it | |
| 921 | + * generates this message. The code below is largely copied from the | |
| 922 | + * drivers/net/can/sja1000/sja1000.c file, and adapted as necessary | |
| 923 | + */ | |
| 924 | +static int ican3_handle_cevtind(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 925 | +{ | |
| 926 | + struct net_device *dev = mod->ndev; | |
| 927 | + struct net_device_stats *stats = &dev->stats; | |
| 928 | + enum can_state state = mod->can.state; | |
| 929 | + u8 status, isrc, rxerr, txerr; | |
| 930 | + struct can_frame *cf; | |
| 931 | + struct sk_buff *skb; | |
| 932 | + | |
| 933 | + /* we can only handle the SJA1000 part */ | |
| 934 | + if (msg->data[1] != CEVTIND_CHIP_SJA1000) { | |
| 935 | + dev_err(mod->dev, "unable to handle errors on non-SJA1000\n"); | |
| 936 | + return -ENODEV; | |
| 937 | + } | |
| 938 | + | |
| 939 | + /* check the message length for sanity */ | |
| 940 | + if (le16_to_cpu(msg->len) < 6) { | |
| 941 | + dev_err(mod->dev, "error message too short\n"); | |
| 942 | + return -EINVAL; | |
| 943 | + } | |
| 944 | + | |
| 945 | + skb = alloc_can_err_skb(dev, &cf); | |
| 946 | + if (skb == NULL) | |
| 947 | + return -ENOMEM; | |
| 948 | + | |
| 949 | + isrc = msg->data[0]; | |
| 950 | + status = msg->data[3]; | |
| 951 | + rxerr = msg->data[4]; | |
| 952 | + txerr = msg->data[5]; | |
| 953 | + | |
| 954 | + /* data overrun interrupt */ | |
| 955 | + if (isrc == CEVTIND_DOI || isrc == CEVTIND_LOST) { | |
| 956 | + dev_dbg(mod->dev, "data overrun interrupt\n"); | |
| 957 | + cf->can_id |= CAN_ERR_CRTL; | |
| 958 | + cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
| 959 | + stats->rx_over_errors++; | |
| 960 | + stats->rx_errors++; | |
| 961 | + } | |
| 962 | + | |
| 963 | + /* error warning + passive interrupt */ | |
| 964 | + if (isrc == CEVTIND_EI) { | |
| 965 | + dev_dbg(mod->dev, "error warning + passive interrupt\n"); | |
| 966 | + if (status & SR_BS) { | |
| 967 | + state = CAN_STATE_BUS_OFF; | |
| 968 | + cf->can_id |= CAN_ERR_BUSOFF; | |
| 969 | + can_bus_off(dev); | |
| 970 | + } else if (status & SR_ES) { | |
| 971 | + if (rxerr >= 128 || txerr >= 128) | |
| 972 | + state = CAN_STATE_ERROR_PASSIVE; | |
| 973 | + else | |
| 974 | + state = CAN_STATE_ERROR_WARNING; | |
| 975 | + } else { | |
| 976 | + state = CAN_STATE_ERROR_ACTIVE; | |
| 977 | + } | |
| 978 | + } | |
| 979 | + | |
| 980 | + /* bus error interrupt */ | |
| 981 | + if (isrc == CEVTIND_BEI) { | |
| 982 | + u8 ecc = msg->data[2]; | |
| 983 | + | |
| 984 | + dev_dbg(mod->dev, "bus error interrupt\n"); | |
| 985 | + mod->can.can_stats.bus_error++; | |
| 986 | + stats->rx_errors++; | |
| 987 | + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
| 988 | + | |
| 989 | + switch (ecc & ECC_MASK) { | |
| 990 | + case ECC_BIT: | |
| 991 | + cf->data[2] |= CAN_ERR_PROT_BIT; | |
| 992 | + break; | |
| 993 | + case ECC_FORM: | |
| 994 | + cf->data[2] |= CAN_ERR_PROT_FORM; | |
| 995 | + break; | |
| 996 | + case ECC_STUFF: | |
| 997 | + cf->data[2] |= CAN_ERR_PROT_STUFF; | |
| 998 | + break; | |
| 999 | + default: | |
| 1000 | + cf->data[2] |= CAN_ERR_PROT_UNSPEC; | |
| 1001 | + cf->data[3] = ecc & ECC_SEG; | |
| 1002 | + break; | |
| 1003 | + } | |
| 1004 | + | |
| 1005 | + if ((ecc & ECC_DIR) == 0) | |
| 1006 | + cf->data[2] |= CAN_ERR_PROT_TX; | |
| 1007 | + | |
| 1008 | + cf->data[6] = txerr; | |
| 1009 | + cf->data[7] = rxerr; | |
| 1010 | + } | |
| 1011 | + | |
| 1012 | + if (state != mod->can.state && (state == CAN_STATE_ERROR_WARNING || | |
| 1013 | + state == CAN_STATE_ERROR_PASSIVE)) { | |
| 1014 | + cf->can_id |= CAN_ERR_CRTL; | |
| 1015 | + if (state == CAN_STATE_ERROR_WARNING) { | |
| 1016 | + mod->can.can_stats.error_warning++; | |
| 1017 | + cf->data[1] = (txerr > rxerr) ? | |
| 1018 | + CAN_ERR_CRTL_TX_WARNING : | |
| 1019 | + CAN_ERR_CRTL_RX_WARNING; | |
| 1020 | + } else { | |
| 1021 | + mod->can.can_stats.error_passive++; | |
| 1022 | + cf->data[1] = (txerr > rxerr) ? | |
| 1023 | + CAN_ERR_CRTL_TX_PASSIVE : | |
| 1024 | + CAN_ERR_CRTL_RX_PASSIVE; | |
| 1025 | + } | |
| 1026 | + | |
| 1027 | + cf->data[6] = txerr; | |
| 1028 | + cf->data[7] = rxerr; | |
| 1029 | + } | |
| 1030 | + | |
| 1031 | + mod->can.state = state; | |
| 1032 | + stats->rx_errors++; | |
| 1033 | + stats->rx_bytes += cf->can_dlc; | |
| 1034 | + netif_rx(skb); | |
| 1035 | + return 0; | |
| 1036 | +} | |
| 1037 | + | |
| 1038 | +static void ican3_handle_inquiry(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 1039 | +{ | |
| 1040 | + switch (msg->data[0]) { | |
| 1041 | + case INQUIRY_STATUS: | |
| 1042 | + case INQUIRY_EXTENDED: | |
| 1043 | + mod->bec.rxerr = msg->data[5]; | |
| 1044 | + mod->bec.txerr = msg->data[6]; | |
| 1045 | + complete(&mod->buserror_comp); | |
| 1046 | + break; | |
| 1047 | + case INQUIRY_TERMINATION: | |
| 1048 | + mod->termination_enabled = msg->data[6] & HWCONF_TERMINATE_ON; | |
| 1049 | + complete(&mod->termination_comp); | |
| 1050 | + break; | |
| 1051 | + default: | |
| 1052 | + dev_err(mod->dev, "recieved an unknown inquiry response\n"); | |
| 1053 | + break; | |
| 1054 | + } | |
| 1055 | +} | |
| 1056 | + | |
| 1057 | +static void ican3_handle_unknown_message(struct ican3_dev *mod, | |
| 1058 | + struct ican3_msg *msg) | |
| 1059 | +{ | |
| 1060 | + dev_warn(mod->dev, "recieved unknown message: spec 0x%.2x length %d\n", | |
| 1061 | + msg->spec, le16_to_cpu(msg->len)); | |
| 1062 | +} | |
| 1063 | + | |
| 1064 | +/* | |
| 1065 | + * Handle a control message from the firmware | |
| 1066 | + */ | |
| 1067 | +static void ican3_handle_message(struct ican3_dev *mod, struct ican3_msg *msg) | |
| 1068 | +{ | |
| 1069 | + dev_dbg(mod->dev, "%s: modno %d spec 0x%.2x len %d bytes\n", __func__, | |
| 1070 | + mod->num, msg->spec, le16_to_cpu(msg->len)); | |
| 1071 | + | |
| 1072 | + switch (msg->spec) { | |
| 1073 | + case MSG_IDVERS: | |
| 1074 | + ican3_handle_idvers(mod, msg); | |
| 1075 | + break; | |
| 1076 | + case MSG_MSGLOST: | |
| 1077 | + case MSG_FMSGLOST: | |
| 1078 | + ican3_handle_msglost(mod, msg); | |
| 1079 | + break; | |
| 1080 | + case MSG_CEVTIND: | |
| 1081 | + ican3_handle_cevtind(mod, msg); | |
| 1082 | + break; | |
| 1083 | + case MSG_INQUIRY: | |
| 1084 | + ican3_handle_inquiry(mod, msg); | |
| 1085 | + break; | |
| 1086 | + default: | |
| 1087 | + ican3_handle_unknown_message(mod, msg); | |
| 1088 | + break; | |
| 1089 | + } | |
| 1090 | +} | |
| 1091 | + | |
| 1092 | +/* | |
| 1093 | + * Check that there is room in the TX ring to transmit another skb | |
| 1094 | + * | |
| 1095 | + * LOCKING: must hold mod->lock | |
| 1096 | + */ | |
| 1097 | +static bool ican3_txok(struct ican3_dev *mod) | |
| 1098 | +{ | |
| 1099 | + struct ican3_fast_desc __iomem *desc; | |
| 1100 | + u8 control; | |
| 1101 | + | |
| 1102 | + /* copy the control bits of the descriptor */ | |
| 1103 | + ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16)); | |
| 1104 | + desc = mod->dpm + ((mod->fasttx_num % 16) * sizeof(*desc)); | |
| 1105 | + control = ioread8(&desc->control); | |
| 1106 | + | |
| 1107 | + /* if the control bits are not valid, then we have no more space */ | |
| 1108 | + if (!(control & DESC_VALID)) | |
| 1109 | + return false; | |
| 1110 | + | |
| 1111 | + return true; | |
| 1112 | +} | |
| 1113 | + | |
| 1114 | +/* | |
| 1115 | + * Recieve one CAN frame from the hardware | |
| 1116 | + * | |
| 1117 | + * This works like the core of a NAPI function, but is intended to be called | |
| 1118 | + * from workqueue context instead. This driver already needs a workqueue to | |
| 1119 | + * process control messages, so we use the workqueue instead of using NAPI. | |
| 1120 | + * This was done to simplify locking. | |
| 1121 | + * | |
| 1122 | + * CONTEXT: must be called from user context | |
| 1123 | + */ | |
| 1124 | +static int ican3_recv_skb(struct ican3_dev *mod) | |
| 1125 | +{ | |
| 1126 | + struct net_device *ndev = mod->ndev; | |
| 1127 | + struct net_device_stats *stats = &ndev->stats; | |
| 1128 | + struct ican3_fast_desc desc; | |
| 1129 | + void __iomem *desc_addr; | |
| 1130 | + struct can_frame *cf; | |
| 1131 | + struct sk_buff *skb; | |
| 1132 | + unsigned long flags; | |
| 1133 | + | |
| 1134 | + spin_lock_irqsave(&mod->lock, flags); | |
| 1135 | + | |
| 1136 | + /* copy the whole descriptor */ | |
| 1137 | + ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16)); | |
| 1138 | + desc_addr = mod->dpm + ((mod->fastrx_num % 16) * sizeof(desc)); | |
| 1139 | + memcpy_fromio(&desc, desc_addr, sizeof(desc)); | |
| 1140 | + | |
| 1141 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 1142 | + | |
| 1143 | + /* check that we actually have a CAN frame */ | |
| 1144 | + if (!(desc.control & DESC_VALID)) | |
| 1145 | + return -ENOBUFS; | |
| 1146 | + | |
| 1147 | + /* allocate an skb */ | |
| 1148 | + skb = alloc_can_skb(ndev, &cf); | |
| 1149 | + if (unlikely(skb == NULL)) { | |
| 1150 | + stats->rx_dropped++; | |
| 1151 | + goto err_noalloc; | |
| 1152 | + } | |
| 1153 | + | |
| 1154 | + /* convert the ICAN3 frame into Linux CAN format */ | |
| 1155 | + ican3_to_can_frame(mod, &desc, cf); | |
| 1156 | + | |
| 1157 | + /* receive the skb, update statistics */ | |
| 1158 | + netif_receive_skb(skb); | |
| 1159 | + stats->rx_packets++; | |
| 1160 | + stats->rx_bytes += cf->can_dlc; | |
| 1161 | + | |
| 1162 | +err_noalloc: | |
| 1163 | + /* toggle the valid bit and return the descriptor to the ring */ | |
| 1164 | + desc.control ^= DESC_VALID; | |
| 1165 | + | |
| 1166 | + spin_lock_irqsave(&mod->lock, flags); | |
| 1167 | + | |
| 1168 | + ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16)); | |
| 1169 | + memcpy_toio(desc_addr, &desc, 1); | |
| 1170 | + | |
| 1171 | + /* update the next buffer pointer */ | |
| 1172 | + mod->fastrx_num = (desc.control & DESC_WRAP) ? 0 | |
| 1173 | + : (mod->fastrx_num + 1); | |
| 1174 | + | |
| 1175 | + /* there are still more buffers to process */ | |
| 1176 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 1177 | + return 0; | |
| 1178 | +} | |
| 1179 | + | |
| 1180 | +static int ican3_napi(struct napi_struct *napi, int budget) | |
| 1181 | +{ | |
| 1182 | + struct ican3_dev *mod = container_of(napi, struct ican3_dev, napi); | |
| 1183 | + struct ican3_msg msg; | |
| 1184 | + unsigned long flags; | |
| 1185 | + int received = 0; | |
| 1186 | + int ret; | |
| 1187 | + | |
| 1188 | + /* process all communication messages */ | |
| 1189 | + while (true) { | |
| 1190 | + ret = ican3_recv_msg(mod, &msg); | |
| 1191 | + if (ret) | |
| 1192 | + break; | |
| 1193 | + | |
| 1194 | + ican3_handle_message(mod, &msg); | |
| 1195 | + } | |
| 1196 | + | |
| 1197 | + /* process all CAN frames from the fast interface */ | |
| 1198 | + while (received < budget) { | |
| 1199 | + ret = ican3_recv_skb(mod); | |
| 1200 | + if (ret) | |
| 1201 | + break; | |
| 1202 | + | |
| 1203 | + received++; | |
| 1204 | + } | |
| 1205 | + | |
| 1206 | + /* We have processed all packets that the adapter had, but it | |
| 1207 | + * was less than our budget, stop polling */ | |
| 1208 | + if (received < budget) | |
| 1209 | + napi_complete(napi); | |
| 1210 | + | |
| 1211 | + spin_lock_irqsave(&mod->lock, flags); | |
| 1212 | + | |
| 1213 | + /* Wake up the transmit queue if necessary */ | |
| 1214 | + if (netif_queue_stopped(mod->ndev) && ican3_txok(mod)) | |
| 1215 | + netif_wake_queue(mod->ndev); | |
| 1216 | + | |
| 1217 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 1218 | + | |
| 1219 | + /* re-enable interrupt generation */ | |
| 1220 | + iowrite8(1 << mod->num, &mod->ctrl->int_enable); | |
| 1221 | + return received; | |
| 1222 | +} | |
| 1223 | + | |
| 1224 | +static irqreturn_t ican3_irq(int irq, void *dev_id) | |
| 1225 | +{ | |
| 1226 | + struct ican3_dev *mod = dev_id; | |
| 1227 | + u8 stat; | |
| 1228 | + | |
| 1229 | + /* | |
| 1230 | + * The interrupt status register on this device reports interrupts | |
| 1231 | + * as zeroes instead of using ones like most other devices | |
| 1232 | + */ | |
| 1233 | + stat = ioread8(&mod->ctrl->int_disable) & (1 << mod->num); | |
| 1234 | + if (stat == (1 << mod->num)) | |
| 1235 | + return IRQ_NONE; | |
| 1236 | + | |
| 1237 | + /* clear the MODULbus interrupt from the microcontroller */ | |
| 1238 | + ioread8(&mod->dpmctrl->interrupt); | |
| 1239 | + | |
| 1240 | + /* disable interrupt generation, schedule the NAPI poller */ | |
| 1241 | + iowrite8(1 << mod->num, &mod->ctrl->int_disable); | |
| 1242 | + napi_schedule(&mod->napi); | |
| 1243 | + return IRQ_HANDLED; | |
| 1244 | +} | |
| 1245 | + | |
| 1246 | +/* | |
| 1247 | + * Firmware reset, startup, and shutdown | |
| 1248 | + */ | |
| 1249 | + | |
| 1250 | +/* | |
| 1251 | + * Reset an ICAN module to its power-on state | |
| 1252 | + * | |
| 1253 | + * CONTEXT: no network device registered | |
| 1254 | + * LOCKING: work function disabled | |
| 1255 | + */ | |
| 1256 | +static int ican3_reset_module(struct ican3_dev *mod) | |
| 1257 | +{ | |
| 1258 | + u8 val = 1 << mod->num; | |
| 1259 | + unsigned long start; | |
| 1260 | + u8 runold, runnew; | |
| 1261 | + | |
| 1262 | + /* disable interrupts so no more work is scheduled */ | |
| 1263 | + iowrite8(1 << mod->num, &mod->ctrl->int_disable); | |
| 1264 | + | |
| 1265 | + /* flush any pending work */ | |
| 1266 | + flush_scheduled_work(); | |
| 1267 | + | |
| 1268 | + /* the first unallocated page in the DPM is #9 */ | |
| 1269 | + mod->free_page = DPM_FREE_START; | |
| 1270 | + | |
| 1271 | + ican3_set_page(mod, QUEUE_OLD_CONTROL); | |
| 1272 | + runold = ioread8(mod->dpm + TARGET_RUNNING); | |
| 1273 | + | |
| 1274 | + /* reset the module */ | |
| 1275 | + iowrite8(val, &mod->ctrl->reset_assert); | |
| 1276 | + iowrite8(val, &mod->ctrl->reset_deassert); | |
| 1277 | + | |
| 1278 | + /* wait until the module has finished resetting and is running */ | |
| 1279 | + start = jiffies; | |
| 1280 | + do { | |
| 1281 | + ican3_set_page(mod, QUEUE_OLD_CONTROL); | |
| 1282 | + runnew = ioread8(mod->dpm + TARGET_RUNNING); | |
| 1283 | + if (runnew == (runold ^ 0xff)) | |
| 1284 | + return 0; | |
| 1285 | + | |
| 1286 | + msleep(10); | |
| 1287 | + } while (time_before(jiffies, start + HZ / 4)); | |
| 1288 | + | |
| 1289 | + dev_err(mod->dev, "failed to reset CAN module\n"); | |
| 1290 | + return -ETIMEDOUT; | |
| 1291 | +} | |
| 1292 | + | |
| 1293 | +static void __devexit ican3_shutdown_module(struct ican3_dev *mod) | |
| 1294 | +{ | |
| 1295 | + ican3_msg_disconnect(mod); | |
| 1296 | + ican3_reset_module(mod); | |
| 1297 | +} | |
| 1298 | + | |
| 1299 | +/* | |
| 1300 | + * Startup an ICAN module, bringing it into fast mode | |
| 1301 | + */ | |
| 1302 | +static int __devinit ican3_startup_module(struct ican3_dev *mod) | |
| 1303 | +{ | |
| 1304 | + int ret; | |
| 1305 | + | |
| 1306 | + ret = ican3_reset_module(mod); | |
| 1307 | + if (ret) { | |
| 1308 | + dev_err(mod->dev, "unable to reset module\n"); | |
| 1309 | + return ret; | |
| 1310 | + } | |
| 1311 | + | |
| 1312 | + /* re-enable interrupts so we can send messages */ | |
| 1313 | + iowrite8(1 << mod->num, &mod->ctrl->int_enable); | |
| 1314 | + | |
| 1315 | + ret = ican3_msg_connect(mod); | |
| 1316 | + if (ret) { | |
| 1317 | + dev_err(mod->dev, "unable to connect to module\n"); | |
| 1318 | + return ret; | |
| 1319 | + } | |
| 1320 | + | |
| 1321 | + ican3_init_new_host_interface(mod); | |
| 1322 | + ret = ican3_msg_newhostif(mod); | |
| 1323 | + if (ret) { | |
| 1324 | + dev_err(mod->dev, "unable to switch to new-style interface\n"); | |
| 1325 | + return ret; | |
| 1326 | + } | |
| 1327 | + | |
| 1328 | + /* default to "termination on" */ | |
| 1329 | + ret = ican3_set_termination(mod, true); | |
| 1330 | + if (ret) { | |
| 1331 | + dev_err(mod->dev, "unable to enable termination\n"); | |
| 1332 | + return ret; | |
| 1333 | + } | |
| 1334 | + | |
| 1335 | + /* default to "bus errors enabled" */ | |
| 1336 | + ret = ican3_set_buserror(mod, ICAN3_BUSERR_QUOTA_MAX); | |
| 1337 | + if (ret) { | |
| 1338 | + dev_err(mod->dev, "unable to set bus-error\n"); | |
| 1339 | + return ret; | |
| 1340 | + } | |
| 1341 | + | |
| 1342 | + ican3_init_fast_host_interface(mod); | |
| 1343 | + ret = ican3_msg_fasthostif(mod); | |
| 1344 | + if (ret) { | |
| 1345 | + dev_err(mod->dev, "unable to switch to fast host interface\n"); | |
| 1346 | + return ret; | |
| 1347 | + } | |
| 1348 | + | |
| 1349 | + ret = ican3_set_id_filter(mod, true); | |
| 1350 | + if (ret) { | |
| 1351 | + dev_err(mod->dev, "unable to set acceptance filter\n"); | |
| 1352 | + return ret; | |
| 1353 | + } | |
| 1354 | + | |
| 1355 | + return 0; | |
| 1356 | +} | |
| 1357 | + | |
| 1358 | +/* | |
| 1359 | + * CAN Network Device | |
| 1360 | + */ | |
| 1361 | + | |
| 1362 | +static int ican3_open(struct net_device *ndev) | |
| 1363 | +{ | |
| 1364 | + struct ican3_dev *mod = netdev_priv(ndev); | |
| 1365 | + u8 quota; | |
| 1366 | + int ret; | |
| 1367 | + | |
| 1368 | + /* open the CAN layer */ | |
| 1369 | + ret = open_candev(ndev); | |
| 1370 | + if (ret) { | |
| 1371 | + dev_err(mod->dev, "unable to start CAN layer\n"); | |
| 1372 | + return ret; | |
| 1373 | + } | |
| 1374 | + | |
| 1375 | + /* set the bus error generation state appropriately */ | |
| 1376 | + if (mod->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) | |
| 1377 | + quota = ICAN3_BUSERR_QUOTA_MAX; | |
| 1378 | + else | |
| 1379 | + quota = 0; | |
| 1380 | + | |
| 1381 | + ret = ican3_set_buserror(mod, quota); | |
| 1382 | + if (ret) { | |
| 1383 | + dev_err(mod->dev, "unable to set bus-error\n"); | |
| 1384 | + close_candev(ndev); | |
| 1385 | + return ret; | |
| 1386 | + } | |
| 1387 | + | |
| 1388 | + /* bring the bus online */ | |
| 1389 | + ret = ican3_set_bus_state(mod, true); | |
| 1390 | + if (ret) { | |
| 1391 | + dev_err(mod->dev, "unable to set bus-on\n"); | |
| 1392 | + close_candev(ndev); | |
| 1393 | + return ret; | |
| 1394 | + } | |
| 1395 | + | |
| 1396 | + /* start up the network device */ | |
| 1397 | + mod->can.state = CAN_STATE_ERROR_ACTIVE; | |
| 1398 | + netif_start_queue(ndev); | |
| 1399 | + | |
| 1400 | + return 0; | |
| 1401 | +} | |
| 1402 | + | |
| 1403 | +static int ican3_stop(struct net_device *ndev) | |
| 1404 | +{ | |
| 1405 | + struct ican3_dev *mod = netdev_priv(ndev); | |
| 1406 | + int ret; | |
| 1407 | + | |
| 1408 | + /* stop the network device xmit routine */ | |
| 1409 | + netif_stop_queue(ndev); | |
| 1410 | + mod->can.state = CAN_STATE_STOPPED; | |
| 1411 | + | |
| 1412 | + /* bring the bus offline, stop receiving packets */ | |
| 1413 | + ret = ican3_set_bus_state(mod, false); | |
| 1414 | + if (ret) { | |
| 1415 | + dev_err(mod->dev, "unable to set bus-off\n"); | |
| 1416 | + return ret; | |
| 1417 | + } | |
| 1418 | + | |
| 1419 | + /* close the CAN layer */ | |
| 1420 | + close_candev(ndev); | |
| 1421 | + return 0; | |
| 1422 | +} | |
| 1423 | + | |
| 1424 | +static int ican3_xmit(struct sk_buff *skb, struct net_device *ndev) | |
| 1425 | +{ | |
| 1426 | + struct ican3_dev *mod = netdev_priv(ndev); | |
| 1427 | + struct net_device_stats *stats = &ndev->stats; | |
| 1428 | + struct can_frame *cf = (struct can_frame *)skb->data; | |
| 1429 | + struct ican3_fast_desc desc; | |
| 1430 | + void __iomem *desc_addr; | |
| 1431 | + unsigned long flags; | |
| 1432 | + | |
| 1433 | + spin_lock_irqsave(&mod->lock, flags); | |
| 1434 | + | |
| 1435 | + /* check that we can actually transmit */ | |
| 1436 | + if (!ican3_txok(mod)) { | |
| 1437 | + dev_err(mod->dev, "no free descriptors, stopping queue\n"); | |
| 1438 | + netif_stop_queue(ndev); | |
| 1439 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 1440 | + return NETDEV_TX_BUSY; | |
| 1441 | + } | |
| 1442 | + | |
| 1443 | + /* copy the control bits of the descriptor */ | |
| 1444 | + ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16)); | |
| 1445 | + desc_addr = mod->dpm + ((mod->fasttx_num % 16) * sizeof(desc)); | |
| 1446 | + memset(&desc, 0, sizeof(desc)); | |
| 1447 | + memcpy_fromio(&desc, desc_addr, 1); | |
| 1448 | + | |
| 1449 | + /* convert the Linux CAN frame into ICAN3 format */ | |
| 1450 | + can_frame_to_ican3(mod, cf, &desc); | |
| 1451 | + | |
| 1452 | + /* | |
| 1453 | + * the programming manual says that you must set the IVALID bit, then | |
| 1454 | + * interrupt, then set the valid bit. Quite weird, but it seems to be | |
| 1455 | + * required for this to work | |
| 1456 | + */ | |
| 1457 | + desc.control |= DESC_IVALID; | |
| 1458 | + memcpy_toio(desc_addr, &desc, sizeof(desc)); | |
| 1459 | + | |
| 1460 | + /* generate a MODULbus interrupt to the microcontroller */ | |
| 1461 | + iowrite8(0x01, &mod->dpmctrl->interrupt); | |
| 1462 | + | |
| 1463 | + desc.control ^= DESC_VALID; | |
| 1464 | + memcpy_toio(desc_addr, &desc, sizeof(desc)); | |
| 1465 | + | |
| 1466 | + /* update the next buffer pointer */ | |
| 1467 | + mod->fasttx_num = (desc.control & DESC_WRAP) ? 0 | |
| 1468 | + : (mod->fasttx_num + 1); | |
| 1469 | + | |
| 1470 | + /* update statistics */ | |
| 1471 | + stats->tx_packets++; | |
| 1472 | + stats->tx_bytes += cf->can_dlc; | |
| 1473 | + kfree_skb(skb); | |
| 1474 | + | |
| 1475 | + /* | |
| 1476 | + * This hardware doesn't have TX-done notifications, so we'll try and | |
| 1477 | + * emulate it the best we can using ECHO skbs. Get the next TX | |
| 1478 | + * descriptor, and see if we have room to send. If not, stop the queue. | |
| 1479 | + * It will be woken when the ECHO skb for the current packet is recv'd. | |
| 1480 | + */ | |
| 1481 | + | |
| 1482 | + /* copy the control bits of the descriptor */ | |
| 1483 | + if (!ican3_txok(mod)) | |
| 1484 | + netif_stop_queue(ndev); | |
| 1485 | + | |
| 1486 | + spin_unlock_irqrestore(&mod->lock, flags); | |
| 1487 | + return NETDEV_TX_OK; | |
| 1488 | +} | |
| 1489 | + | |
| 1490 | +static const struct net_device_ops ican3_netdev_ops = { | |
| 1491 | + .ndo_open = ican3_open, | |
| 1492 | + .ndo_stop = ican3_stop, | |
| 1493 | + .ndo_start_xmit = ican3_xmit, | |
| 1494 | +}; | |
| 1495 | + | |
| 1496 | +/* | |
| 1497 | + * Low-level CAN Device | |
| 1498 | + */ | |
| 1499 | + | |
| 1500 | +/* This structure was stolen from drivers/net/can/sja1000/sja1000.c */ | |
| 1501 | +static struct can_bittiming_const ican3_bittiming_const = { | |
| 1502 | + .name = DRV_NAME, | |
| 1503 | + .tseg1_min = 1, | |
| 1504 | + .tseg1_max = 16, | |
| 1505 | + .tseg2_min = 1, | |
| 1506 | + .tseg2_max = 8, | |
| 1507 | + .sjw_max = 4, | |
| 1508 | + .brp_min = 1, | |
| 1509 | + .brp_max = 64, | |
| 1510 | + .brp_inc = 1, | |
| 1511 | +}; | |
| 1512 | + | |
| 1513 | +/* | |
| 1514 | + * This routine was stolen from drivers/net/can/sja1000/sja1000.c | |
| 1515 | + * | |
| 1516 | + * The bittiming register command for the ICAN3 just sets the bit timing | |
| 1517 | + * registers on the SJA1000 chip directly | |
| 1518 | + */ | |
| 1519 | +static int ican3_set_bittiming(struct net_device *ndev) | |
| 1520 | +{ | |
| 1521 | + struct ican3_dev *mod = netdev_priv(ndev); | |
| 1522 | + struct can_bittiming *bt = &mod->can.bittiming; | |
| 1523 | + struct ican3_msg msg; | |
| 1524 | + u8 btr0, btr1; | |
| 1525 | + | |
| 1526 | + btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6); | |
| 1527 | + btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) | | |
| 1528 | + (((bt->phase_seg2 - 1) & 0x7) << 4); | |
| 1529 | + if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | |
| 1530 | + btr1 |= 0x80; | |
| 1531 | + | |
| 1532 | + memset(&msg, 0, sizeof(msg)); | |
| 1533 | + msg.spec = MSG_CBTRREQ; | |
| 1534 | + msg.len = cpu_to_le16(4); | |
| 1535 | + msg.data[0] = 0x00; | |
| 1536 | + msg.data[1] = 0x00; | |
| 1537 | + msg.data[2] = btr0; | |
| 1538 | + msg.data[3] = btr1; | |
| 1539 | + | |
| 1540 | + return ican3_send_msg(mod, &msg); | |
| 1541 | +} | |
| 1542 | + | |
| 1543 | +static int ican3_set_mode(struct net_device *ndev, enum can_mode mode) | |
| 1544 | +{ | |
| 1545 | + struct ican3_dev *mod = netdev_priv(ndev); | |
| 1546 | + int ret; | |
| 1547 | + | |
| 1548 | + if (mode != CAN_MODE_START) | |
| 1549 | + return -ENOTSUPP; | |
| 1550 | + | |
| 1551 | + /* bring the bus online */ | |
| 1552 | + ret = ican3_set_bus_state(mod, true); | |
| 1553 | + if (ret) { | |
| 1554 | + dev_err(mod->dev, "unable to set bus-on\n"); | |
| 1555 | + return ret; | |
| 1556 | + } | |
| 1557 | + | |
| 1558 | + /* start up the network device */ | |
| 1559 | + mod->can.state = CAN_STATE_ERROR_ACTIVE; | |
| 1560 | + | |
| 1561 | + if (netif_queue_stopped(ndev)) | |
| 1562 | + netif_wake_queue(ndev); | |
| 1563 | + | |
| 1564 | + return 0; | |
| 1565 | +} | |
| 1566 | + | |
| 1567 | +static int ican3_get_berr_counter(const struct net_device *ndev, | |
| 1568 | + struct can_berr_counter *bec) | |
| 1569 | +{ | |
| 1570 | + struct ican3_dev *mod = netdev_priv(ndev); | |
| 1571 | + int ret; | |
| 1572 | + | |
| 1573 | + ret = ican3_send_inquiry(mod, INQUIRY_STATUS); | |
| 1574 | + if (ret) | |
| 1575 | + return ret; | |
| 1576 | + | |
| 1577 | + ret = wait_for_completion_timeout(&mod->buserror_comp, HZ); | |
| 1578 | + if (ret <= 0) { | |
| 1579 | + dev_info(mod->dev, "%s timed out\n", __func__); | |
| 1580 | + return -ETIMEDOUT; | |
| 1581 | + } | |
| 1582 | + | |
| 1583 | + bec->rxerr = mod->bec.rxerr; | |
| 1584 | + bec->txerr = mod->bec.txerr; | |
| 1585 | + return 0; | |
| 1586 | +} | |
| 1587 | + | |
| 1588 | +/* | |
| 1589 | + * Sysfs Attributes | |
| 1590 | + */ | |
| 1591 | + | |
| 1592 | +static ssize_t ican3_sysfs_show_term(struct device *dev, | |
| 1593 | + struct device_attribute *attr, | |
| 1594 | + char *buf) | |
| 1595 | +{ | |
| 1596 | + struct ican3_dev *mod = netdev_priv(to_net_dev(dev)); | |
| 1597 | + int ret; | |
| 1598 | + | |
| 1599 | + ret = ican3_send_inquiry(mod, INQUIRY_TERMINATION); | |
| 1600 | + if (ret) | |
| 1601 | + return ret; | |
| 1602 | + | |
| 1603 | + ret = wait_for_completion_timeout(&mod->termination_comp, HZ); | |
| 1604 | + if (ret <= 0) { | |
| 1605 | + dev_info(mod->dev, "%s timed out\n", __func__); | |
| 1606 | + return -ETIMEDOUT; | |
| 1607 | + } | |
| 1608 | + | |
| 1609 | + return snprintf(buf, PAGE_SIZE, "%u\n", mod->termination_enabled); | |
| 1610 | +} | |
| 1611 | + | |
| 1612 | +static ssize_t ican3_sysfs_set_term(struct device *dev, | |
| 1613 | + struct device_attribute *attr, | |
| 1614 | + const char *buf, size_t count) | |
| 1615 | +{ | |
| 1616 | + struct ican3_dev *mod = netdev_priv(to_net_dev(dev)); | |
| 1617 | + unsigned long enable; | |
| 1618 | + int ret; | |
| 1619 | + | |
| 1620 | + if (strict_strtoul(buf, 0, &enable)) | |
| 1621 | + return -EINVAL; | |
| 1622 | + | |
| 1623 | + ret = ican3_set_termination(mod, enable); | |
| 1624 | + if (ret) | |
| 1625 | + return ret; | |
| 1626 | + | |
| 1627 | + return count; | |
| 1628 | +} | |
| 1629 | + | |
| 1630 | +static DEVICE_ATTR(termination, S_IWUGO | S_IRUGO, ican3_sysfs_show_term, | |
| 1631 | + ican3_sysfs_set_term); | |
| 1632 | + | |
| 1633 | +static struct attribute *ican3_sysfs_attrs[] = { | |
| 1634 | + &dev_attr_termination.attr, | |
| 1635 | + NULL, | |
| 1636 | +}; | |
| 1637 | + | |
| 1638 | +static struct attribute_group ican3_sysfs_attr_group = { | |
| 1639 | + .attrs = ican3_sysfs_attrs, | |
| 1640 | +}; | |
| 1641 | + | |
| 1642 | +/* | |
| 1643 | + * PCI Subsystem | |
| 1644 | + */ | |
| 1645 | + | |
| 1646 | +static int __devinit ican3_probe(struct platform_device *pdev) | |
| 1647 | +{ | |
| 1648 | + struct janz_platform_data *pdata; | |
| 1649 | + struct net_device *ndev; | |
| 1650 | + struct ican3_dev *mod; | |
| 1651 | + struct resource *res; | |
| 1652 | + struct device *dev; | |
| 1653 | + int ret; | |
| 1654 | + | |
| 1655 | + pdata = pdev->dev.platform_data; | |
| 1656 | + if (!pdata) | |
| 1657 | + return -ENXIO; | |
| 1658 | + | |
| 1659 | + dev_dbg(&pdev->dev, "probe: module number %d\n", pdata->modno); | |
| 1660 | + | |
| 1661 | + /* save the struct device for printing */ | |
| 1662 | + dev = &pdev->dev; | |
| 1663 | + | |
| 1664 | + /* allocate the CAN device and private data */ | |
| 1665 | + ndev = alloc_candev(sizeof(*mod), 0); | |
| 1666 | + if (!ndev) { | |
| 1667 | + dev_err(dev, "unable to allocate CANdev\n"); | |
| 1668 | + ret = -ENOMEM; | |
| 1669 | + goto out_return; | |
| 1670 | + } | |
| 1671 | + | |
| 1672 | + platform_set_drvdata(pdev, ndev); | |
| 1673 | + mod = netdev_priv(ndev); | |
| 1674 | + mod->ndev = ndev; | |
| 1675 | + mod->dev = &pdev->dev; | |
| 1676 | + mod->num = pdata->modno; | |
| 1677 | + netif_napi_add(ndev, &mod->napi, ican3_napi, ICAN3_RX_BUFFERS); | |
| 1678 | + spin_lock_init(&mod->lock); | |
| 1679 | + init_completion(&mod->termination_comp); | |
| 1680 | + init_completion(&mod->buserror_comp); | |
| 1681 | + | |
| 1682 | + /* setup device-specific sysfs attributes */ | |
| 1683 | + ndev->sysfs_groups[0] = &ican3_sysfs_attr_group; | |
| 1684 | + | |
| 1685 | + /* the first unallocated page in the DPM is 9 */ | |
| 1686 | + mod->free_page = DPM_FREE_START; | |
| 1687 | + | |
| 1688 | + ndev->netdev_ops = &ican3_netdev_ops; | |
| 1689 | + ndev->flags |= IFF_ECHO; | |
| 1690 | + SET_NETDEV_DEV(ndev, &pdev->dev); | |
| 1691 | + | |
| 1692 | + mod->can.clock.freq = ICAN3_CAN_CLOCK; | |
| 1693 | + mod->can.bittiming_const = &ican3_bittiming_const; | |
| 1694 | + mod->can.do_set_bittiming = ican3_set_bittiming; | |
| 1695 | + mod->can.do_set_mode = ican3_set_mode; | |
| 1696 | + mod->can.do_get_berr_counter = ican3_get_berr_counter; | |
| 1697 | + mod->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | |
| 1698 | + | CAN_CTRLMODE_BERR_REPORTING; | |
| 1699 | + | |
| 1700 | + /* find our IRQ number */ | |
| 1701 | + mod->irq = platform_get_irq(pdev, 0); | |
| 1702 | + if (mod->irq < 0) { | |
| 1703 | + dev_err(dev, "IRQ line not found\n"); | |
| 1704 | + ret = -ENODEV; | |
| 1705 | + goto out_free_ndev; | |
| 1706 | + } | |
| 1707 | + | |
| 1708 | + ndev->irq = mod->irq; | |
| 1709 | + | |
| 1710 | + /* get access to the MODULbus registers for this module */ | |
| 1711 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
| 1712 | + if (!res) { | |
| 1713 | + dev_err(dev, "MODULbus registers not found\n"); | |
| 1714 | + ret = -ENODEV; | |
| 1715 | + goto out_free_ndev; | |
| 1716 | + } | |
| 1717 | + | |
| 1718 | + mod->dpm = ioremap(res->start, resource_size(res)); | |
| 1719 | + if (!mod->dpm) { | |
| 1720 | + dev_err(dev, "MODULbus registers not ioremap\n"); | |
| 1721 | + ret = -ENOMEM; | |
| 1722 | + goto out_free_ndev; | |
| 1723 | + } | |
| 1724 | + | |
| 1725 | + mod->dpmctrl = mod->dpm + DPM_PAGE_SIZE; | |
| 1726 | + | |
| 1727 | + /* get access to the control registers for this module */ | |
| 1728 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
| 1729 | + if (!res) { | |
| 1730 | + dev_err(dev, "CONTROL registers not found\n"); | |
| 1731 | + ret = -ENODEV; | |
| 1732 | + goto out_iounmap_dpm; | |
| 1733 | + } | |
| 1734 | + | |
| 1735 | + mod->ctrl = ioremap(res->start, resource_size(res)); | |
| 1736 | + if (!mod->ctrl) { | |
| 1737 | + dev_err(dev, "CONTROL registers not ioremap\n"); | |
| 1738 | + ret = -ENOMEM; | |
| 1739 | + goto out_iounmap_dpm; | |
| 1740 | + } | |
| 1741 | + | |
| 1742 | + /* disable our IRQ, then hookup the IRQ handler */ | |
| 1743 | + iowrite8(1 << mod->num, &mod->ctrl->int_disable); | |
| 1744 | + ret = request_irq(mod->irq, ican3_irq, IRQF_SHARED, DRV_NAME, mod); | |
| 1745 | + if (ret) { | |
| 1746 | + dev_err(dev, "unable to request IRQ\n"); | |
| 1747 | + goto out_iounmap_ctrl; | |
| 1748 | + } | |
| 1749 | + | |
| 1750 | + /* reset and initialize the CAN controller into fast mode */ | |
| 1751 | + napi_enable(&mod->napi); | |
| 1752 | + ret = ican3_startup_module(mod); | |
| 1753 | + if (ret) { | |
| 1754 | + dev_err(dev, "%s: unable to start CANdev\n", __func__); | |
| 1755 | + goto out_free_irq; | |
| 1756 | + } | |
| 1757 | + | |
| 1758 | + /* register with the Linux CAN layer */ | |
| 1759 | + ret = register_candev(ndev); | |
| 1760 | + if (ret) { | |
| 1761 | + dev_err(dev, "%s: unable to register CANdev\n", __func__); | |
| 1762 | + goto out_free_irq; | |
| 1763 | + } | |
| 1764 | + | |
| 1765 | + dev_info(dev, "module %d: registered CAN device\n", pdata->modno); | |
| 1766 | + return 0; | |
| 1767 | + | |
| 1768 | +out_free_irq: | |
| 1769 | + napi_disable(&mod->napi); | |
| 1770 | + iowrite8(1 << mod->num, &mod->ctrl->int_disable); | |
| 1771 | + free_irq(mod->irq, mod); | |
| 1772 | +out_iounmap_ctrl: | |
| 1773 | + iounmap(mod->ctrl); | |
| 1774 | +out_iounmap_dpm: | |
| 1775 | + iounmap(mod->dpm); | |
| 1776 | +out_free_ndev: | |
| 1777 | + free_candev(ndev); | |
| 1778 | +out_return: | |
| 1779 | + return ret; | |
| 1780 | +} | |
| 1781 | + | |
| 1782 | +static int __devexit ican3_remove(struct platform_device *pdev) | |
| 1783 | +{ | |
| 1784 | + struct net_device *ndev = platform_get_drvdata(pdev); | |
| 1785 | + struct ican3_dev *mod = netdev_priv(ndev); | |
| 1786 | + | |
| 1787 | + /* unregister the netdevice, stop interrupts */ | |
| 1788 | + unregister_netdev(ndev); | |
| 1789 | + napi_disable(&mod->napi); | |
| 1790 | + iowrite8(1 << mod->num, &mod->ctrl->int_disable); | |
| 1791 | + free_irq(mod->irq, mod); | |
| 1792 | + | |
| 1793 | + /* put the module into reset */ | |
| 1794 | + ican3_shutdown_module(mod); | |
| 1795 | + | |
| 1796 | + /* unmap all registers */ | |
| 1797 | + iounmap(mod->ctrl); | |
| 1798 | + iounmap(mod->dpm); | |
| 1799 | + | |
| 1800 | + free_candev(ndev); | |
| 1801 | + | |
| 1802 | + return 0; | |
| 1803 | +} | |
| 1804 | + | |
| 1805 | +static struct platform_driver ican3_driver = { | |
| 1806 | + .driver = { | |
| 1807 | + .name = DRV_NAME, | |
| 1808 | + .owner = THIS_MODULE, | |
| 1809 | + }, | |
| 1810 | + .probe = ican3_probe, | |
| 1811 | + .remove = __devexit_p(ican3_remove), | |
| 1812 | +}; | |
| 1813 | + | |
| 1814 | +static int __init ican3_init(void) | |
| 1815 | +{ | |
| 1816 | + return platform_driver_register(&ican3_driver); | |
| 1817 | +} | |
| 1818 | + | |
| 1819 | +static void __exit ican3_exit(void) | |
| 1820 | +{ | |
| 1821 | + platform_driver_unregister(&ican3_driver); | |
| 1822 | +} | |
| 1823 | + | |
| 1824 | +MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>"); | |
| 1825 | +MODULE_DESCRIPTION("Janz MODULbus VMOD-ICAN3 Driver"); | |
| 1826 | +MODULE_LICENSE("GPL"); | |
| 1827 | +MODULE_ALIAS("platform:janz-ican3"); | |
| 1828 | + | |
| 1829 | +module_init(ican3_init); | |
| 1830 | +module_exit(ican3_exit); | |
| @@ -16,7 +16,7 @@ · 15 unmodified lines | ||
| 16 | 16 | #include <linux/delay.h> |
| 17 | 17 | #include <linux/platform_device.h> |
| 18 | 18 | #include <linux/regulator/driver.h> |
| 19 | −#include <linux/mfd/ab3100.h> | |
| 19 | +#include <linux/mfd/abx500.h> | |
| 20 | 20 | |
| 21 | 21 | /* LDO registers and some handy masking definitions for AB3100 */ |
| 22 | 22 | #define AB3100_LDO_A 0x40 |
| @@ -41,7 +41,7 @@ · 18 unmodified lines | ||
| 41 | 41 | * struct ab3100_regulator |
| 42 | 42 | * A struct passed around the individual regulator functions |
| 43 | 43 | * @platform_device: platform device holding this regulator |
| 44 | − * @ab3100: handle to the AB3100 parent chip | |
| 44 | + * @dev: handle to the device | |
| 45 | 45 | * @plfdata: AB3100 platform data passed in at probe time |
| 46 | 46 | * @regreg: regulator register number in the AB3100 |
| 47 | 47 | * @fixed_voltage: a fixed voltage for this regulator, if this |
| @@ -52,7 +52,7 @@ · 4 unmodified lines | ||
| 52 | 52 | */ |
| 53 | 53 | struct ab3100_regulator { |
| 54 | 54 | struct regulator_dev *rdev; |
| 55 | − struct ab3100 *ab3100; | |
| 55 | + struct device *dev; | |
| 56 | 56 | struct ab3100_platform_data *plfdata; |
| 57 | 57 | u8 regreg; |
| 58 | 58 | int fixed_voltage; |
| @@ -183,7 +183,7 @@ static int ab3100_enable_regulator(struct regulator_dev *reg) · 124 unmodified lines | ||
| 183 | 183 | int err; |
| 184 | 184 | u8 regval; |
| 185 | 185 | |
| 186 | − err = ab3100_get_register_interruptible(abreg->ab3100, abreg->regreg, | |
| 186 | + err = abx500_get_register_interruptible(abreg->dev, 0, abreg->regreg, | |
| 187 | 187 | ®val); |
| 188 | 188 | if (err) { |
| 189 | 189 | dev_warn(®->dev, "failed to get regid %d value\n", |
| @@ -197,7 +197,7 @@ static int ab3100_enable_regulator(struct regulator_dev *reg) · 7 unmodified lines | ||
| 197 | 197 | |
| 198 | 198 | regval |= AB3100_REG_ON_MASK; |
| 199 | 199 | |
| 200 | − err = ab3100_set_register_interruptible(abreg->ab3100, abreg->regreg, | |
| 200 | + err = abx500_set_register_interruptible(abreg->dev, 0, abreg->regreg, | |
| 201 | 201 | regval); |
| 202 | 202 | if (err) { |
| 203 | 203 | dev_warn(®->dev, "failed to set regid %d value\n", |
| @@ -245,14 +245,14 @@ static int ab3100_disable_regulator(struct regulator_dev *reg) · 41 unmodified lines | ||
| 245 | 245 | if (abreg->regreg == AB3100_LDO_D) { |
| 246 | 246 | dev_info(®->dev, "disabling LDO D - shut down system\n"); |
| 247 | 247 | /* Setting LDO D to 0x00 cuts the power to the SoC */ |
| 248 | − return ab3100_set_register_interruptible(abreg->ab3100, | |
| 248 | + return abx500_set_register_interruptible(abreg->dev, 0, | |
| 249 | 249 | AB3100_LDO_D, 0x00U); |
| 250 | 250 | } |
| 251 | 251 | |
| 252 | 252 | /* |
| 253 | 253 | * All other regulators are handled here |
| 254 | 254 | */ |
| 255 | − err = ab3100_get_register_interruptible(abreg->ab3100, abreg->regreg, | |
| 255 | + err = abx500_get_register_interruptible(abreg->dev, 0, abreg->regreg, | |
| 256 | 256 | ®val); |
| 257 | 257 | if (err) { |
| 258 | 258 | dev_err(®->dev, "unable to get register 0x%x\n", |
| @@ -260,7 +260,7 @@ static int ab3100_disable_regulator(struct regulator_dev *reg) · 1 unmodified line | ||
| 260 | 260 | return err; |
| 261 | 261 | } |
| 262 | 262 | regval &= ~AB3100_REG_ON_MASK; |
| 263 | − return ab3100_set_register_interruptible(abreg->ab3100, abreg->regreg, | |
| 263 | + return abx500_set_register_interruptible(abreg->dev, 0, abreg->regreg, | |
| 264 | 264 | regval); |
| 265 | 265 | } |
| 266 | 266 | |
| @@ -270,7 +270,7 @@ static int ab3100_is_enabled_regulator(struct regulator_dev *reg) · 3 unmodified lines | ||
| 270 | 270 | u8 regval; |
| 271 | 271 | int err; |
| 272 | 272 | |
| 273 | − err = ab3100_get_register_interruptible(abreg->ab3100, abreg->regreg, | |
| 273 | + err = abx500_get_register_interruptible(abreg->dev, 0, abreg->regreg, | |
| 274 | 274 | ®val); |
| 275 | 275 | if (err) { |
| 276 | 276 | dev_err(®->dev, "unable to get register 0x%x\n", |
| @@ -305,7 +305,7 @@ static int ab3100_get_voltage_regulator(struct regulator_dev *reg) · 28 unmodified lines | ||
| 305 | 305 | * For variable types, read out setting and index into |
| 306 | 306 | * supplied voltage list. |
| 307 | 307 | */ |
| 308 | − err = ab3100_get_register_interruptible(abreg->ab3100, | |
| 308 | + err = abx500_get_register_interruptible(abreg->dev, 0, | |
| 309 | 309 | abreg->regreg, ®val); |
| 310 | 310 | if (err) { |
| 311 | 311 | dev_warn(®->dev, |
| @@ -373,7 +373,7 @@ static int ab3100_set_voltage_regulator(struct regulator_dev *reg, · 61 unmodified lines | ||
| 373 | 373 | if (bestindex < 0) |
| 374 | 374 | return bestindex; |
| 375 | 375 | |
| 376 | − err = ab3100_get_register_interruptible(abreg->ab3100, | |
| 376 | + err = abx500_get_register_interruptible(abreg->dev, 0, | |
| 377 | 377 | abreg->regreg, ®val); |
| 378 | 378 | if (err) { |
| 379 | 379 | dev_warn(®->dev, |
| @@ -386,7 +386,7 @@ static int ab3100_set_voltage_regulator(struct regulator_dev *reg, · 6 unmodified lines | ||
| 386 | 386 | regval &= ~0xE0; |
| 387 | 387 | regval |= (bestindex << 5); |
| 388 | 388 | |
| 389 | − err = ab3100_set_register_interruptible(abreg->ab3100, | |
| 389 | + err = abx500_set_register_interruptible(abreg->dev, 0, | |
| 390 | 390 | abreg->regreg, regval); |
| 391 | 391 | if (err) |
| 392 | 392 | dev_warn(®->dev, "failed to set regulator register %02x\n", |
| @@ -414,7 +414,7 @@ static int ab3100_set_suspend_voltage_regulator(struct regulator_dev *reg, · 21 unmodified lines | ||
| 414 | 414 | /* LDO E and BUCK have special suspend voltages you can set */ |
| 415 | 415 | bestindex = ab3100_get_best_voltage_index(reg, uV, uV); |
| 416 | 416 | |
| 417 | − err = ab3100_get_register_interruptible(abreg->ab3100, | |
| 417 | + err = abx500_get_register_interruptible(abreg->dev, 0, | |
| 418 | 418 | targetreg, ®val); |
| 419 | 419 | if (err) { |
| 420 | 420 | dev_warn(®->dev, |
| @@ -427,7 +427,7 @@ static int ab3100_set_suspend_voltage_regulator(struct regulator_dev *reg, · 6 unmodified lines | ||
| 427 | 427 | regval &= ~0xE0; |
| 428 | 428 | regval |= (bestindex << 5); |
| 429 | 429 | |
| 430 | − err = ab3100_set_register_interruptible(abreg->ab3100, | |
| 430 | + err = abx500_set_register_interruptible(abreg->dev, 0, | |
| 431 | 431 | targetreg, regval); |
| 432 | 432 | if (err) |
| 433 | 433 | dev_warn(®->dev, "failed to set regulator register %02x\n", |
| @@ -574,13 +574,12 @@ ab3100_regulator_desc[AB3100_NUM_REGULATORS] = { · 140 unmodified lines | ||
| 574 | 574 | static int __devinit ab3100_regulators_probe(struct platform_device *pdev) |
| 575 | 575 | { |
| 576 | 576 | struct ab3100_platform_data *plfdata = pdev->dev.platform_data; |
| 577 | − struct ab3100 *ab3100 = platform_get_drvdata(pdev); | |
| 578 | 577 | int err = 0; |
| 579 | 578 | u8 data; |
| 580 | 579 | int i; |
| 581 | 580 | |
| 582 | 581 | /* Check chip state */ |
| 583 | − err = ab3100_get_register_interruptible(ab3100, | |
| 582 | + err = abx500_get_register_interruptible(&pdev->dev, 0, | |
| 584 | 583 | AB3100_LDO_D, &data); |
| 585 | 584 | if (err) { |
| 586 | 585 | dev_err(&pdev->dev, "could not read initial status of LDO_D\n"); |
| @@ -595,7 +594,7 @@ static int __devinit ab3100_regulators_probe(struct platform_device *pdev) · 8 unmodified lines | ||
| 595 | 594 | |
| 596 | 595 | /* Set up regulators */ |
| 597 | 596 | for (i = 0; i < ARRAY_SIZE(ab3100_reg_init_order); i++) { |
| 598 | − err = ab3100_set_register_interruptible(ab3100, | |
| 597 | + err = abx500_set_register_interruptible(&pdev->dev, 0, | |
| 599 | 598 | ab3100_reg_init_order[i], |
| 600 | 599 | plfdata->reg_initvals[i]); |
| 601 | 600 | if (err) { |
| @@ -617,7 +616,7 @@ static int __devinit ab3100_regulators_probe(struct platform_device *pdev) · 15 unmodified lines | ||
| 617 | 616 | * see what it looks like for a certain machine, go |
| 618 | 617 | * into the machine I2C setup. |
| 619 | 618 | */ |
| 620 | − reg->ab3100 = ab3100; | |
| 619 | + reg->dev = &pdev->dev; | |
| 621 | 620 | reg->plfdata = plfdata; |
| 622 | 621 | |
| 623 | 622 | /* |
| @@ -22,68 +22,9 @@ · 21 unmodified lines | ||
| 22 | 22 | #include <linux/platform_device.h> |
| 23 | 23 | #include <linux/regulator/driver.h> |
| 24 | 24 | #include <linux/regulator/machine.h> |
| 25 | −#include <linux/i2c.h> | |
| 26 | 25 | #include <linux/delay.h> |
| 27 | 26 | #include <linux/slab.h> |
| 28 | − | |
| 29 | −/* Register definitions */ | |
| 30 | −#define TPS6507X_REG_PPATH1 0X01 | |
| 31 | −#define TPS6507X_REG_INT 0X02 | |
| 32 | −#define TPS6507X_REG_CHGCONFIG0 0X03 | |
| 33 | −#define TPS6507X_REG_CHGCONFIG1 0X04 | |
| 34 | −#define TPS6507X_REG_CHGCONFIG2 0X05 | |
| 35 | −#define TPS6507X_REG_CHGCONFIG3 0X06 | |
| 36 | −#define TPS6507X_REG_REG_ADCONFIG 0X07 | |
| 37 | −#define TPS6507X_REG_TSCMODE 0X08 | |
| 38 | −#define TPS6507X_REG_ADRESULT_1 0X09 | |
| 39 | −#define TPS6507X_REG_ADRESULT_2 0X0A | |
| 40 | −#define TPS6507X_REG_PGOOD 0X0B | |
| 41 | −#define TPS6507X_REG_PGOODMASK 0X0C | |
| 42 | −#define TPS6507X_REG_CON_CTRL1 0X0D | |
| 43 | −#define TPS6507X_REG_CON_CTRL2 0X0E | |
| 44 | −#define TPS6507X_REG_CON_CTRL3 0X0F | |
| 45 | −#define TPS6507X_REG_DEFDCDC1 0X10 | |
| 46 | −#define TPS6507X_REG_DEFDCDC2_LOW 0X11 | |
| 47 | −#define TPS6507X_REG_DEFDCDC2_HIGH 0X12 | |
| 48 | −#define TPS6507X_REG_DEFDCDC3_LOW 0X13 | |
| 49 | −#define TPS6507X_REG_DEFDCDC3_HIGH 0X14 | |
| 50 | −#define TPS6507X_REG_DEFSLEW 0X15 | |
| 51 | −#define TPS6507X_REG_LDO_CTRL1 0X16 | |
| 52 | −#define TPS6507X_REG_DEFLDO2 0X17 | |
| 53 | −#define TPS6507X_REG_WLED_CTRL1 0X18 | |
| 54 | −#define TPS6507X_REG_WLED_CTRL2 0X19 | |
| 55 | − | |
| 56 | −/* CON_CTRL1 bitfields */ | |
| 57 | −#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4) | |
| 58 | −#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3) | |
| 59 | −#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2) | |
| 60 | −#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1) | |
| 61 | −#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0) | |
| 62 | − | |
| 63 | −/* DEFDCDC1 bitfields */ | |
| 64 | −#define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7) | |
| 65 | −#define TPS6507X_DEFDCDC1_DCDC1_MASK 0X3F | |
| 66 | − | |
| 67 | −/* DEFDCDC2_LOW bitfields */ | |
| 68 | −#define TPS6507X_DEFDCDC2_LOW_DCDC2_MASK 0X3F | |
| 69 | − | |
| 70 | −/* DEFDCDC2_HIGH bitfields */ | |
| 71 | −#define TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK 0X3F | |
| 72 | − | |
| 73 | −/* DEFDCDC3_LOW bitfields */ | |
| 74 | −#define TPS6507X_DEFDCDC3_LOW_DCDC3_MASK 0X3F | |
| 75 | − | |
| 76 | −/* DEFDCDC3_HIGH bitfields */ | |
| 77 | −#define TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK 0X3F | |
| 78 | − | |
| 79 | −/* TPS6507X_REG_LDO_CTRL1 bitfields */ | |
| 80 | −#define TPS6507X_REG_LDO_CTRL1_LDO1_MASK 0X0F | |
| 81 | − | |
| 82 | −/* TPS6507X_REG_DEFLDO2 bitfields */ | |
| 83 | −#define TPS6507X_REG_DEFLDO2_LDO2_MASK 0X3F | |
| 84 | − | |
| 85 | −/* VDCDC MASK */ | |
| 86 | −#define TPS6507X_DEFDCDCX_DCDC_MASK 0X3F | |
| 27 | +#include <linux/mfd/tps6507x.h> | |
| 87 | 28 | |
| 88 | 29 | /* DCDC's */ |
| 89 | 30 | #define TPS6507X_DCDC_1 0 |
| @@ -162,101 +103,146 @@ struct tps_info { · 72 unmodified lines | ||
| 162 | 103 | const u16 *table; |
| 163 | 104 | }; |
| 164 | 105 | |
| 165 | −struct tps_pmic { | |
| 106 | +static const struct tps_info tps6507x_pmic_regs[] = { | |
| 107 | + { | |
| 108 | + .name = "VDCDC1", | |
| 109 | + .min_uV = 725000, | |
| 110 | + .max_uV = 3300000, | |
| 111 | + .table_len = ARRAY_SIZE(VDCDCx_VSEL_table), | |
| 112 | + .table = VDCDCx_VSEL_table, | |
| 113 | + }, | |
| 114 | + { | |
| 115 | + .name = "VDCDC2", | |
| 116 | + .min_uV = 725000, | |
| 117 | + .max_uV = 3300000, | |
| 118 | + .table_len = ARRAY_SIZE(VDCDCx_VSEL_table), | |
| 119 | + .table = VDCDCx_VSEL_table, | |
| 120 | + }, | |
| 121 | + { | |
| 122 | + .name = "VDCDC3", | |
| 123 | + .min_uV = 725000, | |
| 124 | + .max_uV = 3300000, | |
| 125 | + .table_len = ARRAY_SIZE(VDCDCx_VSEL_table), | |
| 126 | + .table = VDCDCx_VSEL_table, | |
| 127 | + }, | |
| 128 | + { | |
| 129 | + .name = "LDO1", | |
| 130 | + .min_uV = 1000000, | |
| 131 | + .max_uV = 3300000, | |
| 132 | + .table_len = ARRAY_SIZE(LDO1_VSEL_table), | |
| 133 | + .table = LDO1_VSEL_table, | |
| 134 | + }, | |
| 135 | + { | |
| 136 | + .name = "LDO2", | |
| 137 | + .min_uV = 725000, | |
| 138 | + .max_uV = 3300000, | |
| 139 | + .table_len = ARRAY_SIZE(LDO2_VSEL_table), | |
| 140 | + .table = LDO2_VSEL_table, | |
| 141 | + }, | |
| 142 | +}; | |
| 143 | + | |
| 144 | +struct tps6507x_pmic { | |
| 166 | 145 | struct regulator_desc desc[TPS6507X_NUM_REGULATOR]; |
| 167 | − struct i2c_client *client; | |
| 146 | + struct tps6507x_dev *mfd; | |
| 168 | 147 | struct regulator_dev *rdev[TPS6507X_NUM_REGULATOR]; |
| 169 | 148 | const struct tps_info *info[TPS6507X_NUM_REGULATOR]; |
| 170 | 149 | struct mutex io_lock; |
| 171 | 150 | }; |
| 172 | − | |
| 173 | −static inline int tps_6507x_read(struct tps_pmic *tps, u8 reg) | |
| 151 | +static inline int tps6507x_pmic_read(struct tps6507x_pmic *tps, u8 reg) | |
| 174 | 152 | { |
| 175 | − return i2c_smbus_read_byte_data(tps->client, reg); | |
| 153 | + u8 val; | |
| 154 | + int err; | |
| 155 | + | |
| 156 | + err = tps->mfd->read_dev(tps->mfd, reg, 1, &val); | |
| 157 | + | |
| 158 | + if (err) | |
| 159 | + return err; | |
| 160 | + | |
| 161 | + return val; | |
| 176 | 162 | } |
| 177 | 163 | |
| 178 | −static inline int tps_6507x_write(struct tps_pmic *tps, u8 reg, u8 val) | |
| 164 | +static inline int tps6507x_pmic_write(struct tps6507x_pmic *tps, u8 reg, u8 val) | |
| 179 | 165 | { |
| 180 | − return i2c_smbus_write_byte_data(tps->client, reg, val); | |
| 166 | + return tps->mfd->write_dev(tps->mfd, reg, 1, &val); | |
| 181 | 167 | } |
| 182 | 168 | |
| 183 | −static int tps_6507x_set_bits(struct tps_pmic *tps, u8 reg, u8 mask) | |
| 169 | +static int tps6507x_pmic_set_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) | |
| 184 | 170 | { |
| 185 | 171 | int err, data; |
| 186 | 172 | |
| 187 | 173 | mutex_lock(&tps->io_lock); |
| 188 | 174 | |
| 189 | − data = tps_6507x_read(tps, reg); | |
| 175 | + data = tps6507x_pmic_read(tps, reg); | |
| 190 | 176 | if (data < 0) { |
| 191 | − dev_err(&tps->client->dev, "Read from reg 0x%x failed\n", reg); | |
| 177 | + dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
| 192 | 178 | err = data; |
| 193 | 179 | goto out; |
| 194 | 180 | } |
| 195 | 181 | |
| 196 | 182 | data |= mask; |
| 197 | − err = tps_6507x_write(tps, reg, data); | |
| 183 | + err = tps6507x_pmic_write(tps, reg, data); | |
| 198 | 184 | if (err) |
| 199 | − dev_err(&tps->client->dev, "Write for reg 0x%x failed\n", reg); | |
| 185 | + dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
| 200 | 186 | |
| 201 | 187 | out: |
| 202 | 188 | mutex_unlock(&tps->io_lock); |
| 203 | 189 | return err; |
| 204 | 190 | } |
| 205 | 191 | |
| 206 | −static int tps_6507x_clear_bits(struct tps_pmic *tps, u8 reg, u8 mask) | |
| 192 | +static int tps6507x_pmic_clear_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) | |
| 207 | 193 | { |
| 208 | 194 | int err, data; |
| 209 | 195 | |
| 210 | 196 | mutex_lock(&tps->io_lock); |
| 211 | 197 | |
| 212 | − data = tps_6507x_read(tps, reg); | |
| 198 | + data = tps6507x_pmic_read(tps, reg); | |
| 213 | 199 | if (data < 0) { |
| 214 | − dev_err(&tps->client->dev, "Read from reg 0x%x failed\n", reg); | |
| 200 | + dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
| 215 | 201 | err = data; |
| 216 | 202 | goto out; |
| 217 | 203 | } |
| 218 | 204 | |
| 219 | 205 | data &= ~mask; |
| 220 | − err = tps_6507x_write(tps, reg, data); | |
| 206 | + err = tps6507x_pmic_write(tps, reg, data); | |
| 221 | 207 | if (err) |
| 222 | − dev_err(&tps->client->dev, "Write for reg 0x%x failed\n", reg); | |
| 208 | + dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
| 223 | 209 | |
| 224 | 210 | out: |
| 225 | 211 | mutex_unlock(&tps->io_lock); |
| 226 | 212 | return err; |
| 227 | 213 | } |
| 228 | 214 | |
| 229 | −static int tps_6507x_reg_read(struct tps_pmic *tps, u8 reg) | |
| 215 | +static int tps6507x_pmic_reg_read(struct tps6507x_pmic *tps, u8 reg) | |
| 230 | 216 | { |
| 231 | 217 | int data; |
| 232 | 218 | |
| 233 | 219 | mutex_lock(&tps->io_lock); |
| 234 | 220 | |
| 235 | − data = tps_6507x_read(tps, reg); | |
| 221 | + data = tps6507x_pmic_read(tps, reg); | |
| 236 | 222 | if (data < 0) |
| 237 | − dev_err(&tps->client->dev, "Read from reg 0x%x failed\n", reg); | |
| 223 | + dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
| 238 | 224 | |
| 239 | 225 | mutex_unlock(&tps->io_lock); |
| 240 | 226 | return data; |
| 241 | 227 | } |
| 242 | 228 | |
| 243 | −static int tps_6507x_reg_write(struct tps_pmic *tps, u8 reg, u8 val) | |
| 229 | +static int tps6507x_pmic_reg_write(struct tps6507x_pmic *tps, u8 reg, u8 val) | |
| 244 | 230 | { |
| 245 | 231 | int err; |
| 246 | 232 | |
| 247 | 233 | mutex_lock(&tps->io_lock); |
| 248 | 234 | |
| 249 | − err = tps_6507x_write(tps, reg, val); | |
| 235 | + err = tps6507x_pmic_write(tps, reg, val); | |
| 250 | 236 | if (err < 0) |
| 251 | − dev_err(&tps->client->dev, "Write for reg 0x%x failed\n", reg); | |
| 237 | + dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
| 252 | 238 | |
| 253 | 239 | mutex_unlock(&tps->io_lock); |
| 254 | 240 | return err; |
| 255 | 241 | } |
| 256 | 242 | |
| 257 | −static int tps6507x_dcdc_is_enabled(struct regulator_dev *dev) | |
| 243 | +static int tps6507x_pmic_dcdc_is_enabled(struct regulator_dev *dev) | |
| 258 | 244 | { |
| 259 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 245 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 260 | 246 | int data, dcdc = rdev_get_id(dev); |
| 261 | 247 | u8 shift; |
| 262 | 248 | |
| @@ -264,7 +250,7 @@ static int tps6507x_dcdc_is_enabled(struct regulator_dev *dev) · 1 unmodified line | ||
| 264 | 250 | return -EINVAL; |
| 265 | 251 | |
| 266 | 252 | shift = TPS6507X_MAX_REG_ID - dcdc; |
| 267 | − data = tps_6507x_reg_read(tps, TPS6507X_REG_CON_CTRL1); | |
| 253 | + data = tps6507x_pmic_reg_read(tps, TPS6507X_REG_CON_CTRL1); | |
| 268 | 254 | |
| 269 | 255 | if (data < 0) |
| 270 | 256 | return data; |
| @@ -272,9 +258,9 @@ static int tps6507x_dcdc_is_enabled(struct regulator_dev *dev) · 1 unmodified line | ||
| 272 | 258 | return (data & 1<<shift) ? 1 : 0; |
| 273 | 259 | } |
| 274 | 260 | |
| 275 | −static int tps6507x_ldo_is_enabled(struct regulator_dev *dev) | |
| 261 | +static int tps6507x_pmic_ldo_is_enabled(struct regulator_dev *dev) | |
| 276 | 262 | { |
| 277 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 263 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 278 | 264 | int data, ldo = rdev_get_id(dev); |
| 279 | 265 | u8 shift; |
| 280 | 266 | |
| @@ -282,7 +268,7 @@ static int tps6507x_ldo_is_enabled(struct regulator_dev *dev) · 1 unmodified line | ||
| 282 | 268 | return -EINVAL; |
| 283 | 269 | |
| 284 | 270 | shift = TPS6507X_MAX_REG_ID - ldo; |
| 285 | − data = tps_6507x_reg_read(tps, TPS6507X_REG_CON_CTRL1); | |
| 271 | + data = tps6507x_pmic_reg_read(tps, TPS6507X_REG_CON_CTRL1); | |
| 286 | 272 | |
| 287 | 273 | if (data < 0) |
| 288 | 274 | return data; |
| @@ -290,9 +276,9 @@ static int tps6507x_ldo_is_enabled(struct regulator_dev *dev) · 1 unmodified line | ||
| 290 | 276 | return (data & 1<<shift) ? 1 : 0; |
| 291 | 277 | } |
| 292 | 278 | |
| 293 | −static int tps6507x_dcdc_enable(struct regulator_dev *dev) | |
| 279 | +static int tps6507x_pmic_dcdc_enable(struct regulator_dev *dev) | |
| 294 | 280 | { |
| 295 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 281 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 296 | 282 | int dcdc = rdev_get_id(dev); |
| 297 | 283 | u8 shift; |
| 298 | 284 | |
| @@ -300,12 +286,12 @@ static int tps6507x_dcdc_enable(struct regulator_dev *dev) · 1 unmodified line | ||
| 300 | 286 | return -EINVAL; |
| 301 | 287 | |
| 302 | 288 | shift = TPS6507X_MAX_REG_ID - dcdc; |
| 303 | − return tps_6507x_set_bits(tps, TPS6507X_REG_CON_CTRL1, 1 << shift); | |
| 289 | + return tps6507x_pmic_set_bits(tps, TPS6507X_REG_CON_CTRL1, 1 << shift); | |
| 304 | 290 | } |
| 305 | 291 | |
| 306 | −static int tps6507x_dcdc_disable(struct regulator_dev *dev) | |
| 292 | +static int tps6507x_pmic_dcdc_disable(struct regulator_dev *dev) | |
| 307 | 293 | { |
| 308 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 294 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 309 | 295 | int dcdc = rdev_get_id(dev); |
| 310 | 296 | u8 shift; |
| 311 | 297 | |
| @@ -313,12 +299,13 @@ static int tps6507x_dcdc_disable(struct regulator_dev *dev) · 1 unmodified line | ||
| 313 | 299 | return -EINVAL; |
| 314 | 300 | |
| 315 | 301 | shift = TPS6507X_MAX_REG_ID - dcdc; |
| 316 | − return tps_6507x_clear_bits(tps, TPS6507X_REG_CON_CTRL1, 1 << shift); | |
| 302 | + return tps6507x_pmic_clear_bits(tps, TPS6507X_REG_CON_CTRL1, | |
| 303 | + 1 << shift); | |
| 317 | 304 | } |
| 318 | 305 | |
| 319 | −static int tps6507x_ldo_enable(struct regulator_dev *dev) | |
| 306 | +static int tps6507x_pmic_ldo_enable(struct regulator_dev *dev) | |
| 320 | 307 | { |
| 321 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 308 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 322 | 309 | int ldo = rdev_get_id(dev); |
| 323 | 310 | u8 shift; |
| 324 | 311 | |
| @@ -326,12 +313,12 @@ static int tps6507x_ldo_enable(struct regulator_dev *dev) · 1 unmodified line | ||
| 326 | 313 | return -EINVAL; |
| 327 | 314 | |
| 328 | 315 | shift = TPS6507X_MAX_REG_ID - ldo; |
| 329 | − return tps_6507x_set_bits(tps, TPS6507X_REG_CON_CTRL1, 1 << shift); | |
| 316 | + return tps6507x_pmic_set_bits(tps, TPS6507X_REG_CON_CTRL1, 1 << shift); | |
| 330 | 317 | } |
| 331 | 318 | |
| 332 | −static int tps6507x_ldo_disable(struct regulator_dev *dev) | |
| 319 | +static int tps6507x_pmic_ldo_disable(struct regulator_dev *dev) | |
| 333 | 320 | { |
| 334 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 321 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 335 | 322 | int ldo = rdev_get_id(dev); |
| 336 | 323 | u8 shift; |
| 337 | 324 | |
| @@ -339,12 +326,13 @@ static int tps6507x_ldo_disable(struct regulator_dev *dev) · 1 unmodified line | ||
| 339 | 326 | return -EINVAL; |
| 340 | 327 | |
| 341 | 328 | shift = TPS6507X_MAX_REG_ID - ldo; |
| 342 | − return tps_6507x_clear_bits(tps, TPS6507X_REG_CON_CTRL1, 1 << shift); | |
| 329 | + return tps6507x_pmic_clear_bits(tps, TPS6507X_REG_CON_CTRL1, | |
| 330 | + 1 << shift); | |
| 343 | 331 | } |
| 344 | 332 | |
| 345 | −static int tps6507x_dcdc_get_voltage(struct regulator_dev *dev) | |
| 333 | +static int tps6507x_pmic_dcdc_get_voltage(struct regulator_dev *dev) | |
| 346 | 334 | { |
| 347 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 335 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 348 | 336 | int data, dcdc = rdev_get_id(dev); |
| 349 | 337 | u8 reg; |
| 350 | 338 | |
| @@ -362,7 +350,7 @@ static int tps6507x_dcdc_get_voltage(struct regulator_dev *dev) · 11 unmodified lines | ||
| 362 | 350 | return -EINVAL; |
| 363 | 351 | } |
| 364 | 352 | |
| 365 | − data = tps_6507x_reg_read(tps, reg); | |
| 353 | + data = tps6507x_pmic_reg_read(tps, reg); | |
| 366 | 354 | if (data < 0) |
| 367 | 355 | return data; |
| 368 | 356 | |
| @@ -370,10 +358,10 @@ static int tps6507x_dcdc_get_voltage(struct regulator_dev *dev) · 1 unmodified line | ||
| 370 | 358 | return tps->info[dcdc]->table[data] * 1000; |
| 371 | 359 | } |
| 372 | 360 | |
| 373 | −static int tps6507x_dcdc_set_voltage(struct regulator_dev *dev, | |
| 361 | +static int tps6507x_pmic_dcdc_set_voltage(struct regulator_dev *dev, | |
| 374 | 362 | int min_uV, int max_uV) |
| 375 | 363 | { |
| 376 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 364 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 377 | 365 | int data, vsel, dcdc = rdev_get_id(dev); |
| 378 | 366 | u8 reg; |
| 379 | 367 | |
| @@ -411,19 +399,19 @@ static int tps6507x_dcdc_set_voltage(struct regulator_dev *dev, · 31 unmodified lines | ||
| 411 | 399 | if (vsel == tps->info[dcdc]->table_len) |
| 412 | 400 | return -EINVAL; |
| 413 | 401 | |
| 414 | − data = tps_6507x_reg_read(tps, reg); | |
| 402 | + data = tps6507x_pmic_reg_read(tps, reg); | |
| 415 | 403 | if (data < 0) |
| 416 | 404 | return data; |
| 417 | 405 | |
| 418 | 406 | data &= ~TPS6507X_DEFDCDCX_DCDC_MASK; |
| 419 | 407 | data |= vsel; |
| 420 | 408 | |
| 421 | − return tps_6507x_reg_write(tps, reg, data); | |
| 409 | + return tps6507x_pmic_reg_write(tps, reg, data); | |
| 422 | 410 | } |
| 423 | 411 | |
| 424 | −static int tps6507x_ldo_get_voltage(struct regulator_dev *dev) | |
| 412 | +static int tps6507x_pmic_ldo_get_voltage(struct regulator_dev *dev) | |
| 425 | 413 | { |
| 426 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 414 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 427 | 415 | int data, ldo = rdev_get_id(dev); |
| 428 | 416 | u8 reg, mask; |
| 429 | 417 | |
| @@ -437,7 +425,7 @@ static int tps6507x_ldo_get_voltage(struct regulator_dev *dev) · 7 unmodified lines | ||
| 437 | 425 | TPS6507X_REG_DEFLDO2_LDO2_MASK); |
| 438 | 426 | } |
| 439 | 427 | |
| 440 | − data = tps_6507x_reg_read(tps, reg); | |
| 428 | + data = tps6507x_pmic_reg_read(tps, reg); | |
| 441 | 429 | if (data < 0) |
| 442 | 430 | return data; |
| 443 | 431 | |
| @@ -445,10 +433,10 @@ static int tps6507x_ldo_get_voltage(struct regulator_dev *dev) · 1 unmodified line | ||
| 445 | 433 | return tps->info[ldo]->table[data] * 1000; |
| 446 | 434 | } |
| 447 | 435 | |
| 448 | −static int tps6507x_ldo_set_voltage(struct regulator_dev *dev, | |
| 436 | +static int tps6507x_pmic_ldo_set_voltage(struct regulator_dev *dev, | |
| 449 | 437 | int min_uV, int max_uV) |
| 450 | 438 | { |
| 451 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 439 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 452 | 440 | int data, vsel, ldo = rdev_get_id(dev); |
| 453 | 441 | u8 reg, mask; |
| 454 | 442 | |
| @@ -479,20 +467,20 @@ static int tps6507x_ldo_set_voltage(struct regulator_dev *dev, · 24 unmodified lines | ||
| 479 | 467 | if (vsel == tps->info[ldo]->table_len) |
| 480 | 468 | return -EINVAL; |
| 481 | 469 | |
| 482 | − data = tps_6507x_reg_read(tps, reg); | |
| 470 | + data = tps6507x_pmic_reg_read(tps, reg); | |
| 483 | 471 | if (data < 0) |
| 484 | 472 | return data; |
| 485 | 473 | |
| 486 | 474 | data &= ~mask; |
| 487 | 475 | data |= vsel; |
| 488 | 476 | |
| 489 | − return tps_6507x_reg_write(tps, reg, data); | |
| 477 | + return tps6507x_pmic_reg_write(tps, reg, data); | |
| 490 | 478 | } |
| 491 | 479 | |
| 492 | −static int tps6507x_dcdc_list_voltage(struct regulator_dev *dev, | |
| 480 | +static int tps6507x_pmic_dcdc_list_voltage(struct regulator_dev *dev, | |
| 493 | 481 | unsigned selector) |
| 494 | 482 | { |
| 495 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 483 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 496 | 484 | int dcdc = rdev_get_id(dev); |
| 497 | 485 | |
| 498 | 486 | if (dcdc < TPS6507X_DCDC_1 || dcdc > TPS6507X_DCDC_3) |
| @@ -504,10 +492,10 @@ static int tps6507x_dcdc_list_voltage(struct regulator_dev *dev, · 5 unmodified lines | ||
| 504 | 492 | return tps->info[dcdc]->table[selector] * 1000; |
| 505 | 493 | } |
| 506 | 494 | |
| 507 | −static int tps6507x_ldo_list_voltage(struct regulator_dev *dev, | |
| 495 | +static int tps6507x_pmic_ldo_list_voltage(struct regulator_dev *dev, | |
| 508 | 496 | unsigned selector) |
| 509 | 497 | { |
| 510 | − struct tps_pmic *tps = rdev_get_drvdata(dev); | |
| 498 | + struct tps6507x_pmic *tps = rdev_get_drvdata(dev); | |
| 511 | 499 | int ldo = rdev_get_id(dev); |
| 512 | 500 | |
| 513 | 501 | if (ldo < TPS6507X_LDO_1 || ldo > TPS6507X_LDO_2) |
| @@ -520,47 +508,54 @@ static int tps6507x_ldo_list_voltage(struct regulator_dev *dev, · 6 unmodified lines | ||
| 520 | 508 | } |
| 521 | 509 | |
| 522 | 510 | /* Operations permitted on VDCDCx */ |
| 523 | −static struct regulator_ops tps6507x_dcdc_ops = { | |
| 524 | − .is_enabled = tps6507x_dcdc_is_enabled, | |
| 525 | − .enable = tps6507x_dcdc_enable, | |
| 526 | − .disable = tps6507x_dcdc_disable, | |
| 527 | − .get_voltage = tps6507x_dcdc_get_voltage, | |
| 528 | − .set_voltage = tps6507x_dcdc_set_voltage, | |
| 529 | − .list_voltage = tps6507x_dcdc_list_voltage, | |
| 511 | +static struct regulator_ops tps6507x_pmic_dcdc_ops = { | |
| 512 | + .is_enabled = tps6507x_pmic_dcdc_is_enabled, | |
| 513 | + .enable = tps6507x_pmic_dcdc_enable, | |
| 514 | + .disable = tps6507x_pmic_dcdc_disable, | |
| 515 | + .get_voltage = tps6507x_pmic_dcdc_get_voltage, | |
| 516 | + .set_voltage = tps6507x_pmic_dcdc_set_voltage, | |
| 517 | + .list_voltage = tps6507x_pmic_dcdc_list_voltage, | |
| 530 | 518 | }; |
| 531 | 519 | |
| 532 | 520 | /* Operations permitted on LDOx */ |
| 533 | −static struct regulator_ops tps6507x_ldo_ops = { | |
| 534 | − .is_enabled = tps6507x_ldo_is_enabled, | |
| 535 | − .enable = tps6507x_ldo_enable, | |
| 536 | − .disable = tps6507x_ldo_disable, | |
| 537 | − .get_voltage = tps6507x_ldo_get_voltage, | |
| 538 | − .set_voltage = tps6507x_ldo_set_voltage, | |
| 539 | − .list_voltage = tps6507x_ldo_list_voltage, | |
| 521 | +static struct regulator_ops tps6507x_pmic_ldo_ops = { | |
| 522 | + .is_enabled = tps6507x_pmic_ldo_is_enabled, | |
| 523 | + .enable = tps6507x_pmic_ldo_enable, | |
| 524 | + .disable = tps6507x_pmic_ldo_disable, | |
| 525 | + .get_voltage = tps6507x_pmic_ldo_get_voltage, | |
| 526 | + .set_voltage = tps6507x_pmic_ldo_set_voltage, | |
| 527 | + .list_voltage = tps6507x_pmic_ldo_list_voltage, | |
| 540 | 528 | }; |
| 541 | 529 | |
| 542 | −static int __devinit tps_6507x_probe(struct i2c_client *client, | |
| 543 | − const struct i2c_device_id *id) | |
| 530 | +static __devinit | |
| 531 | +int tps6507x_pmic_probe(struct platform_device *pdev) | |
| 544 | 532 | { |
| 533 | + struct tps6507x_dev *tps6507x_dev = dev_get_drvdata(pdev->dev.parent); | |
| 545 | 534 | static int desc_id; |
| 546 | − const struct tps_info *info = (void *)id->driver_data; | |
| 535 | + const struct tps_info *info = &tps6507x_pmic_regs[0]; | |
| 547 | 536 | struct regulator_init_data *init_data; |
| 548 | 537 | struct regulator_dev *rdev; |
| 549 | − struct tps_pmic *tps; | |
| 538 | + struct tps6507x_pmic *tps; | |
| 539 | + struct tps6507x_board *tps_board; | |
| 550 | 540 | int i; |
| 551 | 541 | int error; |
| 552 | 542 | |
| 553 | − if (!i2c_check_functionality(client->adapter, | |
| 554 | − I2C_FUNC_SMBUS_BYTE_DATA)) | |
| 555 | − return -EIO; | |
| 543 | + /** | |
| 544 | + * tps_board points to pmic related constants | |
| 545 | + * coming from the board-evm file. | |
| 546 | + */ | |
| 547 | + | |
| 548 | + tps_board = dev_get_platdata(tps6507x_dev->dev); | |
| 549 | + if (!tps_board) | |
| 550 | + return -EINVAL; | |
| 556 | 551 | |
| 557 | 552 | /** |
| 558 | 553 | * init_data points to array of regulator_init structures |
| 559 | 554 | * coming from the board-evm file. |
| 560 | 555 | */ |
| 561 | − init_data = client->dev.platform_data; | |
| 556 | + init_data = tps_board->tps6507x_pmic_init_data; | |
| 562 | 557 | if (!init_data) |
| 563 | − return -EIO; | |
| 558 | + return -EINVAL; | |
| 564 | 559 | |
| 565 | 560 | tps = kzalloc(sizeof(*tps), GFP_KERNEL); |
| 566 | 561 | if (!tps) |
| @@ -569,7 +564,7 @@ static int __devinit tps_6507x_probe(struct i2c_client *client, · 2 unmodified lines | ||
| 569 | 564 | mutex_init(&tps->io_lock); |
| 570 | 565 | |
| 571 | 566 | /* common for all regulators */ |
| 572 | − tps->client = client; | |
| 567 | + tps->mfd = tps6507x_dev; | |
| 573 | 568 | |
| 574 | 569 | for (i = 0; i < TPS6507X_NUM_REGULATOR; i++, info++, init_data++) { |
| 575 | 570 | /* Register the regulators */ |
| @@ -578,15 +573,16 @@ static int __devinit tps_6507x_probe(struct i2c_client *client, · 2 unmodified lines | ||
| 578 | 573 | tps->desc[i].id = desc_id++; |
| 579 | 574 | tps->desc[i].n_voltages = num_voltages[i]; |
| 580 | 575 | tps->desc[i].ops = (i > TPS6507X_DCDC_3 ? |
| 581 | − &tps6507x_ldo_ops : &tps6507x_dcdc_ops); | |
| 576 | + &tps6507x_pmic_ldo_ops : &tps6507x_pmic_dcdc_ops); | |
| 582 | 577 | tps->desc[i].type = REGULATOR_VOLTAGE; |
| 583 | 578 | tps->desc[i].owner = THIS_MODULE; |
| 584 | 579 | |
| 585 | 580 | rdev = regulator_register(&tps->desc[i], |
| 586 | − &client->dev, init_data, tps); | |
| 581 | + tps6507x_dev->dev, init_data, tps); | |
| 587 | 582 | if (IS_ERR(rdev)) { |
| 588 | − dev_err(&client->dev, "failed to register %s\n", | |
| 589 | − id->name); | |
| 583 | + dev_err(tps6507x_dev->dev, | |
| 584 | + "failed to register %s regulator\n", | |
| 585 | + pdev->name); | |
| 590 | 586 | error = PTR_ERR(rdev); |
| 591 | 587 | goto fail; |
| 592 | 588 | } |
| @@ -595,7 +591,7 @@ static int __devinit tps_6507x_probe(struct i2c_client *client, · 2 unmodified lines | ||
| 595 | 591 | tps->rdev[i] = rdev; |
| 596 | 592 | } |
| 597 | 593 | |
| 598 | − i2c_set_clientdata(client, tps); | |
| 594 | + tps6507x_dev->pmic = tps; | |
| 599 | 595 | |
| 600 | 596 | return 0; |
| 601 | 597 | |
| @@ -608,19 +604,17 @@ fail: · 6 unmodified lines | ||
| 608 | 604 | } |
| 609 | 605 | |
| 610 | 606 | /** |
| 611 | − * tps_6507x_remove - TPS6507x driver i2c remove handler | |
| 607 | + * tps6507x_remove - TPS6507x driver i2c remove handler | |
| 612 | 608 | * @client: i2c driver client device structure |
| 613 | 609 | * |
| 614 | 610 | * Unregister TPS driver as an i2c client device driver |
| 615 | 611 | */ |
| 616 | −static int __devexit tps_6507x_remove(struct i2c_client *client) | |
| 612 | +static int __devexit tps6507x_pmic_remove(struct platform_device *pdev) | |
| 617 | 613 | { |
| 618 | − struct tps_pmic *tps = i2c_get_clientdata(client); | |
| 614 | + struct tps6507x_dev *tps6507x_dev = platform_get_drvdata(pdev); | |
| 615 | + struct tps6507x_pmic *tps = tps6507x_dev->pmic; | |
| 619 | 616 | int i; |
| 620 | 617 | |
| 621 | − /* clear the client data in i2c */ | |
| 622 | − i2c_set_clientdata(client, NULL); | |
| 623 | − | |
| 624 | 618 | for (i = 0; i < TPS6507X_NUM_REGULATOR; i++) |
| 625 | 619 | regulator_unregister(tps->rdev[i]); |
| 626 | 620 | |
| @@ -629,83 +623,38 @@ static int __devexit tps_6507x_remove(struct i2c_client *client) · 2 unmodified lines | ||
| 629 | 623 | return 0; |
| 630 | 624 | } |
| 631 | 625 | |
| 632 | −static const struct tps_info tps6507x_regs[] = { | |
| 633 | − { | |
| 634 | − .name = "VDCDC1", | |
| 635 | − .min_uV = 725000, | |
| 636 | − .max_uV = 3300000, | |
| 637 | − .table_len = ARRAY_SIZE(VDCDCx_VSEL_table), | |
| 638 | − .table = VDCDCx_VSEL_table, | |
| 639 | − }, | |
| 640 | − { | |
| 641 | − .name = "VDCDC2", | |
| 642 | − .min_uV = 725000, | |
| 643 | − .max_uV = 3300000, | |
| 644 | − .table_len = ARRAY_SIZE(VDCDCx_VSEL_table), | |
| 645 | − .table = VDCDCx_VSEL_table, | |
| 646 | − }, | |
| 647 | − { | |
| 648 | − .name = "VDCDC3", | |
| 649 | − .min_uV = 725000, | |
| 650 | − .max_uV = 3300000, | |
| 651 | − .table_len = ARRAY_SIZE(VDCDCx_VSEL_table), | |
| 652 | − .table = VDCDCx_VSEL_table, | |
| 653 | − }, | |
| 654 | − { | |
| 655 | − .name = "LDO1", | |
| 656 | − .min_uV = 1000000, | |
| 657 | − .max_uV = 3300000, | |
| 658 | − .table_len = ARRAY_SIZE(LDO1_VSEL_table), | |
| 659 | − .table = LDO1_VSEL_table, | |
| 660 | − }, | |
| 661 | − { | |
| 662 | − .name = "LDO2", | |
| 663 | − .min_uV = 725000, | |
| 664 | − .max_uV = 3300000, | |
| 665 | − .table_len = ARRAY_SIZE(LDO2_VSEL_table), | |
| 666 | − .table = LDO2_VSEL_table, | |
| 667 | − }, | |
| 668 | −}; | |
| 669 | − | |
| 670 | −static const struct i2c_device_id tps_6507x_id[] = { | |
| 671 | − {.name = "tps6507x", | |
| 672 | − .driver_data = (unsigned long) tps6507x_regs,}, | |
| 673 | − { }, | |
| 674 | −}; | |
| 675 | −MODULE_DEVICE_TABLE(i2c, tps_6507x_id); | |
| 676 | − | |
| 677 | −static struct i2c_driver tps_6507x_i2c_driver = { | |
| 626 | +static struct platform_driver tps6507x_pmic_driver = { | |
| 678 | 627 | .driver = { |
| 679 | − .name = "tps6507x", | |
| 628 | + .name = "tps6507x-pmic", | |
| 680 | 629 | .owner = THIS_MODULE, |
| 681 | 630 | }, |
| 682 | − .probe = tps_6507x_probe, | |
| 683 | − .remove = __devexit_p(tps_6507x_remove), | |
| 684 | − .id_table = tps_6507x_id, | |
| 631 | + .probe = tps6507x_pmic_probe, | |
| 632 | + .remove = __devexit_p(tps6507x_pmic_remove), | |
| 685 | 633 | }; |
| 686 | 634 | |
| 687 | 635 | /** |
| 688 | − * tps_6507x_init | |
| 636 | + * tps6507x_pmic_init | |
| 689 | 637 | * |
| 690 | 638 | * Module init function |
| 691 | 639 | */ |
| 692 | −static int __init tps_6507x_init(void) | |
| 640 | +static int __init tps6507x_pmic_init(void) | |
| 693 | 641 | { |
| 694 | − return i2c_add_driver(&tps_6507x_i2c_driver); | |
| 642 | + return platform_driver_register(&tps6507x_pmic_driver); | |
| 695 | 643 | } |
| 696 | −subsys_initcall(tps_6507x_init); | |
| 644 | +subsys_initcall(tps6507x_pmic_init); | |
| 697 | 645 | |
| 698 | 646 | /** |
| 699 | − * tps_6507x_cleanup | |
| 647 | + * tps6507x_pmic_cleanup | |
| 700 | 648 | * |
| 701 | 649 | * Module exit function |
| 702 | 650 | */ |
| 703 | −static void __exit tps_6507x_cleanup(void) | |
| 651 | +static void __exit tps6507x_pmic_cleanup(void) | |
| 704 | 652 | { |
| 705 | − i2c_del_driver(&tps_6507x_i2c_driver); | |
| 653 | + platform_driver_unregister(&tps6507x_pmic_driver); | |
| 706 | 654 | } |
| 707 | −module_exit(tps_6507x_cleanup); | |
| 655 | +module_exit(tps6507x_pmic_cleanup); | |
| 708 | 656 | |
| 709 | 657 | MODULE_AUTHOR("Texas Instruments"); |
| 710 | 658 | MODULE_DESCRIPTION("TPS6507x voltage regulator driver"); |
| 711 | 659 | MODULE_LICENSE("GPL v2"); |
| 660 | +MODULE_ALIAS("platform:tps6507x-pmic"); | |
| @@ -9,7 +9,7 @@ · 8 unmodified lines | ||
| 9 | 9 | #include <linux/init.h> |
| 10 | 10 | #include <linux/platform_device.h> |
| 11 | 11 | #include <linux/rtc.h> |
| 12 | −#include <linux/mfd/ab3100.h> | |
| 12 | +#include <linux/mfd/abx500.h> | |
| 13 | 13 | |
| 14 | 14 | /* Clock rate in Hz */ |
| 15 | 15 | #define AB3100_RTC_CLOCK_RATE 32768 |
| @@ -45,7 +45,6 @@ · 29 unmodified lines | ||
| 45 | 45 | */ |
| 46 | 46 | static int ab3100_rtc_set_mmss(struct device *dev, unsigned long secs) |
| 47 | 47 | { |
| 48 | − struct ab3100 *ab3100_data = dev_get_drvdata(dev); | |
| 49 | 48 | u8 regs[] = {AB3100_TI0, AB3100_TI1, AB3100_TI2, |
| 50 | 49 | AB3100_TI3, AB3100_TI4, AB3100_TI5}; |
| 51 | 50 | unsigned char buf[6]; |
| @@ -61,27 +60,26 @@ static int ab3100_rtc_set_mmss(struct device *dev, unsigned long secs) · 9 unmodified lines | ||
| 61 | 60 | buf[5] = (fat_time >> 40) & 0xFF; |
| 62 | 61 | |
| 63 | 62 | for (i = 0; i < 6; i++) { |
| 64 | − err = ab3100_set_register_interruptible(ab3100_data, | |
| 63 | + err = abx500_set_register_interruptible(dev, 0, | |
| 65 | 64 | regs[i], buf[i]); |
| 66 | 65 | if (err) |
| 67 | 66 | return err; |
| 68 | 67 | } |
| 69 | 68 | |
| 70 | 69 | /* Set the flag to mark that the clock is now set */ |
| 71 | − return ab3100_mask_and_set_register_interruptible(ab3100_data, | |
| 70 | + return abx500_mask_and_set_register_interruptible(dev, 0, | |
| 72 | 71 | AB3100_RTC, |
| 73 | − 0xFE, 0x01); | |
| 72 | + 0x01, 0x01); | |
| 74 | 73 | |
| 75 | 74 | } |
| 76 | 75 | |
| 77 | 76 | static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
| 78 | 77 | { |
| 79 | − struct ab3100 *ab3100_data = dev_get_drvdata(dev); | |
| 80 | 78 | unsigned long time; |
| 81 | 79 | u8 rtcval; |
| 82 | 80 | int err; |
| 83 | 81 | |
| 84 | − err = ab3100_get_register_interruptible(ab3100_data, | |
| 82 | + err = abx500_get_register_interruptible(dev, 0, | |
| 85 | 83 | AB3100_RTC, &rtcval); |
| 86 | 84 | if (err) |
| 87 | 85 | return err; |
| @@ -94,7 +92,7 @@ static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm) · 6 unmodified lines | ||
| 94 | 92 | u8 buf[6]; |
| 95 | 93 | |
| 96 | 94 | /* Read out time registers */ |
| 97 | − err = ab3100_get_register_page_interruptible(ab3100_data, | |
| 95 | + err = abx500_get_register_page_interruptible(dev, 0, | |
| 98 | 96 | AB3100_TI0, |
| 99 | 97 | buf, 6); |
| 100 | 98 | if (err != 0) |
| @@ -114,7 +112,6 @@ static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm) · 13 unmodified lines | ||
| 114 | 112 | |
| 115 | 113 | static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
| 116 | 114 | { |
| 117 | − struct ab3100 *ab3100_data = dev_get_drvdata(dev); | |
| 118 | 115 | unsigned long time; |
| 119 | 116 | u64 fat_time; |
| 120 | 117 | u8 buf[6]; |
| @@ -122,7 +119,7 @@ static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) · 1 unmodified line | ||
| 122 | 119 | int err; |
| 123 | 120 | |
| 124 | 121 | /* Figure out if alarm is enabled or not */ |
| 125 | − err = ab3100_get_register_interruptible(ab3100_data, | |
| 122 | + err = abx500_get_register_interruptible(dev, 0, | |
| 126 | 123 | AB3100_RTC, &rtcval); |
| 127 | 124 | if (err) |
| 128 | 125 | return err; |
| @@ -133,7 +130,7 @@ static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) · 4 unmodified lines | ||
| 133 | 130 | /* No idea how this could be represented */ |
| 134 | 131 | alarm->pending = 0; |
| 135 | 132 | /* Read out alarm registers, only 4 bytes */ |
| 136 | − err = ab3100_get_register_page_interruptible(ab3100_data, | |
| 133 | + err = abx500_get_register_page_interruptible(dev, 0, | |
| 137 | 134 | AB3100_AL0, buf, 4); |
| 138 | 135 | if (err) |
| 139 | 136 | return err; |
| @@ -148,7 +145,6 @@ static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) · 8 unmodified lines | ||
| 148 | 145 | |
| 149 | 146 | static int ab3100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
| 150 | 147 | { |
| 151 | − struct ab3100 *ab3100_data = dev_get_drvdata(dev); | |
| 152 | 148 | u8 regs[] = {AB3100_AL0, AB3100_AL1, AB3100_AL2, AB3100_AL3}; |
| 153 | 149 | unsigned char buf[4]; |
| 154 | 150 | unsigned long secs; |
| @@ -165,21 +161,19 @@ static int ab3100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) · 10 unmodified lines | ||
| 165 | 161 | |
| 166 | 162 | /* Set the alarm */ |
| 167 | 163 | for (i = 0; i < 4; i++) { |
| 168 | − err = ab3100_set_register_interruptible(ab3100_data, | |
| 164 | + err = abx500_set_register_interruptible(dev, 0, | |
| 169 | 165 | regs[i], buf[i]); |
| 170 | 166 | if (err) |
| 171 | 167 | return err; |
| 172 | 168 | } |
| 173 | 169 | /* Then enable the alarm */ |
| 174 | − return ab3100_mask_and_set_register_interruptible(ab3100_data, | |
| 175 | − AB3100_RTC, ~(1 << 2), | |
| 170 | + return abx500_mask_and_set_register_interruptible(dev, 0, | |
| 171 | + AB3100_RTC, (1 << 2), | |
| 176 | 172 | alarm->enabled << 2); |
| 177 | 173 | } |
| 178 | 174 | |
| 179 | 175 | static int ab3100_rtc_irq_enable(struct device *dev, unsigned int enabled) |
| 180 | 176 | { |
| 181 | − struct ab3100 *ab3100_data = dev_get_drvdata(dev); | |
| 182 | − | |
| 183 | 177 | /* |
| 184 | 178 | * It's not possible to enable/disable the alarm IRQ for this RTC. |
| 185 | 179 | * It does not actually trigger any IRQ: instead its only function is |
| @@ -188,12 +182,12 @@ static int ab3100_rtc_irq_enable(struct device *dev, unsigned int enabled) · 2 unmodified lines | ||
| 188 | 182 | * and need to be handled there instead. |
| 189 | 183 | */ |
| 190 | 184 | if (enabled) |
| 191 | − return ab3100_mask_and_set_register_interruptible(ab3100_data, | |
| 192 | − AB3100_RTC, ~(1 << 2), | |
| 185 | + return abx500_mask_and_set_register_interruptible(dev, 0, | |
| 186 | + AB3100_RTC, (1 << 2), | |
| 193 | 187 | 1 << 2); |
| 194 | 188 | else |
| 195 | − return ab3100_mask_and_set_register_interruptible(ab3100_data, | |
| 196 | − AB3100_RTC, ~(1 << 2), | |
| 189 | + return abx500_mask_and_set_register_interruptible(dev, 0, | |
| 190 | + AB3100_RTC, (1 << 2), | |
| 197 | 191 | 0); |
| 198 | 192 | } |
| 199 | 193 | |
| @@ -210,10 +204,9 @@ static int __init ab3100_rtc_probe(struct platform_device *pdev) · 10 unmodified lines | ||
| 210 | 204 | int err; |
| 211 | 205 | u8 regval; |
| 212 | 206 | struct rtc_device *rtc; |
| 213 | − struct ab3100 *ab3100_data = platform_get_drvdata(pdev); | |
| 214 | 207 | |
| 215 | 208 | /* The first RTC register needs special treatment */ |
| 216 | − err = ab3100_get_register_interruptible(ab3100_data, | |
| 209 | + err = abx500_get_register_interruptible(&pdev->dev, 0, | |
| 217 | 210 | AB3100_RTC, ®val); |
| 218 | 211 | if (err) { |
| 219 | 212 | dev_err(&pdev->dev, "unable to read RTC register\n"); |
| @@ -231,7 +224,7 @@ static int __init ab3100_rtc_probe(struct platform_device *pdev) · 11 unmodified lines | ||
| 231 | 224 | * This bit remains until RTC power is lost. |
| 232 | 225 | */ |
| 233 | 226 | regval = 1 | RTC_SETTING; |
| 234 | − err = ab3100_set_register_interruptible(ab3100_data, | |
| 227 | + err = abx500_set_register_interruptible(&pdev->dev, 0, | |
| 235 | 228 | AB3100_RTC, regval); |
| 236 | 229 | /* Ignore any error on this write */ |
| 237 | 230 | } |
| @@ -1,7 +1,7 @@ | ||
| 1 | 1 | /* |
| 2 | 2 | * RDC321x watchdog driver |
| 3 | 3 | * |
| 4 | − * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org> | |
| 4 | + * Copyright (C) 2007-2010 Florian Fainelli <florian@openwrt.org> | |
| 5 | 5 | * |
| 6 | 6 | * This driver is highly inspired from the cpu5_wdt driver |
| 7 | 7 | * |
| @@ -36,8 +36,7 @@ · 28 unmodified lines | ||
| 36 | 36 | #include <linux/watchdog.h> |
| 37 | 37 | #include <linux/io.h> |
| 38 | 38 | #include <linux/uaccess.h> |
| 39 | − | |
| 40 | −#include <asm/rdc321x_defs.h> | |
| 39 | +#include <linux/mfd/rdc321x.h> | |
| 41 | 40 | |
| 42 | 41 | #define RDC_WDT_MASK 0x80000000 /* Mask */ |
| 43 | 42 | #define RDC_WDT_EN 0x00800000 /* Enable bit */ |
| @@ -63,6 +62,8 @@ static struct { · 19 unmodified lines | ||
| 63 | 62 | int default_ticks; |
| 64 | 63 | unsigned long inuse; |
| 65 | 64 | spinlock_t lock; |
| 65 | + struct pci_dev *sb_pdev; | |
| 66 | + int base_reg; | |
| 66 | 67 | } rdc321x_wdt_device; |
| 67 | 68 | |
| 68 | 69 | /* generic helper functions */ |
| @@ -70,14 +71,18 @@ static struct { · 1 unmodified line | ||
| 70 | 71 | static void rdc321x_wdt_trigger(unsigned long unused) |
| 71 | 72 | { |
| 72 | 73 | unsigned long flags; |
| 74 | + u32 val; | |
| 73 | 75 | |
| 74 | 76 | if (rdc321x_wdt_device.running) |
| 75 | 77 | ticks--; |
| 76 | 78 | |
| 77 | 79 | /* keep watchdog alive */ |
| 78 | 80 | spin_lock_irqsave(&rdc321x_wdt_device.lock, flags); |
| 79 | − outl(RDC_WDT_EN | inl(RDC3210_CFGREG_DATA), | |
| 80 | − RDC3210_CFGREG_DATA); | |
| 81 | + pci_read_config_dword(rdc321x_wdt_device.sb_pdev, | |
| 82 | + rdc321x_wdt_device.base_reg, &val); | |
| 83 | + val |= RDC_WDT_EN; | |
| 84 | + pci_write_config_dword(rdc321x_wdt_device.sb_pdev, | |
| 85 | + rdc321x_wdt_device.base_reg, val); | |
| 81 | 86 | spin_unlock_irqrestore(&rdc321x_wdt_device.lock, flags); |
| 82 | 87 | |
| 83 | 88 | /* requeue?? */ |
| @@ -105,10 +110,13 @@ static void rdc321x_wdt_start(void) · 21 unmodified lines | ||
| 105 | 110 | |
| 106 | 111 | /* Clear the timer */ |
| 107 | 112 | spin_lock_irqsave(&rdc321x_wdt_device.lock, flags); |
| 108 | − outl(RDC_CLS_TMR, RDC3210_CFGREG_ADDR); | |
| 113 | + pci_write_config_dword(rdc321x_wdt_device.sb_pdev, | |
| 114 | + rdc321x_wdt_device.base_reg, RDC_CLS_TMR); | |
| 109 | 115 | |
| 110 | 116 | /* Enable watchdog and set the timeout to 81.92 us */ |
| 111 | − outl(RDC_WDT_EN | RDC_WDT_CNT, RDC3210_CFGREG_DATA); | |
| 117 | + pci_write_config_dword(rdc321x_wdt_device.sb_pdev, | |
| 118 | + rdc321x_wdt_device.base_reg, | |
| 119 | + RDC_WDT_EN | RDC_WDT_CNT); | |
| 112 | 120 | spin_unlock_irqrestore(&rdc321x_wdt_device.lock, flags); |
| 113 | 121 | |
| 114 | 122 | mod_timer(&rdc321x_wdt_device.timer, |
| @@ -148,7 +156,7 @@ static long rdc321x_wdt_ioctl(struct file *file, unsigned int cmd, · 33 unmodified lines | ||
| 148 | 156 | unsigned long arg) |
| 149 | 157 | { |
| 150 | 158 | void __user *argp = (void __user *)arg; |
| 151 | − unsigned int value; | |
| 159 | + u32 value; | |
| 152 | 160 | static const struct watchdog_info ident = { |
| 153 | 161 | .options = WDIOF_CARDRESET, |
| 154 | 162 | .identity = "RDC321x WDT", |
| @@ -162,9 +170,10 @@ static long rdc321x_wdt_ioctl(struct file *file, unsigned int cmd, · 7 unmodified lines | ||
| 162 | 170 | case WDIOC_GETSTATUS: |
| 163 | 171 | /* Read the value from the DATA register */ |
| 164 | 172 | spin_lock_irqsave(&rdc321x_wdt_device.lock, flags); |
| 165 | − value = inl(RDC3210_CFGREG_DATA); | |
| 173 | + pci_read_config_dword(rdc321x_wdt_device.sb_pdev, | |
| 174 | + rdc321x_wdt_device.base_reg, &value); | |
| 166 | 175 | spin_unlock_irqrestore(&rdc321x_wdt_device.lock, flags); |
| 167 | − if (copy_to_user(argp, &value, sizeof(int))) | |
| 176 | + if (copy_to_user(argp, &value, sizeof(u32))) | |
| 168 | 177 | return -EFAULT; |
| 169 | 178 | break; |
| 170 | 179 | case WDIOC_GETSUPPORT: |
| @@ -219,17 +228,35 @@ static struct miscdevice rdc321x_wdt_misc = { · 48 unmodified lines | ||
| 219 | 228 | static int __devinit rdc321x_wdt_probe(struct platform_device *pdev) |
| 220 | 229 | { |
| 221 | 230 | int err; |
| 231 | + struct resource *r; | |
| 232 | + struct rdc321x_wdt_pdata *pdata; | |
| 233 | + | |
| 234 | + pdata = pdev->dev.platform_data; | |
| 235 | + if (!pdata) { | |
| 236 | + dev_err(&pdev->dev, "no platform data supplied\n"); | |
| 237 | + return -ENODEV; | |
| 238 | + } | |
| 239 | + | |
| 240 | + r = platform_get_resource_byname(pdev, IORESOURCE_IO, "wdt-reg"); | |
| 241 | + if (!r) { | |
| 242 | + dev_err(&pdev->dev, "failed to get wdt-reg resource\n"); | |
| 243 | + return -ENODEV; | |
| 244 | + } | |
| 245 | + | |
| 246 | + rdc321x_wdt_device.sb_pdev = pdata->sb_pdev; | |
| 247 | + rdc321x_wdt_device.base_reg = r->start; | |
| 222 | 248 | |
| 223 | 249 | err = misc_register(&rdc321x_wdt_misc); |
| 224 | 250 | if (err < 0) { |
| 225 | − printk(KERN_ERR PFX "watchdog misc_register failed\n"); | |
| 251 | + dev_err(&pdev->dev, "misc_register failed\n"); | |
| 226 | 252 | return err; |
| 227 | 253 | } |
| 228 | 254 | |
| 229 | 255 | spin_lock_init(&rdc321x_wdt_device.lock); |
| 230 | 256 | |
| 231 | 257 | /* Reset the watchdog */ |
| 232 | − outl(RDC_WDT_RST, RDC3210_CFGREG_DATA); | |
| 258 | + pci_write_config_dword(rdc321x_wdt_device.sb_pdev, | |
| 259 | + rdc321x_wdt_device.base_reg, RDC_WDT_RST); | |
| 233 | 260 | |
| 234 | 261 | init_completion(&rdc321x_wdt_device.stop); |
| 235 | 262 | rdc321x_wdt_device.queue = 0; |
| @@ -240,7 +267,7 @@ static int __devinit rdc321x_wdt_probe(struct platform_device *pdev) · 4 unmodified lines | ||
| 240 | 267 | |
| 241 | 268 | rdc321x_wdt_device.default_ticks = ticks; |
| 242 | 269 | |
| 243 | − printk(KERN_INFO PFX "watchdog init success\n"); | |
| 270 | + dev_info(&pdev->dev, "watchdog init success\n"); | |
| 244 | 271 | |
| 245 | 272 | return 0; |
| 246 | 273 | } |
| @@ -0,0 +1,24 @@ | ||
| 1 | +/* linux/i2c/tps6507x-ts.h | |
| 2 | + * | |
| 3 | + * Functions to access TPS65070 touch screen chip. | |
| 4 | + * | |
| 5 | + * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com) | |
| 6 | + * | |
| 7 | + * | |
| 8 | + * For licencing details see kernel-base/COPYING | |
| 9 | + */ | |
| 10 | + | |
| 11 | +#ifndef __LINUX_I2C_TPS6507X_TS_H | |
| 12 | +#define __LINUX_I2C_TPS6507X_TS_H | |
| 13 | + | |
| 14 | +/* Board specific touch screen initial values */ | |
| 15 | +struct touchscreen_init_data { | |
| 16 | + int poll_period; /* ms */ | |
| 17 | + int vref; /* non-zero to leave vref on */ | |
| 18 | + __u16 min_pressure; /* min reading to be treated as a touch */ | |
| 19 | + __u16 vendor; | |
| 20 | + __u16 product; | |
| 21 | + __u16 version; | |
| 22 | +}; | |
| 23 | + | |
| 24 | +#endif /* __LINUX_I2C_TPS6507X_TS_H */ | |
| @@ -370,7 +370,7 @@ extern int pm860x_set_bits(struct i2c_client *, int, unsigned char, · 369 unmodified lines | ||
| 370 | 370 | unsigned char); |
| 371 | 371 | |
| 372 | 372 | extern int pm860x_device_init(struct pm860x_chip *chip, |
| 373 | − struct pm860x_platform_data *pdata); | |
| 374 | −extern void pm860x_device_exit(struct pm860x_chip *chip); | |
| 373 | + struct pm860x_platform_data *pdata) __devinit ; | |
| 374 | +extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ; | |
| 375 | 375 | |
| 376 | 376 | #endif /* __LINUX_MFD_88PM860X_H */ |
| @@ -1,262 +0,0 @@ | ||
| 1 | −/* | |
| 2 | − * Copyright (C) 2009 ST-Ericsson | |
| 3 | − * | |
| 4 | − * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> | |
| 5 | − * | |
| 6 | − * This program is free software; you can redistribute it and/or modify | |
| 7 | − * it under the terms of the GNU General Public License version 2, as | |
| 8 | − * published by the Free Software Foundation. | |
| 9 | − * | |
| 10 | − * AB4500 device core funtions, for client access | |
| 11 | − */ | |
| 12 | −#ifndef MFD_AB4500_H | |
| 13 | −#define MFD_AB4500_H | |
| 14 | − | |
| 15 | −#include <linux/device.h> | |
| 16 | − | |
| 17 | −/* | |
| 18 | − * AB4500 bank addresses | |
| 19 | − */ | |
| 20 | −#define AB4500_SYS_CTRL1_BLOCK 0x1 | |
| 21 | −#define AB4500_SYS_CTRL2_BLOCK 0x2 | |
| 22 | −#define AB4500_REGU_CTRL1 0x3 | |
| 23 | −#define AB4500_REGU_CTRL2 0x4 | |
| 24 | −#define AB4500_USB 0x5 | |
| 25 | −#define AB4500_TVOUT 0x6 | |
| 26 | −#define AB4500_DBI 0x7 | |
| 27 | −#define AB4500_ECI_AV_ACC 0x8 | |
| 28 | −#define AB4500_RESERVED 0x9 | |
| 29 | −#define AB4500_GPADC 0xA | |
| 30 | −#define AB4500_CHARGER 0xB | |
| 31 | −#define AB4500_GAS_GAUGE 0xC | |
| 32 | −#define AB4500_AUDIO 0xD | |
| 33 | −#define AB4500_INTERRUPT 0xE | |
| 34 | −#define AB4500_RTC 0xF | |
| 35 | −#define AB4500_MISC 0x10 | |
| 36 | −#define AB4500_DEBUG 0x12 | |
| 37 | −#define AB4500_PROD_TEST 0x13 | |
| 38 | −#define AB4500_OTP_EMUL 0x15 | |
| 39 | − | |
| 40 | −/* | |
| 41 | − * System control 1 register offsets. | |
| 42 | − * Bank = 0x01 | |
| 43 | − */ | |
| 44 | −#define AB4500_TURNON_STAT_REG 0x0100 | |
| 45 | −#define AB4500_RESET_STAT_REG 0x0101 | |
| 46 | −#define AB4500_PONKEY1_PRESS_STAT_REG 0x0102 | |
| 47 | − | |
| 48 | −#define AB4500_FSM_STAT1_REG 0x0140 | |
| 49 | −#define AB4500_FSM_STAT2_REG 0x0141 | |
| 50 | −#define AB4500_SYSCLK_REQ_STAT_REG 0x0142 | |
| 51 | −#define AB4500_USB_STAT1_REG 0x0143 | |
| 52 | −#define AB4500_USB_STAT2_REG 0x0144 | |
| 53 | −#define AB4500_STATUS_SPARE1_REG 0x0145 | |
| 54 | −#define AB4500_STATUS_SPARE2_REG 0x0146 | |
| 55 | − | |
| 56 | −#define AB4500_CTRL1_REG 0x0180 | |
| 57 | −#define AB4500_CTRL2_REG 0x0181 | |
| 58 | − | |
| 59 | −/* | |
| 60 | − * System control 2 register offsets. | |
| 61 | − * bank = 0x02 | |
| 62 | − */ | |
| 63 | −#define AB4500_CTRL3_REG 0x0200 | |
| 64 | −#define AB4500_MAIN_WDOG_CTRL_REG 0x0201 | |
| 65 | −#define AB4500_MAIN_WDOG_TIMER_REG 0x0202 | |
| 66 | −#define AB4500_LOW_BAT_REG 0x0203 | |
| 67 | −#define AB4500_BATT_OK_REG 0x0204 | |
| 68 | −#define AB4500_SYSCLK_TIMER_REG 0x0205 | |
| 69 | −#define AB4500_SMPSCLK_CTRL_REG 0x0206 | |
| 70 | −#define AB4500_SMPSCLK_SEL1_REG 0x0207 | |
| 71 | −#define AB4500_SMPSCLK_SEL2_REG 0x0208 | |
| 72 | −#define AB4500_SMPSCLK_SEL3_REG 0x0209 | |
| 73 | −#define AB4500_SYSULPCLK_CONF_REG 0x020A | |
| 74 | −#define AB4500_SYSULPCLK_CTRL1_REG 0x020B | |
| 75 | −#define AB4500_SYSCLK_CTRL_REG 0x020C | |
| 76 | −#define AB4500_SYSCLK_REQ1_VALID_REG 0x020D | |
| 77 | −#define AB4500_SYSCLK_REQ_VALID_REG 0x020E | |
| 78 | −#define AB4500_SYSCTRL_SPARE_REG 0x020F | |
| 79 | −#define AB4500_PAD_CONF_REG 0x0210 | |
| 80 | − | |
| 81 | −/* | |
| 82 | − * Regu control1 register offsets | |
| 83 | − * Bank = 0x03 | |
| 84 | − */ | |
| 85 | −#define AB4500_REGU_SERIAL_CTRL1_REG 0x0300 | |
| 86 | −#define AB4500_REGU_SERIAL_CTRL2_REG 0x0301 | |
| 87 | −#define AB4500_REGU_SERIAL_CTRL3_REG 0x0302 | |
| 88 | −#define AB4500_REGU_REQ_CTRL1_REG 0x0303 | |
| 89 | −#define AB4500_REGU_REQ_CTRL2_REG 0x0304 | |
| 90 | −#define AB4500_REGU_REQ_CTRL3_REG 0x0305 | |
| 91 | −#define AB4500_REGU_REQ_CTRL4_REG 0x0306 | |
| 92 | −#define AB4500_REGU_MISC1_REG 0x0380 | |
| 93 | −#define AB4500_REGU_OTGSUPPLY_CTRL_REG 0x0381 | |
| 94 | −#define AB4500_REGU_VUSB_CTRL_REG 0x0382 | |
| 95 | −#define AB4500_REGU_VAUDIO_SUPPLY_REG 0x0383 | |
| 96 | −#define AB4500_REGU_CTRL1_SPARE_REG 0x0384 | |
| 97 | − | |
| 98 | −/* | |
| 99 | − * Regu control2 Vmod register offsets | |
| 100 | − */ | |
| 101 | −#define AB4500_REGU_VMOD_REGU_REG 0x0440 | |
| 102 | −#define AB4500_REGU_VMOD_SEL1_REG 0x0441 | |
| 103 | −#define AB4500_REGU_VMOD_SEL2_REG 0x0442 | |
| 104 | −#define AB4500_REGU_CTRL_DISCH_REG 0x0443 | |
| 105 | −#define AB4500_REGU_CTRL_DISCH2_REG 0x0444 | |
| 106 | − | |
| 107 | −/* | |
| 108 | − * USB/ULPI register offsets | |
| 109 | − * Bank : 0x5 | |
| 110 | − */ | |
| 111 | −#define AB4500_USB_LINE_STAT_REG 0x0580 | |
| 112 | −#define AB4500_USB_LINE_CTRL1_REG 0x0581 | |
| 113 | −#define AB4500_USB_LINE_CTRL2_REG 0x0582 | |
| 114 | −#define AB4500_USB_LINE_CTRL3_REG 0x0583 | |
| 115 | −#define AB4500_USB_LINE_CTRL4_REG 0x0584 | |
| 116 | −#define AB4500_USB_LINE_CTRL5_REG 0x0585 | |
| 117 | −#define AB4500_USB_OTG_CTRL_REG 0x0587 | |
| 118 | −#define AB4500_USB_OTG_STAT_REG 0x0588 | |
| 119 | −#define AB4500_USB_OTG_STAT_REG 0x0588 | |
| 120 | −#define AB4500_USB_CTRL_SPARE_REG 0x0589 | |
| 121 | −#define AB4500_USB_PHY_CTRL_REG 0x058A | |
| 122 | − | |
| 123 | −/* | |
| 124 | − * TVOUT / CTRL register offsets | |
| 125 | − * Bank : 0x06 | |
| 126 | − */ | |
| 127 | −#define AB4500_TVOUT_CTRL_REG 0x0680 | |
| 128 | − | |
| 129 | −/* | |
| 130 | − * DBI register offsets | |
| 131 | − * Bank : 0x07 | |
| 132 | − */ | |
| 133 | −#define AB4500_DBI_REG1_REG 0x0700 | |
| 134 | −#define AB4500_DBI_REG2_REG 0x0701 | |
| 135 | − | |
| 136 | −/* | |
| 137 | − * ECI regsiter offsets | |
| 138 | − * Bank : 0x08 | |
| 139 | − */ | |
| 140 | −#define AB4500_ECI_CTRL_REG 0x0800 | |
| 141 | −#define AB4500_ECI_HOOKLEVEL_REG 0x0801 | |
| 142 | −#define AB4500_ECI_DATAOUT_REG 0x0802 | |
| 143 | −#define AB4500_ECI_DATAIN_REG 0x0803 | |
| 144 | − | |
| 145 | −/* | |
| 146 | − * AV Connector register offsets | |
| 147 | − * Bank : 0x08 | |
| 148 | − */ | |
| 149 | −#define AB4500_AV_CONN_REG 0x0840 | |
| 150 | − | |
| 151 | −/* | |
| 152 | − * Accessory detection register offsets | |
| 153 | − * Bank : 0x08 | |
| 154 | − */ | |
| 155 | −#define AB4500_ACC_DET_DB1_REG 0x0880 | |
| 156 | −#define AB4500_ACC_DET_DB2_REG 0x0881 | |
| 157 | − | |
| 158 | −/* | |
| 159 | − * GPADC register offsets | |
| 160 | − * Bank : 0x0A | |
| 161 | − */ | |
| 162 | −#define AB4500_GPADC_CTRL1_REG 0x0A00 | |
| 163 | −#define AB4500_GPADC_CTRL2_REG 0x0A01 | |
| 164 | −#define AB4500_GPADC_CTRL3_REG 0x0A02 | |
| 165 | −#define AB4500_GPADC_AUTO_TIMER_REG 0x0A03 | |
| 166 | −#define AB4500_GPADC_STAT_REG 0x0A04 | |
| 167 | −#define AB4500_GPADC_MANDATAL_REG 0x0A05 | |
| 168 | −#define AB4500_GPADC_MANDATAH_REG 0x0A06 | |
| 169 | −#define AB4500_GPADC_AUTODATAL_REG 0x0A07 | |
| 170 | −#define AB4500_GPADC_AUTODATAH_REG 0x0A08 | |
| 171 | −#define AB4500_GPADC_MUX_CTRL_REG 0x0A09 | |
| 172 | − | |
| 173 | −/* | |
| 174 | − * Charger / status register offfsets | |
| 175 | − * Bank : 0x0B | |
| 176 | − */ | |
| 177 | −#define AB4500_CH_STATUS1_REG 0x0B00 | |
| 178 | −#define AB4500_CH_STATUS2_REG 0x0B01 | |
| 179 | −#define AB4500_CH_USBCH_STAT1_REG 0x0B02 | |
| 180 | −#define AB4500_CH_USBCH_STAT2_REG 0x0B03 | |
| 181 | −#define AB4500_CH_FSM_STAT_REG 0x0B04 | |
| 182 | −#define AB4500_CH_STAT_REG 0x0B05 | |
| 183 | − | |
| 184 | −/* | |
| 185 | − * Charger / control register offfsets | |
| 186 | − * Bank : 0x0B | |
| 187 | − */ | |
| 188 | −#define AB4500_CH_VOLT_LVL_REG 0x0B40 | |
| 189 | − | |
| 190 | −/* | |
| 191 | − * Charger / main control register offfsets | |
| 192 | − * Bank : 0x0B | |
| 193 | − */ | |
| 194 | −#define AB4500_MCH_CTRL1 0x0B80 | |
| 195 | −#define AB4500_MCH_CTRL2 0x0B81 | |
| 196 | −#define AB4500_MCH_IPT_CURLVL_REG 0x0B82 | |
| 197 | −#define AB4500_CH_WD_REG 0x0B83 | |
| 198 | − | |
| 199 | −/* | |
| 200 | − * Charger / USB control register offsets | |
| 201 | − * Bank : 0x0B | |
| 202 | − */ | |
| 203 | −#define AB4500_USBCH_CTRL1_REG 0x0BC0 | |
| 204 | −#define AB4500_USBCH_CTRL2_REG 0x0BC1 | |
| 205 | −#define AB4500_USBCH_IPT_CRNTLVL_REG 0x0BC2 | |
| 206 | − | |
| 207 | −/* | |
| 208 | − * RTC bank register offsets | |
| 209 | − * Bank : 0xF | |
| 210 | − */ | |
| 211 | −#define AB4500_RTC_SOFF_STAT_REG 0x0F00 | |
| 212 | −#define AB4500_RTC_CC_CONF_REG 0x0F01 | |
| 213 | −#define AB4500_RTC_READ_REQ_REG 0x0F02 | |
| 214 | −#define AB4500_RTC_WATCH_TSECMID_REG 0x0F03 | |
| 215 | −#define AB4500_RTC_WATCH_TSECHI_REG 0x0F04 | |
| 216 | −#define AB4500_RTC_WATCH_TMIN_LOW_REG 0x0F05 | |
| 217 | −#define AB4500_RTC_WATCH_TMIN_MID_REG 0x0F06 | |
| 218 | −#define AB4500_RTC_WATCH_TMIN_HI_REG 0x0F07 | |
| 219 | −#define AB4500_RTC_ALRM_MIN_LOW_REG 0x0F08 | |
| 220 | −#define AB4500_RTC_ALRM_MIN_MID_REG 0x0F09 | |
| 221 | −#define AB4500_RTC_ALRM_MIN_HI_REG 0x0F0A | |
| 222 | −#define AB4500_RTC_STAT_REG 0x0F0B | |
| 223 | −#define AB4500_RTC_BKUP_CHG_REG 0x0F0C | |
| 224 | −#define AB4500_RTC_FORCE_BKUP_REG 0x0F0D | |
| 225 | −#define AB4500_RTC_CALIB_REG 0x0F0E | |
| 226 | −#define AB4500_RTC_SWITCH_STAT_REG 0x0F0F | |
| 227 | − | |
| 228 | −/* | |
| 229 | − * PWM Out generators | |
| 230 | − * Bank: 0x10 | |
| 231 | − */ | |
| 232 | −#define AB4500_PWM_OUT_CTRL1_REG 0x1060 | |
| 233 | −#define AB4500_PWM_OUT_CTRL2_REG 0x1061 | |
| 234 | −#define AB4500_PWM_OUT_CTRL3_REG 0x1062 | |
| 235 | −#define AB4500_PWM_OUT_CTRL4_REG 0x1063 | |
| 236 | −#define AB4500_PWM_OUT_CTRL5_REG 0x1064 | |
| 237 | −#define AB4500_PWM_OUT_CTRL6_REG 0x1065 | |
| 238 | −#define AB4500_PWM_OUT_CTRL7_REG 0x1066 | |
| 239 | − | |
| 240 | −#define AB4500_I2C_PAD_CTRL_REG 0x1067 | |
| 241 | −#define AB4500_REV_REG 0x1080 | |
| 242 | − | |
| 243 | −/** | |
| 244 | − * struct ab4500 | |
| 245 | − * @spi: spi device structure | |
| 246 | − * @tx_buf: transmit buffer | |
| 247 | − * @rx_buf: receive buffer | |
| 248 | − * @lock: sync primitive | |
| 249 | − */ | |
| 250 | −struct ab4500 { | |
| 251 | − struct spi_device *spi; | |
| 252 | − unsigned long tx_buf[4]; | |
| 253 | − unsigned long rx_buf[4]; | |
| 254 | − struct mutex lock; | |
| 255 | −}; | |
| 256 | − | |
| 257 | −int ab4500_write(struct ab4500 *ab4500, unsigned char block, | |
| 258 | − unsigned long addr, unsigned char data); | |
| 259 | −int ab4500_read(struct ab4500 *ab4500, unsigned char block, | |
| 260 | − unsigned long addr); | |
| 261 | − | |
| 262 | −#endif /* MFD_AB4500_H */ | |
| @@ -0,0 +1,128 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | + * | |
| 4 | + * License Terms: GNU General Public License v2 | |
| 5 | + * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
| 6 | + */ | |
| 7 | +#ifndef MFD_AB8500_H | |
| 8 | +#define MFD_AB8500_H | |
| 9 | + | |
| 10 | +#include <linux/device.h> | |
| 11 | + | |
| 12 | +/* | |
| 13 | + * Interrupts | |
| 14 | + */ | |
| 15 | + | |
| 16 | +#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 | |
| 17 | +#define AB8500_INT_UN_PLUG_TV_DET 1 | |
| 18 | +#define AB8500_INT_PLUG_TV_DET 2 | |
| 19 | +#define AB8500_INT_TEMP_WARM 3 | |
| 20 | +#define AB8500_INT_PON_KEY2DB_F 4 | |
| 21 | +#define AB8500_INT_PON_KEY2DB_R 5 | |
| 22 | +#define AB8500_INT_PON_KEY1DB_F 6 | |
| 23 | +#define AB8500_INT_PON_KEY1DB_R 7 | |
| 24 | +#define AB8500_INT_BATT_OVV 8 | |
| 25 | +#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 | |
| 26 | +#define AB8500_INT_MAIN_CH_PLUG_DET 11 | |
| 27 | +#define AB8500_INT_USB_ID_DET_F 12 | |
| 28 | +#define AB8500_INT_USB_ID_DET_R 13 | |
| 29 | +#define AB8500_INT_VBUS_DET_F 14 | |
| 30 | +#define AB8500_INT_VBUS_DET_R 15 | |
| 31 | +#define AB8500_INT_VBUS_CH_DROP_END 16 | |
| 32 | +#define AB8500_INT_RTC_60S 17 | |
| 33 | +#define AB8500_INT_RTC_ALARM 18 | |
| 34 | +#define AB8500_INT_BAT_CTRL_INDB 20 | |
| 35 | +#define AB8500_INT_CH_WD_EXP 21 | |
| 36 | +#define AB8500_INT_VBUS_OVV 22 | |
| 37 | +#define AB8500_INT_MAIN_CH_DROP_END 23 | |
| 38 | +#define AB8500_INT_CCN_CONV_ACC 24 | |
| 39 | +#define AB8500_INT_INT_AUD 25 | |
| 40 | +#define AB8500_INT_CCEOC 26 | |
| 41 | +#define AB8500_INT_CC_INT_CALIB 27 | |
| 42 | +#define AB8500_INT_LOW_BAT_F 28 | |
| 43 | +#define AB8500_INT_LOW_BAT_R 29 | |
| 44 | +#define AB8500_INT_BUP_CHG_NOT_OK 30 | |
| 45 | +#define AB8500_INT_BUP_CHG_OK 31 | |
| 46 | +#define AB8500_INT_GP_HW_ADC_CONV_END 32 | |
| 47 | +#define AB8500_INT_ACC_DETECT_1DB_F 33 | |
| 48 | +#define AB8500_INT_ACC_DETECT_1DB_R 34 | |
| 49 | +#define AB8500_INT_ACC_DETECT_22DB_F 35 | |
| 50 | +#define AB8500_INT_ACC_DETECT_22DB_R 36 | |
| 51 | +#define AB8500_INT_ACC_DETECT_21DB_F 37 | |
| 52 | +#define AB8500_INT_ACC_DETECT_21DB_R 38 | |
| 53 | +#define AB8500_INT_GP_SW_ADC_CONV_END 39 | |
| 54 | +#define AB8500_INT_BTEMP_LOW 72 | |
| 55 | +#define AB8500_INT_BTEMP_LOW_MEDIUM 73 | |
| 56 | +#define AB8500_INT_BTEMP_MEDIUM_HIGH 74 | |
| 57 | +#define AB8500_INT_BTEMP_HIGH 75 | |
| 58 | +#define AB8500_INT_USB_CHARGER_NOT_OK 81 | |
| 59 | +#define AB8500_INT_ID_WAKEUP_R 82 | |
| 60 | +#define AB8500_INT_ID_DET_R1R 84 | |
| 61 | +#define AB8500_INT_ID_DET_R2R 85 | |
| 62 | +#define AB8500_INT_ID_DET_R3R 86 | |
| 63 | +#define AB8500_INT_ID_DET_R4R 87 | |
| 64 | +#define AB8500_INT_ID_WAKEUP_F 88 | |
| 65 | +#define AB8500_INT_ID_DET_R1F 90 | |
| 66 | +#define AB8500_INT_ID_DET_R2F 91 | |
| 67 | +#define AB8500_INT_ID_DET_R3F 92 | |
| 68 | +#define AB8500_INT_ID_DET_R4F 93 | |
| 69 | +#define AB8500_INT_USB_CHG_DET_DONE 94 | |
| 70 | +#define AB8500_INT_USB_CH_TH_PROT_F 96 | |
| 71 | +#define AB8500_INT_USB_CH_TH_PROP_R 97 | |
| 72 | +#define AB8500_INT_MAIN_CH_TH_PROP_F 98 | |
| 73 | +#define AB8500_INT_MAIN_CH_TH_PROT_R 99 | |
| 74 | +#define AB8500_INT_USB_CHARGER_NOT_OKF 103 | |
| 75 | + | |
| 76 | +#define AB8500_NR_IRQS 104 | |
| 77 | +#define AB8500_NUM_IRQ_REGS 13 | |
| 78 | + | |
| 79 | +/** | |
| 80 | + * struct ab8500 - ab8500 internal structure | |
| 81 | + * @dev: parent device | |
| 82 | + * @lock: read/write operations lock | |
| 83 | + * @irq_lock: genirq bus lock | |
| 84 | + * @revision: chip revision | |
| 85 | + * @irq: irq line | |
| 86 | + * @write: register write | |
| 87 | + * @read: register read | |
| 88 | + * @rx_buf: rx buf for SPI | |
| 89 | + * @tx_buf: tx buf for SPI | |
| 90 | + * @mask: cache of IRQ regs for bus lock | |
| 91 | + * @oldmask: cache of previous IRQ regs for bus lock | |
| 92 | + */ | |
| 93 | +struct ab8500 { | |
| 94 | + struct device *dev; | |
| 95 | + struct mutex lock; | |
| 96 | + struct mutex irq_lock; | |
| 97 | + int revision; | |
| 98 | + int irq_base; | |
| 99 | + int irq; | |
| 100 | + | |
| 101 | + int (*write) (struct ab8500 *a8500, u16 addr, u8 data); | |
| 102 | + int (*read) (struct ab8500 *a8500, u16 addr); | |
| 103 | + | |
| 104 | + unsigned long tx_buf[4]; | |
| 105 | + unsigned long rx_buf[4]; | |
| 106 | + | |
| 107 | + u8 mask[AB8500_NUM_IRQ_REGS]; | |
| 108 | + u8 oldmask[AB8500_NUM_IRQ_REGS]; | |
| 109 | +}; | |
| 110 | + | |
| 111 | +/** | |
| 112 | + * struct ab8500_platform_data - AB8500 platform data | |
| 113 | + * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used | |
| 114 | + * @init: board-specific initialization after detection of ab8500 | |
| 115 | + */ | |
| 116 | +struct ab8500_platform_data { | |
| 117 | + int irq_base; | |
| 118 | + void (*init) (struct ab8500 *); | |
| 119 | +}; | |
| 120 | + | |
| 121 | +extern int ab8500_write(struct ab8500 *a8500, u16 addr, u8 data); | |
| 122 | +extern int ab8500_read(struct ab8500 *a8500, u16 addr); | |
| 123 | +extern int ab8500_set_bits(struct ab8500 *a8500, u16 addr, u8 mask, u8 data); | |
| 124 | + | |
| 125 | +extern int __devinit ab8500_init(struct ab8500 *ab8500); | |
| 126 | +extern int __devexit ab8500_exit(struct ab8500 *ab8500); | |
| 127 | + | |
| 128 | +#endif /* MFD_AB8500_H */ | |
| @@ -3,17 +3,37 @@ · 2 unmodified lines | ||
| 3 | 3 | * License terms: GNU General Public License (GPL) version 2 |
| 4 | 4 | * AB3100 core access functions |
| 5 | 5 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 6 | + * | |
| 7 | + * ABX500 core access functions. | |
| 8 | + * The abx500 interface is used for the Analog Baseband chip | |
| 9 | + * ab3100, ab3550, ab5500 and possibly comming. It is not used for | |
| 10 | + * ab4500 and ab8500 since they are another family of chip. | |
| 11 | + * | |
| 12 | + * Author: Mattias Wallin <mattias.wallin@stericsson.com> | |
| 13 | + * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> | |
| 14 | + * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> | |
| 15 | + * Author: Rickard Andersson <rickard.andersson@stericsson.com> | |
| 6 | 16 | */ |
| 7 | 17 | |
| 8 | 18 | #include <linux/device.h> |
| 9 | 19 | #include <linux/regulator/machine.h> |
| 10 | 20 | |
| 11 | −#ifndef MFD_AB3100_H | |
| 12 | −#define MFD_AB3100_H | |
| 21 | +#ifndef MFD_ABX500_H | |
| 22 | +#define MFD_ABX500_H | |
| 13 | 23 | |
| 14 | −#define ABUNKNOWN 0 | |
| 15 | −#define AB3000 1 | |
| 16 | −#define AB3100 2 | |
| 24 | +#define AB3100_P1A 0xc0 | |
| 25 | +#define AB3100_P1B 0xc1 | |
| 26 | +#define AB3100_P1C 0xc2 | |
| 27 | +#define AB3100_P1D 0xc3 | |
| 28 | +#define AB3100_P1E 0xc4 | |
| 29 | +#define AB3100_P1F 0xc5 | |
| 30 | +#define AB3100_P1G 0xc6 | |
| 31 | +#define AB3100_R2A 0xc7 | |
| 32 | +#define AB3100_R2B 0xc8 | |
| 33 | +#define AB3550_P1A 0x10 | |
| 34 | +#define AB5500_1_0 0x20 | |
| 35 | +#define AB5500_2_0 0x21 | |
| 36 | +#define AB5500_2_1 0x22 | |
| 17 | 37 | |
| 18 | 38 | /* |
| 19 | 39 | * AB3100, EVENTA1, A2 and A3 event register flags |
| @@ -89,7 +109,7 @@ struct ab3100 { · 69 unmodified lines | ||
| 89 | 109 | char chip_name[32]; |
| 90 | 110 | u8 chip_id; |
| 91 | 111 | struct blocking_notifier_head event_subscribers; |
| 92 | − u32 startup_events; | |
| 112 | + u8 startup_events[3]; | |
| 93 | 113 | bool startup_events_read; |
| 94 | 114 | }; |
| 95 | 115 | |
| @@ -112,18 +132,102 @@ struct ab3100_platform_data { · 16 unmodified lines | ||
| 112 | 132 | int external_voltage; |
| 113 | 133 | }; |
| 114 | 134 | |
| 115 | −int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval); | |
| 116 | −int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval); | |
| 117 | −int ab3100_get_register_page_interruptible(struct ab3100 *ab3100, | |
| 118 | − u8 first_reg, u8 *regvals, u8 numregs); | |
| 119 | −int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100, | |
| 120 | − u8 reg, u8 andmask, u8 ormask); | |
| 121 | −u8 ab3100_get_chip_type(struct ab3100 *ab3100); | |
| 122 | 135 | int ab3100_event_register(struct ab3100 *ab3100, |
| 123 | 136 | struct notifier_block *nb); |
| 124 | 137 | int ab3100_event_unregister(struct ab3100 *ab3100, |
| 125 | 138 | struct notifier_block *nb); |
| 126 | −int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100, | |
| 127 | − u32 *fatevent); | |
| 128 | 139 | |
| 140 | +/* AB3550, STR register flags */ | |
| 141 | +#define AB3550_STR_ONSWA (0x01) | |
| 142 | +#define AB3550_STR_ONSWB (0x02) | |
| 143 | +#define AB3550_STR_ONSWC (0x04) | |
| 144 | +#define AB3550_STR_DCIO (0x08) | |
| 145 | +#define AB3550_STR_BOOT_MODE (0x10) | |
| 146 | +#define AB3550_STR_SIM_OFF (0x20) | |
| 147 | +#define AB3550_STR_BATT_REMOVAL (0x40) | |
| 148 | +#define AB3550_STR_VBUS (0x80) | |
| 149 | + | |
| 150 | +/* Interrupt mask registers */ | |
| 151 | +#define AB3550_IMR1 0x29 | |
| 152 | +#define AB3550_IMR2 0x2a | |
| 153 | +#define AB3550_IMR3 0x2b | |
| 154 | +#define AB3550_IMR4 0x2c | |
| 155 | +#define AB3550_IMR5 0x2d | |
| 156 | + | |
| 157 | +enum ab3550_devid { | |
| 158 | + AB3550_DEVID_ADC, | |
| 159 | + AB3550_DEVID_DAC, | |
| 160 | + AB3550_DEVID_LEDS, | |
| 161 | + AB3550_DEVID_POWER, | |
| 162 | + AB3550_DEVID_REGULATORS, | |
| 163 | + AB3550_DEVID_SIM, | |
| 164 | + AB3550_DEVID_UART, | |
| 165 | + AB3550_DEVID_RTC, | |
| 166 | + AB3550_DEVID_CHARGER, | |
| 167 | + AB3550_DEVID_FUELGAUGE, | |
| 168 | + AB3550_DEVID_VIBRATOR, | |
| 169 | + AB3550_DEVID_CODEC, | |
| 170 | + AB3550_NUM_DEVICES, | |
| 171 | +}; | |
| 172 | + | |
| 173 | +/** | |
| 174 | + * struct abx500_init_setting | |
| 175 | + * Initial value of the registers for driver to use during setup. | |
| 176 | + */ | |
| 177 | +struct abx500_init_settings { | |
| 178 | + u8 bank; | |
| 179 | + u8 reg; | |
| 180 | + u8 setting; | |
| 181 | +}; | |
| 182 | + | |
| 183 | +/** | |
| 184 | + * struct ab3550_platform_data | |
| 185 | + * Data supplied to initialize board connections to the AB3550 | |
| 186 | + */ | |
| 187 | +struct ab3550_platform_data { | |
| 188 | + struct {unsigned int base; unsigned int count; } irq; | |
| 189 | + void *dev_data[AB3550_NUM_DEVICES]; | |
| 190 | + size_t dev_data_sz[AB3550_NUM_DEVICES]; | |
| 191 | + struct abx500_init_settings *init_settings; | |
| 192 | + unsigned int init_settings_sz; | |
| 193 | +}; | |
| 194 | + | |
| 195 | +int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, | |
| 196 | + u8 value); | |
| 197 | +int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, | |
| 198 | + u8 *value); | |
| 199 | +int abx500_get_register_page_interruptible(struct device *dev, u8 bank, | |
| 200 | + u8 first_reg, u8 *regvals, u8 numregs); | |
| 201 | +int abx500_set_register_page_interruptible(struct device *dev, u8 bank, | |
| 202 | + u8 first_reg, u8 *regvals, u8 numregs); | |
| 203 | +/** | |
| 204 | + * abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a | |
| 205 | + * target register | |
| 206 | + * | |
| 207 | + * @dev: The AB sub device. | |
| 208 | + * @bank: The i2c bank number. | |
| 209 | + * @bitmask: The bit mask to use. | |
| 210 | + * @bitvalues: The new bit values. | |
| 211 | + * | |
| 212 | + * Updates the value of an AB register: | |
| 213 | + * value -> ((value & ~bitmask) | (bitvalues & bitmask)) | |
| 214 | + */ | |
| 215 | +int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank, | |
| 216 | + u8 reg, u8 bitmask, u8 bitvalues); | |
| 217 | +int abx500_get_chip_id(struct device *dev); | |
| 218 | +int abx500_event_registers_startup_state_get(struct device *dev, u8 *event); | |
| 219 | +int abx500_startup_irq_enabled(struct device *dev, unsigned int irq); | |
| 220 | + | |
| 221 | +struct abx500_ops { | |
| 222 | + int (*get_chip_id) (struct device *); | |
| 223 | + int (*get_register) (struct device *, u8, u8, u8 *); | |
| 224 | + int (*set_register) (struct device *, u8, u8, u8); | |
| 225 | + int (*get_register_page) (struct device *, u8, u8, u8 *, u8); | |
| 226 | + int (*set_register_page) (struct device *, u8, u8, u8 *, u8); | |
| 227 | + int (*mask_and_set_register) (struct device *, u8, u8, u8, u8); | |
| 228 | + int (*event_registers_startup_state_get) (struct device *, u8 *); | |
| 229 | + int (*startup_irq_enabled) (struct device *, unsigned int); | |
| 230 | +}; | |
| 231 | + | |
| 232 | +int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops); | |
| 129 | 233 | #endif |
| @@ -0,0 +1,54 @@ | ||
| 1 | +/* | |
| 2 | + * Common Definitions for Janz MODULbus devices | |
| 3 | + * | |
| 4 | + * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu> | |
| 5 | + * | |
| 6 | + * This program is free software; you can redistribute it and/or modify it | |
| 7 | + * under the terms of the GNU General Public License as published by the | |
| 8 | + * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | + * option) any later version. | |
| 10 | + */ | |
| 11 | + | |
| 12 | +#ifndef JANZ_H | |
| 13 | +#define JANZ_H | |
| 14 | + | |
| 15 | +struct janz_platform_data { | |
| 16 | + /* MODULbus Module Number */ | |
| 17 | + unsigned int modno; | |
| 18 | +}; | |
| 19 | + | |
| 20 | +/* PLX bridge chip onboard registers */ | |
| 21 | +struct janz_cmodio_onboard_regs { | |
| 22 | + u8 unused1; | |
| 23 | + | |
| 24 | + /* | |
| 25 | + * Read access: interrupt status | |
| 26 | + * Write access: interrupt disable | |
| 27 | + */ | |
| 28 | + u8 int_disable; | |
| 29 | + u8 unused2; | |
| 30 | + | |
| 31 | + /* | |
| 32 | + * Read access: MODULbus number (hex switch) | |
| 33 | + * Write access: interrupt enable | |
| 34 | + */ | |
| 35 | + u8 int_enable; | |
| 36 | + u8 unused3; | |
| 37 | + | |
| 38 | + /* write-only */ | |
| 39 | + u8 reset_assert; | |
| 40 | + u8 unused4; | |
| 41 | + | |
| 42 | + /* write-only */ | |
| 43 | + u8 reset_deassert; | |
| 44 | + u8 unused5; | |
| 45 | + | |
| 46 | + /* read-write access to serial EEPROM */ | |
| 47 | + u8 eep; | |
| 48 | + u8 unused6; | |
| 49 | + | |
| 50 | + /* write-only access to EEPROM chip select */ | |
| 51 | + u8 enid; | |
| 52 | +}; | |
| 53 | + | |
| 54 | +#endif /* JANZ_H */ | |
| @@ -0,0 +1,26 @@ | ||
| 1 | +#ifndef __RDC321X_MFD_H | |
| 2 | +#define __RDC321X_MFD_H | |
| 3 | + | |
| 4 | +#include <linux/types.h> | |
| 5 | +#include <linux/pci.h> | |
| 6 | + | |
| 7 | +/* Offsets to be accessed in the southbridge PCI | |
| 8 | + * device configuration register */ | |
| 9 | +#define RDC321X_WDT_CTRL 0x44 | |
| 10 | +#define RDC321X_GPIO_CTRL_REG1 0x48 | |
| 11 | +#define RDC321X_GPIO_DATA_REG1 0x4c | |
| 12 | +#define RDC321X_GPIO_CTRL_REG2 0x84 | |
| 13 | +#define RDC321X_GPIO_DATA_REG2 0x88 | |
| 14 | + | |
| 15 | +#define RDC321X_MAX_GPIO 58 | |
| 16 | + | |
| 17 | +struct rdc321x_gpio_pdata { | |
| 18 | + struct pci_dev *sb_pdev; | |
| 19 | + unsigned max_gpios; | |
| 20 | +}; | |
| 21 | + | |
| 22 | +struct rdc321x_wdt_pdata { | |
| 23 | + struct pci_dev *sb_pdev; | |
| 24 | +}; | |
| 25 | + | |
| 26 | +#endif /* __RDC321X_MFD_H */ | |
| @@ -0,0 +1,132 @@ | ||
| 1 | +/* | |
| 2 | + * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | + * | |
| 4 | + * License Terms: GNU General Public License, version 2 | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef __LINUX_MFD_TC35892_H | |
| 8 | +#define __LINUX_MFD_TC35892_H | |
| 9 | + | |
| 10 | +#include <linux/device.h> | |
| 11 | + | |
| 12 | +#define TC35892_RSTCTRL_IRQRST (1 << 4) | |
| 13 | +#define TC35892_RSTCTRL_TIMRST (1 << 3) | |
| 14 | +#define TC35892_RSTCTRL_ROTRST (1 << 2) | |
| 15 | +#define TC35892_RSTCTRL_KBDRST (1 << 1) | |
| 16 | +#define TC35892_RSTCTRL_GPIRST (1 << 0) | |
| 17 | + | |
| 18 | +#define TC35892_IRQST 0x91 | |
| 19 | + | |
| 20 | +#define TC35892_MANFCODE_MAGIC 0x03 | |
| 21 | +#define TC35892_MANFCODE 0x80 | |
| 22 | +#define TC35892_VERSION 0x81 | |
| 23 | +#define TC35892_IOCFG 0xA7 | |
| 24 | + | |
| 25 | +#define TC35892_CLKMODE 0x88 | |
| 26 | +#define TC35892_CLKCFG 0x89 | |
| 27 | +#define TC35892_CLKEN 0x8A | |
| 28 | + | |
| 29 | +#define TC35892_RSTCTRL 0x82 | |
| 30 | +#define TC35892_EXTRSTN 0x83 | |
| 31 | +#define TC35892_RSTINTCLR 0x84 | |
| 32 | + | |
| 33 | +#define TC35892_GPIOIS0 0xC9 | |
| 34 | +#define TC35892_GPIOIS1 0xCA | |
| 35 | +#define TC35892_GPIOIS2 0xCB | |
| 36 | +#define TC35892_GPIOIBE0 0xCC | |
| 37 | +#define TC35892_GPIOIBE1 0xCD | |
| 38 | +#define TC35892_GPIOIBE2 0xCE | |
| 39 | +#define TC35892_GPIOIEV0 0xCF | |
| 40 | +#define TC35892_GPIOIEV1 0xD0 | |
| 41 | +#define TC35892_GPIOIEV2 0xD1 | |
| 42 | +#define TC35892_GPIOIE0 0xD2 | |
| 43 | +#define TC35892_GPIOIE1 0xD3 | |
| 44 | +#define TC35892_GPIOIE2 0xD4 | |
| 45 | +#define TC35892_GPIORIS0 0xD6 | |
| 46 | +#define TC35892_GPIORIS1 0xD7 | |
| 47 | +#define TC35892_GPIORIS2 0xD8 | |
| 48 | +#define TC35892_GPIOMIS0 0xD9 | |
| 49 | +#define TC35892_GPIOMIS1 0xDA | |
| 50 | +#define TC35892_GPIOMIS2 0xDB | |
| 51 | +#define TC35892_GPIOIC0 0xDC | |
| 52 | +#define TC35892_GPIOIC1 0xDD | |
| 53 | +#define TC35892_GPIOIC2 0xDE | |
| 54 | + | |
| 55 | +#define TC35892_GPIODATA0 0xC0 | |
| 56 | +#define TC35892_GPIOMASK0 0xc1 | |
| 57 | +#define TC35892_GPIODATA1 0xC2 | |
| 58 | +#define TC35892_GPIOMASK1 0xc3 | |
| 59 | +#define TC35892_GPIODATA2 0xC4 | |
| 60 | +#define TC35892_GPIOMASK2 0xC5 | |
| 61 | + | |
| 62 | +#define TC35892_GPIODIR0 0xC6 | |
| 63 | +#define TC35892_GPIODIR1 0xC7 | |
| 64 | +#define TC35892_GPIODIR2 0xC8 | |
| 65 | + | |
| 66 | +#define TC35892_GPIOSYNC0 0xE6 | |
| 67 | +#define TC35892_GPIOSYNC1 0xE7 | |
| 68 | +#define TC35892_GPIOSYNC2 0xE8 | |
| 69 | + | |
| 70 | +#define TC35892_GPIOWAKE0 0xE9 | |
| 71 | +#define TC35892_GPIOWAKE1 0xEA | |
| 72 | +#define TC35892_GPIOWAKE2 0xEB | |
| 73 | + | |
| 74 | +#define TC35892_GPIOODM0 0xE0 | |
| 75 | +#define TC35892_GPIOODE0 0xE1 | |
| 76 | +#define TC35892_GPIOODM1 0xE2 | |
| 77 | +#define TC35892_GPIOODE1 0xE3 | |
| 78 | +#define TC35892_GPIOODM2 0xE4 | |
| 79 | +#define TC35892_GPIOODE2 0xE5 | |
| 80 | + | |
| 81 | +#define TC35892_INT_GPIIRQ 0 | |
| 82 | +#define TC35892_INT_TI0IRQ 1 | |
| 83 | +#define TC35892_INT_TI1IRQ 2 | |
| 84 | +#define TC35892_INT_TI2IRQ 3 | |
| 85 | +#define TC35892_INT_ROTIRQ 5 | |
| 86 | +#define TC35892_INT_KBDIRQ 6 | |
| 87 | +#define TC35892_INT_PORIRQ 7 | |
| 88 | + | |
| 89 | +#define TC35892_NR_INTERNAL_IRQS 8 | |
| 90 | +#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) | |
| 91 | + | |
| 92 | +struct tc35892 { | |
| 93 | + struct mutex lock; | |
| 94 | + struct device *dev; | |
| 95 | + struct i2c_client *i2c; | |
| 96 | + | |
| 97 | + int irq_base; | |
| 98 | + int num_gpio; | |
| 99 | + struct tc35892_platform_data *pdata; | |
| 100 | +}; | |
| 101 | + | |
| 102 | +extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data); | |
| 103 | +extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg); | |
| 104 | +extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length, | |
| 105 | + u8 *values); | |
| 106 | +extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length, | |
| 107 | + const u8 *values); | |
| 108 | +extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val); | |
| 109 | + | |
| 110 | +/** | |
| 111 | + * struct tc35892_gpio_platform_data - TC35892 GPIO platform data | |
| 112 | + * @gpio_base: first gpio number assigned to TC35892. A maximum of | |
| 113 | + * %TC35892_NR_GPIOS GPIOs will be allocated. | |
| 114 | + */ | |
| 115 | +struct tc35892_gpio_platform_data { | |
| 116 | + int gpio_base; | |
| 117 | +}; | |
| 118 | + | |
| 119 | +/** | |
| 120 | + * struct tc35892_platform_data - TC35892 platform data | |
| 121 | + * @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used. | |
| 122 | + * @gpio: GPIO-specific platform data | |
| 123 | + */ | |
| 124 | +struct tc35892_platform_data { | |
| 125 | + int irq_base; | |
| 126 | + struct tc35892_gpio_platform_data *gpio; | |
| 127 | +}; | |
| 128 | + | |
| 129 | +#define TC35892_NR_GPIOS 24 | |
| 130 | +#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) | |
| 131 | + | |
| 132 | +#endif | |
| @@ -0,0 +1,169 @@ | ||
| 1 | +/* linux/mfd/tps6507x.h | |
| 2 | + * | |
| 3 | + * Functions to access TPS65070 power management chip. | |
| 4 | + * | |
| 5 | + * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com) | |
| 6 | + * | |
| 7 | + * | |
| 8 | + * For licencing details see kernel-base/COPYING | |
| 9 | + */ | |
| 10 | + | |
| 11 | +#ifndef __LINUX_MFD_TPS6507X_H | |
| 12 | +#define __LINUX_MFD_TPS6507X_H | |
| 13 | + | |
| 14 | +/* | |
| 15 | + * ---------------------------------------------------------------------------- | |
| 16 | + * Registers, all 8 bits | |
| 17 | + * ---------------------------------------------------------------------------- | |
| 18 | + */ | |
| 19 | + | |
| 20 | + | |
| 21 | +/* Register definitions */ | |
| 22 | +#define TPS6507X_REG_PPATH1 0X01 | |
| 23 | +#define TPS6507X_CHG_USB BIT(7) | |
| 24 | +#define TPS6507X_CHG_AC BIT(6) | |
| 25 | +#define TPS6507X_CHG_USB_PW_ENABLE BIT(5) | |
| 26 | +#define TPS6507X_CHG_AC_PW_ENABLE BIT(4) | |
| 27 | +#define TPS6507X_CHG_AC_CURRENT BIT(2) | |
| 28 | +#define TPS6507X_CHG_USB_CURRENT BIT(0) | |
| 29 | + | |
| 30 | +#define TPS6507X_REG_INT 0X02 | |
| 31 | +#define TPS6507X_REG_MASK_AC_USB BIT(7) | |
| 32 | +#define TPS6507X_REG_MASK_TSC BIT(6) | |
| 33 | +#define TPS6507X_REG_MASK_PB_IN BIT(5) | |
| 34 | +#define TPS6507X_REG_TSC_INT BIT(3) | |
| 35 | +#define TPS6507X_REG_PB_IN_INT BIT(2) | |
| 36 | +#define TPS6507X_REG_AC_USB_APPLIED BIT(1) | |
| 37 | +#define TPS6507X_REG_AC_USB_REMOVED BIT(0) | |
| 38 | + | |
| 39 | +#define TPS6507X_REG_CHGCONFIG0 0X03 | |
| 40 | + | |
| 41 | +#define TPS6507X_REG_CHGCONFIG1 0X04 | |
| 42 | +#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4) | |
| 43 | +#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3) | |
| 44 | +#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2) | |
| 45 | +#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1) | |
| 46 | +#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0) | |
| 47 | + | |
| 48 | +#define TPS6507X_REG_CHGCONFIG2 0X05 | |
| 49 | + | |
| 50 | +#define TPS6507X_REG_CHGCONFIG3 0X06 | |
| 51 | + | |
| 52 | +#define TPS6507X_REG_ADCONFIG 0X07 | |
| 53 | +#define TPS6507X_ADCONFIG_AD_ENABLE BIT(7) | |
| 54 | +#define TPS6507X_ADCONFIG_START_CONVERSION BIT(6) | |
| 55 | +#define TPS6507X_ADCONFIG_CONVERSION_DONE BIT(5) | |
| 56 | +#define TPS6507X_ADCONFIG_VREF_ENABLE BIT(4) | |
| 57 | +#define TPS6507X_ADCONFIG_INPUT_AD_IN1 0 | |
| 58 | +#define TPS6507X_ADCONFIG_INPUT_AD_IN2 1 | |
| 59 | +#define TPS6507X_ADCONFIG_INPUT_AD_IN3 2 | |
| 60 | +#define TPS6507X_ADCONFIG_INPUT_AD_IN4 3 | |
| 61 | +#define TPS6507X_ADCONFIG_INPUT_TS_PIN 4 | |
| 62 | +#define TPS6507X_ADCONFIG_INPUT_BAT_CURRENT 5 | |
| 63 | +#define TPS6507X_ADCONFIG_INPUT_AC_VOLTAGE 6 | |
| 64 | +#define TPS6507X_ADCONFIG_INPUT_SYS_VOLTAGE 7 | |
| 65 | +#define TPS6507X_ADCONFIG_INPUT_CHARGER_VOLTAGE 8 | |
| 66 | +#define TPS6507X_ADCONFIG_INPUT_BAT_VOLTAGE 9 | |
| 67 | +#define TPS6507X_ADCONFIG_INPUT_THRESHOLD_VOLTAGE 10 | |
| 68 | +#define TPS6507X_ADCONFIG_INPUT_ISET1_VOLTAGE 11 | |
| 69 | +#define TPS6507X_ADCONFIG_INPUT_ISET2_VOLTAGE 12 | |
| 70 | +#define TPS6507X_ADCONFIG_INPUT_REAL_TSC 14 | |
| 71 | +#define TPS6507X_ADCONFIG_INPUT_TSC 15 | |
| 72 | + | |
| 73 | +#define TPS6507X_REG_TSCMODE 0X08 | |
| 74 | +#define TPS6507X_TSCMODE_X_POSITION 0 | |
| 75 | +#define TPS6507X_TSCMODE_Y_POSITION 1 | |
| 76 | +#define TPS6507X_TSCMODE_PRESSURE 2 | |
| 77 | +#define TPS6507X_TSCMODE_X_PLATE 3 | |
| 78 | +#define TPS6507X_TSCMODE_Y_PLATE 4 | |
| 79 | +#define TPS6507X_TSCMODE_STANDBY 5 | |
| 80 | +#define TPS6507X_TSCMODE_ADC_INPUT 6 | |
| 81 | +#define TPS6507X_TSCMODE_DISABLE 7 | |
| 82 | + | |
| 83 | +#define TPS6507X_REG_ADRESULT_1 0X09 | |
| 84 | + | |
| 85 | +#define TPS6507X_REG_ADRESULT_2 0X0A | |
| 86 | +#define TPS6507X_REG_ADRESULT_2_MASK (BIT(1) | BIT(0)) | |
| 87 | + | |
| 88 | +#define TPS6507X_REG_PGOOD 0X0B | |
| 89 | + | |
| 90 | +#define TPS6507X_REG_PGOODMASK 0X0C | |
| 91 | + | |
| 92 | +#define TPS6507X_REG_CON_CTRL1 0X0D | |
| 93 | +#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4) | |
| 94 | +#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3) | |
| 95 | +#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2) | |
| 96 | +#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1) | |
| 97 | +#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0) | |
| 98 | + | |
| 99 | +#define TPS6507X_REG_CON_CTRL2 0X0E | |
| 100 | + | |
| 101 | +#define TPS6507X_REG_CON_CTRL3 0X0F | |
| 102 | + | |
| 103 | +#define TPS6507X_REG_DEFDCDC1 0X10 | |
| 104 | +#define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7) | |
| 105 | +#define TPS6507X_DEFDCDC1_DCDC1_MASK 0X3F | |
| 106 | + | |
| 107 | +#define TPS6507X_REG_DEFDCDC2_LOW 0X11 | |
| 108 | +#define TPS6507X_DEFDCDC2_LOW_DCDC2_MASK 0X3F | |
| 109 | + | |
| 110 | +#define TPS6507X_REG_DEFDCDC2_HIGH 0X12 | |
| 111 | +#define TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK 0X3F | |
| 112 | + | |
| 113 | +#define TPS6507X_REG_DEFDCDC3_LOW 0X13 | |
| 114 | +#define TPS6507X_DEFDCDC3_LOW_DCDC3_MASK 0X3F | |
| 115 | + | |
| 116 | +#define TPS6507X_REG_DEFDCDC3_HIGH 0X14 | |
| 117 | +#define TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK 0X3F | |
| 118 | + | |
| 119 | +#define TPS6507X_REG_DEFSLEW 0X15 | |
| 120 | + | |
| 121 | +#define TPS6507X_REG_LDO_CTRL1 0X16 | |
| 122 | +#define TPS6507X_REG_LDO_CTRL1_LDO1_MASK 0X0F | |
| 123 | + | |
| 124 | +#define TPS6507X_REG_DEFLDO2 0X17 | |
| 125 | +#define TPS6507X_REG_DEFLDO2_LDO2_MASK 0X3F | |
| 126 | + | |
| 127 | +#define TPS6507X_REG_WLED_CTRL1 0X18 | |
| 128 | + | |
| 129 | +#define TPS6507X_REG_WLED_CTRL2 0X19 | |
| 130 | + | |
| 131 | +/* VDCDC MASK */ | |
| 132 | +#define TPS6507X_DEFDCDCX_DCDC_MASK 0X3F | |
| 133 | + | |
| 134 | +#define TPS6507X_MAX_REGISTER 0X19 | |
| 135 | + | |
| 136 | +/** | |
| 137 | + * struct tps6507x_board - packages regulator and touchscreen init data | |
| 138 | + * @tps6507x_regulator_data: regulator initialization values | |
| 139 | + * | |
| 140 | + * Board data may be used to initialize regulator and touchscreen. | |
| 141 | + */ | |
| 142 | + | |
| 143 | +struct tps6507x_board { | |
| 144 | + struct regulator_init_data *tps6507x_pmic_init_data; | |
| 145 | + struct touchscreen_init_data *tps6507x_ts_init_data; | |
| 146 | +}; | |
| 147 | + | |
| 148 | +/** | |
| 149 | + * struct tps6507x_dev - tps6507x sub-driver chip access routines | |
| 150 | + * @read_dev() - I2C register read function | |
| 151 | + * @write_dev() - I2C register write function | |
| 152 | + * | |
| 153 | + * Device data may be used to access the TPS6507x chip | |
| 154 | + */ | |
| 155 | + | |
| 156 | +struct tps6507x_dev { | |
| 157 | + struct device *dev; | |
| 158 | + struct i2c_client *i2c_client; | |
| 159 | + int (*read_dev)(struct tps6507x_dev *tps6507x, char reg, int size, | |
| 160 | + void *dest); | |
| 161 | + int (*write_dev)(struct tps6507x_dev *tps6507x, char reg, int size, | |
| 162 | + void *src); | |
| 163 | + | |
| 164 | + /* Client devices */ | |
| 165 | + struct tps6507x_pmic *pmic; | |
| 166 | + struct tps6507x_ts *ts; | |
| 167 | +}; | |
| 168 | + | |
| 169 | +#endif /* __LINUX_MFD_TPS6507X_H */ | |
| @@ -256,8 +256,9 @@ struct wm831x { · 255 unmodified lines | ||
| 256 | 256 | int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ |
| 257 | 257 | |
| 258 | 258 | /* Chip revision based flags */ |
| 259 | − unsigned has_gpio_ena:1; /* Has GPIO enable bit */ | |
| 260 | − unsigned has_cs_sts:1; /* Has current sink status bit */ | |
| 259 | + unsigned has_gpio_ena:1; /* Has GPIO enable bit */ | |
| 260 | + unsigned has_cs_sts:1; /* Has current sink status bit */ | |
| 261 | + unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */ | |
| 261 | 262 | |
| 262 | 263 | int num_gpio; |
| 263 | 264 | |