History

Merge branch 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Misc radeon and amdgpu bug fixes for 4.6. * 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux: amdgpu/uvd: add uvd fw version for amdgpu drm/amdgpu: forbid mapping of userptr bo through radeon device file drm/radeon: forbid mapping of userptr bo through radeon device file drm/amdgpu: bump the afmt limit for CZ, ST, Polaris drm/amdgpu: use defines for CRTCs and AMFT blocks drm/radeon: print a message if ATPX dGPU power control is missing Revert "drm/radeon: disable runtime pm on PX laptops without dGPU power control" drm/amdgpu/acp: fix resume on CZ systems with AZ audio drm/radeon: add a quirk for a XFX R9 270X drm/radeon: print pci revision as well as pci ids on driver load drm/amdgpu: when suspending, if uvd/vce was running. need to cancel delay work. drm/radeon: fix initial connector audio value

Dave Airlie committed 10 years ago

Commit 18cdfe72 parents 221004c 562e26812 files · +37 −19Browse files

Unified · Split

12 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu.h +1 −0
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +4 −0
  3. drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +1 −1
  4. drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +3 −3
  5. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +2 −0
  6. drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +5 −0
  7. drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +1 −0
  8. drivers/gpu/drm/radeon/radeon_atpx_handler.c +7 −4
  9. drivers/gpu/drm/radeon/radeon_connectors.c +6 −1
  10. drivers/gpu/drm/radeon/radeon_device.c +4 −10
  11. drivers/gpu/drm/radeon/radeon_ttm.c +2 −0
  12. drivers/gpu/drm/radeon/si_dpm.c +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu.h+1−0
@@ -1591,6 +1591,7 @@ struct amdgpu_uvd { · 1590 unmodified lines
1591 struct amdgpu_bo *vcpu_bo;1591 struct amdgpu_bo *vcpu_bo;
1592 void *cpu_addr;1592 void *cpu_addr;
1593 uint64_t gpu_addr;1593 uint64_t gpu_addr;
1594 unsigned fw_version;
1594 void *saved_bo;1595 void *saved_bo;
1595 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];1596 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1596 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];1597 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c+4−0
@@ -425,6 +425,10 @@ static int acp_resume(void *handle) · 424 unmodified lines
425 struct acp_pm_domain *apd;425 struct acp_pm_domain *apd;
426 struct amdgpu_device *adev = (struct amdgpu_device *)handle;426 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
427 427
428 /* return early if no ACP */
429 if (!adev->acp.acp_genpd)
430 return 0;
431
428 /* SMU block will power on ACP irrespective of ACP runtime status.432 /* SMU block will power on ACP irrespective of ACP runtime status.
429 * Power off explicitly based on genpd ACP runtime status so that ACP433 * Power off explicitly based on genpd ACP runtime status so that ACP
430 * hw and ACP-genpd status are in sync.434 * hw and ACP-genpd status are in sync.
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+1−1
@@ -303,7 +303,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 302 unmodified lines
303 fw_info.feature = adev->vce.fb_version;303 fw_info.feature = adev->vce.fb_version;
304 break;304 break;
305 case AMDGPU_INFO_FW_UVD:305 case AMDGPU_INFO_FW_UVD:
306 fw_info.ver = 0;306 fw_info.ver = adev->uvd.fw_version;
307 fw_info.feature = 0;307 fw_info.feature = 0;
308 break;308 break;
309 case AMDGPU_INFO_FW_GMC:309 case AMDGPU_INFO_FW_GMC:
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h+3−3
@@ -53,7 +53,7 @@ struct amdgpu_hpd; · 52 unmodified lines
53 53
54#define AMDGPU_MAX_HPD_PINS 654#define AMDGPU_MAX_HPD_PINS 6
55#define AMDGPU_MAX_CRTCS 655#define AMDGPU_MAX_CRTCS 6
56#define AMDGPU_MAX_AFMT_BLOCKS 756#define AMDGPU_MAX_AFMT_BLOCKS 9
57 57
58enum amdgpu_rmx_type {58enum amdgpu_rmx_type {
59 RMX_OFF,59 RMX_OFF,
@@ -309,8 +309,8 @@ struct amdgpu_mode_info { · 249 unmodified lines
309 struct atom_context *atom_context;309 struct atom_context *atom_context;
310 struct card_info *atom_card_info;310 struct card_info *atom_card_info;
311 bool mode_config_initialized;311 bool mode_config_initialized;
312 struct amdgpu_crtc *crtcs[6];312 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
313 struct amdgpu_afmt *afmt[7];313 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
314 /* DVI-I properties */314 /* DVI-I properties */
315 struct drm_property *coherent_mode_property;315 struct drm_property *coherent_mode_property;
316 /* DAC enable load detect */316 /* DAC enable load detect */
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+2−0
@@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) · 222 unmodified lines
223{223{
224 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);224 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
225 225
226 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
227 return -EPERM;
226 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);228 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
227}229}
228 230
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+5−0
@@ -158,6 +158,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) · 157 unmodified lines
158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
159 version_major, version_minor, family_id);159 version_major, version_minor, family_id);
160 160
161 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
162 (family_id << 8));
163
161 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)164 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
162 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;165 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
163 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,166 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
@@ -255,6 +258,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev) · 91 unmodified lines
255 if (i == AMDGPU_MAX_UVD_HANDLES)258 if (i == AMDGPU_MAX_UVD_HANDLES)
256 return 0;259 return 0;
257 260
261 cancel_delayed_work_sync(&adev->uvd.idle_work);
262
258 size = amdgpu_bo_size(adev->uvd.vcpu_bo);263 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
259 ptr = adev->uvd.cpu_addr;264 ptr = adev->uvd.cpu_addr;
260 265
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c+1−0
@@ -234,6 +234,7 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev) · 233 unmodified lines
234 if (i == AMDGPU_MAX_VCE_HANDLES)234 if (i == AMDGPU_MAX_VCE_HANDLES)
235 return 0;235 return 0;
236 236
237 cancel_delayed_work_sync(&adev->vce.idle_work);
237 /* TODO: suspending running encoding sessions isn't supported */238 /* TODO: suspending running encoding sessions isn't supported */
238 return -EINVAL;239 return -EINVAL;
239}240}
drivers/gpu/drm/radeon/radeon_atpx_handler.c+7−4
@@ -62,10 +62,6 @@ bool radeon_has_atpx(void) { · 61 unmodified lines
62 return radeon_atpx_priv.atpx_detected;62 return radeon_atpx_priv.atpx_detected;
63}63}
64 64
65bool radeon_has_atpx_dgpu_power_cntl(void) {
66 return radeon_atpx_priv.atpx.functions.power_cntl;
67}
68
69/**65/**
70 * radeon_atpx_call - call an ATPX method66 * radeon_atpx_call - call an ATPX method
71 *67 *
@@ -145,6 +141,13 @@ static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mas · 73 unmodified lines
145 */141 */
146static int radeon_atpx_validate(struct radeon_atpx *atpx)142static int radeon_atpx_validate(struct radeon_atpx *atpx)
147{143{
144 /* make sure required functions are enabled */
145 /* dGPU power control is required */
146 if (atpx->functions.power_cntl == false) {
147 printk("ATPX dGPU power cntl not present, forcing\n");
148 atpx->functions.power_cntl = true;
149 }
150
148 if (atpx->functions.px_params) {151 if (atpx->functions.px_params) {
149 union acpi_object *info;152 union acpi_object *info;
150 struct atpx_px_params output;153 struct atpx_px_params output;
drivers/gpu/drm/radeon/radeon_connectors.c+6−1
@@ -2002,10 +2002,12 @@ radeon_add_atom_connector(struct drm_device *dev, · 2001 unmodified lines
2002 rdev->mode_info.dither_property,2002 rdev->mode_info.dither_property,
2003 RADEON_FMT_DITHER_DISABLE);2003 RADEON_FMT_DITHER_DISABLE);
2004 2004
2005 if (radeon_audio != 0)2005 if (radeon_audio != 0) {
2006 drm_object_attach_property(&radeon_connector->base.base,2006 drm_object_attach_property(&radeon_connector->base.base,
2007 rdev->mode_info.audio_property,2007 rdev->mode_info.audio_property,
2008 RADEON_AUDIO_AUTO);2008 RADEON_AUDIO_AUTO);
2009 radeon_connector->audio = RADEON_AUDIO_AUTO;
2010 }
2009 if (ASIC_IS_DCE5(rdev))2011 if (ASIC_IS_DCE5(rdev))
2010 drm_object_attach_property(&radeon_connector->base.base,2012 drm_object_attach_property(&radeon_connector->base.base,
2011 rdev->mode_info.output_csc_property,2013 rdev->mode_info.output_csc_property,
@@ -2130,6 +2132,7 @@ radeon_add_atom_connector(struct drm_device *dev, · 118 unmodified lines
2130 drm_object_attach_property(&radeon_connector->base.base,2132 drm_object_attach_property(&radeon_connector->base.base,
2131 rdev->mode_info.audio_property,2133 rdev->mode_info.audio_property,
2132 RADEON_AUDIO_AUTO);2134 RADEON_AUDIO_AUTO);
2135 radeon_connector->audio = RADEON_AUDIO_AUTO;
2133 }2136 }
2134 if (connector_type == DRM_MODE_CONNECTOR_DVII) {2137 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2135 radeon_connector->dac_load_detect = true;2138 radeon_connector->dac_load_detect = true;
@@ -2185,6 +2188,7 @@ radeon_add_atom_connector(struct drm_device *dev, · 49 unmodified lines
2185 drm_object_attach_property(&radeon_connector->base.base,2188 drm_object_attach_property(&radeon_connector->base.base,
2186 rdev->mode_info.audio_property,2189 rdev->mode_info.audio_property,
2187 RADEON_AUDIO_AUTO);2190 RADEON_AUDIO_AUTO);
2191 radeon_connector->audio = RADEON_AUDIO_AUTO;
2188 }2192 }
2189 if (ASIC_IS_DCE5(rdev))2193 if (ASIC_IS_DCE5(rdev))
2190 drm_object_attach_property(&radeon_connector->base.base,2194 drm_object_attach_property(&radeon_connector->base.base,
@@ -2237,6 +2241,7 @@ radeon_add_atom_connector(struct drm_device *dev, · 46 unmodified lines
2237 drm_object_attach_property(&radeon_connector->base.base,2241 drm_object_attach_property(&radeon_connector->base.base,
2238 rdev->mode_info.audio_property,2242 rdev->mode_info.audio_property,
2239 RADEON_AUDIO_AUTO);2243 RADEON_AUDIO_AUTO);
2244 radeon_connector->audio = RADEON_AUDIO_AUTO;
2240 }2245 }
2241 if (ASIC_IS_DCE5(rdev))2246 if (ASIC_IS_DCE5(rdev))
2242 drm_object_attach_property(&radeon_connector->base.base,2247 drm_object_attach_property(&radeon_connector->base.base,
drivers/gpu/drm/radeon/radeon_device.c+4−10
@@ -103,12 +103,6 @@ static const char radeon_family_name[][16] = { · 102 unmodified lines
103 "LAST",103 "LAST",
104};104};
105 105
106#if defined(CONFIG_VGA_SWITCHEROO)
107bool radeon_has_atpx_dgpu_power_cntl(void);
108#else
109static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
110#endif
111
112#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)106#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
113#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)107#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
114 108
@@ -1305,9 +1299,9 @@ int radeon_device_init(struct radeon_device *rdev, · 1190 unmodified lines
1305 }1299 }
1306 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);1300 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
1307 1301
1308 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",1302 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1309 radeon_family_name[rdev->family], pdev->vendor, pdev->device,1303 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1310 pdev->subsystem_vendor, pdev->subsystem_device);1304 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1311 1305
1312 /* mutex initialization are all done here so we1306 /* mutex initialization are all done here so we
1313 * can recall function without having locking issues */1307 * can recall function without having locking issues */
@@ -1439,7 +1433,7 @@ int radeon_device_init(struct radeon_device *rdev, · 125 unmodified lines
1439 * ignore it */1433 * ignore it */
1440 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);1434 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1441 1435
1442 if ((rdev->flags & RADEON_IS_PX) && radeon_has_atpx_dgpu_power_cntl())1436 if (rdev->flags & RADEON_IS_PX)
1443 runtime = true;1437 runtime = true;
1444 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);1438 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1445 if (runtime)1439 if (runtime)
drivers/gpu/drm/radeon/radeon_ttm.c+2−0
@@ -235,6 +235,8 @@ static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) · 234 unmodified lines
235{235{
236 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);236 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
237 237
238 if (radeon_ttm_tt_has_userptr(bo->ttm))
239 return -EPERM;
238 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);240 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
239}241}
240 242
drivers/gpu/drm/radeon/si_dpm.c+1−0
@@ -2931,6 +2931,7 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = { · 2930 unmodified lines
2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2934 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2934 { 0, 0, 0, 0 },2935 { 0, 0, 0, 0 },
2935};2936};
2936 2937