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Merge branch 'pci/dpc' into next

* pci/dpc: PCI/DPC: Add local struct device pointers PCI/DPC: Add eDPC support

Bjorn Helgaas committed 9 years ago

Commit 18f20672 parents f190132 9e16b8d2 files · +187 −10Browse files

Unified · Split

2 files
  1. drivers/pci/pcie/pcie-dpc.c +177 −10
  2. include/uapi/linux/pci_regs.h +10 −0
drivers/pci/pcie/pcie-dpc.c+177−10
@@ -16,17 +16,62 @@ · 15 unmodified lines
16#include <linux/pcieport_if.h>16#include <linux/pcieport_if.h>
17#include "../pci.h"17#include "../pci.h"
18 18
19struct rp_pio_header_log_regs {
20 u32 dw0;
21 u32 dw1;
22 u32 dw2;
23 u32 dw3;
24};
25
26struct dpc_rp_pio_regs {
27 u32 status;
28 u32 mask;
29 u32 severity;
30 u32 syserror;
31 u32 exception;
32
33 struct rp_pio_header_log_regs header_log;
34 u32 impspec_log;
35 u32 tlp_prefix_log[4];
36 u32 log_size;
37 u16 first_error;
38};
39
19struct dpc_dev {40struct dpc_dev {
20 struct pcie_device *dev;41 struct pcie_device *dev;
21 struct work_struct work;42 struct work_struct work;
22 int cap_pos;43 int cap_pos;
23 bool rp;44 bool rp;
45 u32 rp_pio_status;
46};
47
48static const char * const rp_pio_error_string[] = {
49 "Configuration Request received UR Completion", /* Bit Position 0 */
50 "Configuration Request received CA Completion", /* Bit Position 1 */
51 "Configuration Request Completion Timeout", /* Bit Position 2 */
52 NULL,
53 NULL,
54 NULL,
55 NULL,
56 NULL,
57 "I/O Request received UR Completion", /* Bit Position 8 */
58 "I/O Request received CA Completion", /* Bit Position 9 */
59 "I/O Request Completion Timeout", /* Bit Position 10 */
60 NULL,
61 NULL,
62 NULL,
63 NULL,
64 NULL,
65 "Memory Request received UR Completion", /* Bit Position 16 */
66 "Memory Request received CA Completion", /* Bit Position 17 */
67 "Memory Request Completion Timeout", /* Bit Position 18 */
24};68};
25 69
26static int dpc_wait_rp_inactive(struct dpc_dev *dpc)70static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
27{71{
28 unsigned long timeout = jiffies + HZ;72 unsigned long timeout = jiffies + HZ;
29 struct pci_dev *pdev = dpc->dev->port;73 struct pci_dev *pdev = dpc->dev->port;
74 struct device *dev = &dpc->dev->device;
30 u16 status;75 u16 status;
31 76
32 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);77 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
@@ -36,15 +81,17 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc) · 3 unmodified lines
36 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);81 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
37 }82 }
38 if (status & PCI_EXP_DPC_RP_BUSY) {83 if (status & PCI_EXP_DPC_RP_BUSY) {
39 dev_warn(&pdev->dev, "DPC root port still busy\n");84 dev_warn(dev, "DPC root port still busy\n");
40 return -EBUSY;85 return -EBUSY;
41 }86 }
42 return 0;87 return 0;
43}88}
44 89
45static void dpc_wait_link_inactive(struct pci_dev *pdev)90static void dpc_wait_link_inactive(struct dpc_dev *dpc)
46{91{
47 unsigned long timeout = jiffies + HZ;92 unsigned long timeout = jiffies + HZ;
93 struct pci_dev *pdev = dpc->dev->port;
94 struct device *dev = &dpc->dev->device;
48 u16 lnk_status;95 u16 lnk_status;
49 96
50 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);97 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
@@ -54,7 +101,7 @@ static void dpc_wait_link_inactive(struct pci_dev *pdev) · 3 unmodified lines
54 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);101 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
55 }102 }
56 if (lnk_status & PCI_EXP_LNKSTA_DLLLA)103 if (lnk_status & PCI_EXP_LNKSTA_DLLLA)
57 dev_warn(&pdev->dev, "Link state not disabled for DPC event\n");104 dev_warn(dev, "Link state not disabled for DPC event\n");
58}105}
59 106
60static void interrupt_event_handler(struct work_struct *work)107static void interrupt_event_handler(struct work_struct *work)
@@ -76,17 +123,132 @@ static void interrupt_event_handler(struct work_struct *work) · 15 unmodified lines
76 }123 }
77 pci_unlock_rescan_remove();124 pci_unlock_rescan_remove();
78 125
79 dpc_wait_link_inactive(pdev);126 dpc_wait_link_inactive(dpc);
80 if (dpc->rp && dpc_wait_rp_inactive(dpc))127 if (dpc->rp && dpc_wait_rp_inactive(dpc))
81 return;128 return;
129 if (dpc->rp && dpc->rp_pio_status) {
130 pci_write_config_dword(pdev,
131 dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
132 dpc->rp_pio_status);
133 dpc->rp_pio_status = 0;
134 }
135
82 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,136 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,
83 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);137 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
84}138}
85 139
140static void dpc_rp_pio_print_tlp_header(struct device *dev,
141 struct rp_pio_header_log_regs *t)
142{
143 dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
144 t->dw0, t->dw1, t->dw2, t->dw3);
145}
146
147static void dpc_rp_pio_print_error(struct dpc_dev *dpc,
148 struct dpc_rp_pio_regs *rp_pio)
149{
150 struct device *dev = &dpc->dev->device;
151 int i;
152 u32 status;
153
154 dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
155 rp_pio->status, rp_pio->mask);
156
157 dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
158 rp_pio->severity, rp_pio->syserror, rp_pio->exception);
159
160 status = (rp_pio->status & ~rp_pio->mask);
161
162 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
163 if (!(status & (1 << i)))
164 continue;
165
166 dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
167 rp_pio->first_error == i ? " (First)" : "");
168 }
169
170 dpc_rp_pio_print_tlp_header(dev, &rp_pio->header_log);
171 if (rp_pio->log_size == 4)
172 return;
173 dev_err(dev, "RP PIO ImpSpec Log %#010x\n", rp_pio->impspec_log);
174
175 for (i = 0; i < rp_pio->log_size - 5; i++)
176 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i,
177 rp_pio->tlp_prefix_log[i]);
178}
179
180static void dpc_rp_pio_get_info(struct dpc_dev *dpc,
181 struct dpc_rp_pio_regs *rp_pio)
182{
183 struct pci_dev *pdev = dpc->dev->port;
184 struct device *dev = &dpc->dev->device;
185 int i;
186 u16 cap;
187 u16 status;
188
189 pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
190 &rp_pio->status);
191 pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_MASK,
192 &rp_pio->mask);
193
194 pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SEVERITY,
195 &rp_pio->severity);
196 pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SYSERROR,
197 &rp_pio->syserror);
198 pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_EXCEPTION,
199 &rp_pio->exception);
200
201 /* Get First Error Pointer */
202 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
203 rp_pio->first_error = (status & 0x1f00) >> 8;
204
205 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
206 rp_pio->log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
207 if (rp_pio->log_size < 4 || rp_pio->log_size > 9) {
208 dev_err(dev, "RP PIO log size %u is invalid\n",
209 rp_pio->log_size);
210 return;
211 }
212
213 pci_read_config_dword(pdev,
214 dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
215 &rp_pio->header_log.dw0);
216 pci_read_config_dword(pdev,
217 dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
218 &rp_pio->header_log.dw1);
219 pci_read_config_dword(pdev,
220 dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
221 &rp_pio->header_log.dw2);
222 pci_read_config_dword(pdev,
223 dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
224 &rp_pio->header_log.dw3);
225 if (rp_pio->log_size == 4)
226 return;
227
228 pci_read_config_dword(pdev,
229 dpc->cap_pos + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG,
230 &rp_pio->impspec_log);
231 for (i = 0; i < rp_pio->log_size - 5; i++)
232 pci_read_config_dword(pdev,
233 dpc->cap_pos + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
234 &rp_pio->tlp_prefix_log[i]);
235}
236
237static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
238{
239 struct dpc_rp_pio_regs rp_pio_regs;
240
241 dpc_rp_pio_get_info(dpc, &rp_pio_regs);
242 dpc_rp_pio_print_error(dpc, &rp_pio_regs);
243
244 dpc->rp_pio_status = rp_pio_regs.status;
245}
246
86static irqreturn_t dpc_irq(int irq, void *context)247static irqreturn_t dpc_irq(int irq, void *context)
87{248{
88 struct dpc_dev *dpc = (struct dpc_dev *)context;249 struct dpc_dev *dpc = (struct dpc_dev *)context;
89 struct pci_dev *pdev = dpc->dev->port;250 struct pci_dev *pdev = dpc->dev->port;
251 struct device *dev = &dpc->dev->device;
90 u16 status, source;252 u16 status, source;
91 253
92 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);254 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
@@ -95,20 +257,24 @@ static irqreturn_t dpc_irq(int irq, void *context) · 2 unmodified lines
95 if (!status || status == (u16)(~0))257 if (!status || status == (u16)(~0))
96 return IRQ_NONE;258 return IRQ_NONE;
97 259
98 dev_info(&dpc->dev->device, "DPC containment event, status:%#06x source:%#06x\n",260 dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
99 status, source);261 status, source);
100 262
101 if (status & PCI_EXP_DPC_STATUS_TRIGGER) {263 if (status & PCI_EXP_DPC_STATUS_TRIGGER) {
102 u16 reason = (status >> 1) & 0x3;264 u16 reason = (status >> 1) & 0x3;
103 u16 ext_reason = (status >> 5) & 0x3;265 u16 ext_reason = (status >> 5) & 0x3;
104 266
105 dev_warn(&dpc->dev->device, "DPC %s detected, remove downstream devices\n",267 dev_warn(dev, "DPC %s detected, remove downstream devices\n",
106 (reason == 0) ? "unmasked uncorrectable error" :268 (reason == 0) ? "unmasked uncorrectable error" :
107 (reason == 1) ? "ERR_NONFATAL" :269 (reason == 1) ? "ERR_NONFATAL" :
108 (reason == 2) ? "ERR_FATAL" :270 (reason == 2) ? "ERR_FATAL" :
109 (ext_reason == 0) ? "RP PIO error" :271 (ext_reason == 0) ? "RP PIO error" :
110 (ext_reason == 1) ? "software trigger" :272 (ext_reason == 1) ? "software trigger" :
111 "reserved error");273 "reserved error");
274 /* show RP PIO error detail information */
275 if (reason == 3 && ext_reason == 0)
276 dpc_process_rp_pio_error(dpc);
277
112 schedule_work(&dpc->work);278 schedule_work(&dpc->work);
113 }279 }
114 return IRQ_HANDLED;280 return IRQ_HANDLED;
@@ -119,10 +285,11 @@ static int dpc_probe(struct pcie_device *dev) · 4 unmodified lines
119{285{
120 struct dpc_dev *dpc;286 struct dpc_dev *dpc;
121 struct pci_dev *pdev = dev->port;287 struct pci_dev *pdev = dev->port;
288 struct device *device = &dev->device;
122 int status;289 int status;
123 u16 ctl, cap;290 u16 ctl, cap;
124 291
125 dpc = devm_kzalloc(&dev->device, sizeof(*dpc), GFP_KERNEL);292 dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
126 if (!dpc)293 if (!dpc)
127 return -ENOMEM;294 return -ENOMEM;
128 295
@@ -131,10 +298,10 @@ static int dpc_probe(struct pcie_device *dev) · 2 unmodified lines
131 INIT_WORK(&dpc->work, interrupt_event_handler);298 INIT_WORK(&dpc->work, interrupt_event_handler);
132 set_service_data(dev, dpc);299 set_service_data(dev, dpc);
133 300
134 status = devm_request_irq(&dev->device, dev->irq, dpc_irq, IRQF_SHARED,301 status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
135 "pcie-dpc", dpc);302 "pcie-dpc", dpc);
136 if (status) {303 if (status) {
137 dev_warn(&dev->device, "request IRQ%d failed: %d\n", dev->irq,304 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
138 status);305 status);
139 return status;306 return status;
140 }307 }
@@ -147,7 +314,7 @@ static int dpc_probe(struct pcie_device *dev) · 6 unmodified lines
147 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;314 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
148 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);315 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
149 316
150 dev_info(&dev->device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",317 dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
151 cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),318 cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
152 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),319 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
153 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf,320 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf,
include/uapi/linux/pci_regs.h+10−0
@@ -961,6 +961,7 @@ · 960 unmodified lines
961#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */961#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
962#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */962#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
963#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */963#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
964#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */
964#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */965#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
965 966
966#define PCI_EXP_DPC_CTL 6 /* DPC control */967#define PCI_EXP_DPC_CTL 6 /* DPC control */
@@ -974,6 +975,15 @@ · 7 unmodified lines
974 975
975#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */976#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
976 977
978#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */
979#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */
980#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */
981#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */
982#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */
983#define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */
984#define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */
985#define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */
986
977/* Precision Time Measurement */987/* Precision Time Measurement */
978#define PCI_PTM_CAP 0x04 /* PTM Capability */988#define PCI_PTM_CAP 0x04 /* PTM Capability */
979#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */989#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */