History

net: stmmac: setup higher frequency clk support for EHL & TGL

EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk, ptp clock and ptp_max_adj to 200MHz.

Voon Weifeng committed 7 years ago

Commit 190f73a1 parent f6256583 files · +25 −0Browse files

Unified · Split

3 files
  1. drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +21 −0
  2. drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c +3 −0
  3. include/linux/stmmac.h +1 −0
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c+21−0
@@ -9,6 +9,7 @@ · 8 unmodified lines
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/10*******************************************************************************/
11 11
12#include <linux/clk-provider.h>
12#include <linux/pci.h>13#include <linux/pci.h>
13#include <linux/dmi.h>14#include <linux/dmi.h>
14 15
@@ -174,6 +175,19 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, · 159 unmodified lines
174 plat->axi->axi_blen[1] = 8;175 plat->axi->axi_blen[1] = 8;
175 plat->axi->axi_blen[2] = 16;176 plat->axi->axi_blen[2] = 16;
176 177
178 plat->ptp_max_adj = plat->clk_ptp_rate;
179
180 /* Set system clock */
181 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
182 "stmmac-clk", NULL, 0,
183 plat->clk_ptp_rate);
184
185 if (IS_ERR(plat->stmmac_clk)) {
186 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
187 plat->stmmac_clk = NULL;
188 }
189 clk_prepare_enable(plat->stmmac_clk);
190
177 /* Set default value for multicast hash bins */191 /* Set default value for multicast hash bins */
178 plat->multicast_filter_bins = HASH_TABLE_SIZE;192 plat->multicast_filter_bins = HASH_TABLE_SIZE;
179 193
@@ -193,6 +207,7 @@ static int ehl_common_data(struct pci_dev *pdev, · 13 unmodified lines
193 207
194 plat->rx_queues_to_use = 8;208 plat->rx_queues_to_use = 8;
195 plat->tx_queues_to_use = 8;209 plat->tx_queues_to_use = 8;
210 plat->clk_ptp_rate = 200000000;
196 ret = intel_mgbe_common_data(pdev, plat);211 ret = intel_mgbe_common_data(pdev, plat);
197 if (ret)212 if (ret)
198 return ret;213 return ret;
@@ -233,6 +248,7 @@ static int tgl_common_data(struct pci_dev *pdev, · 34 unmodified lines
233 248
234 plat->rx_queues_to_use = 6;249 plat->rx_queues_to_use = 6;
235 plat->tx_queues_to_use = 4;250 plat->tx_queues_to_use = 4;
251 plat->clk_ptp_rate = 200000000;
236 ret = intel_mgbe_common_data(pdev, plat);252 ret = intel_mgbe_common_data(pdev, plat);
237 if (ret)253 if (ret)
238 return ret;254 return ret;
@@ -438,10 +454,15 @@ static int stmmac_pci_probe(struct pci_dev *pdev, · 199 unmodified lines
438 */454 */
439static void stmmac_pci_remove(struct pci_dev *pdev)455static void stmmac_pci_remove(struct pci_dev *pdev)
440{456{
457 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
458 struct stmmac_priv *priv = netdev_priv(ndev);
441 int i;459 int i;
442 460
443 stmmac_dvr_remove(&pdev->dev);461 stmmac_dvr_remove(&pdev->dev);
444 462
463 if (priv->plat->stmmac_clk)
464 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
465
445 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {466 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
446 if (pci_resource_len(pdev, i) == 0)467 if (pci_resource_len(pdev, i) == 0)
447 continue;468 continue;
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c+3−0
@@ -194,6 +194,9 @@ void stmmac_ptp_register(struct stmmac_priv *priv) · 193 unmodified lines
194 priv->pps[i].available = true;194 priv->pps[i].available = true;
195 }195 }
196 196
197 if (priv->plat->ptp_max_adj)
198 stmmac_ptp_clock_ops.max_adj = priv->plat->ptp_max_adj;
199
197 stmmac_ptp_clock_ops.n_per_out = priv->dma_cap.pps_out_num;200 stmmac_ptp_clock_ops.n_per_out = priv->dma_cap.pps_out_num;
198 201
199 spin_lock_init(&priv->ptp_lock);202 spin_lock_init(&priv->ptp_lock);
include/linux/stmmac.h+1−0
@@ -168,6 +168,7 @@ struct plat_stmmacenet_data { · 167 unmodified lines
168 struct clk *clk_ptp_ref;168 struct clk *clk_ptp_ref;
169 unsigned int clk_ptp_rate;169 unsigned int clk_ptp_rate;
170 unsigned int clk_ref_rate;170 unsigned int clk_ref_rate;
171 s32 ptp_max_adj;
171 struct reset_control *stmmac_rst;172 struct reset_control *stmmac_rst;
172 struct stmmac_axi *axi;173 struct stmmac_axi *axi;
173 int has_gmac4;174 int has_gmac4;

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