net: stmmac: setup higher frequency clk support for EHL & TGL

EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk, ptp clock and ptp_max_adj to 200MHz.

Voon Weifeng committed 7 years ago

Commit 190f73a1 parent f6256583 files · +25 −0Browse files

Showing the changes to include/linux (1 of 3 files). Show all

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@@ -168,6 +168,7 @@ struct plat_stmmacenet_data { · 167 unmodified lines
168	struct clk *clk_ptp_ref;	168	struct clk *clk_ptp_ref;
169	unsigned int clk_ptp_rate;	169	unsigned int clk_ptp_rate;
170	unsigned int clk_ref_rate;	170	unsigned int clk_ref_rate;
		171	s32 ptp_max_adj;
171	struct reset_control *stmmac_rst;	172	struct reset_control *stmmac_rst;
172	struct stmmac_axi *axi;	173	struct stmmac_axi *axi;
173	int has_gmac4;	174	int has_gmac4;

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