Pull PCI update from Bjorn Helgaas: "Host bridge hotplug: - Untangle _PRT from struct pci_bus (Bjorn Helgaas) - Request _OSC control before scanning root bus (Taku Izumi) - Assign resources when adding host bridge (Yinghai Lu) - Remove root bus when removing host bridge (Yinghai Lu) - Remove _PRT during hot remove (Yinghai Lu) SRIOV - Add sysfs knobs to control numVFs (Don Dutile) Power management - Notify devices when power resource turned on (Huang Ying) Bug fixes - Work around broken _SEG on HP xw9300 (Bjorn Helgaas) - Keep runtime PM enabled for unbound PCI devices (Huang Ying) - Fix Optimus dual-GPU runtime D3 suspend issue (Dave Airlie) - Fix xen frontend shutdown issue (David Vrabel) - Work around PLX PCI 9050 BAR alignment erratum (Ian Abbott) Miscellaneous - Add GPL license for drivers/pci/ioapic (Andrew Cooks) - Add standard PCI-X, PCIe ASPM register #defines (Bjorn Helgaas) - NumaChip remote PCI support (Daniel Blueman) - Fix PCIe Link Capabilities Supported Link Speed definition (Jingoo Han) - Convert dev_printk() to dev_info(), etc (Joe Perches) - Add support for non PCI BAR ROM data (Matthew Garrett) - Add x86 support for host bridge translation offset (Mike Yoknis) - Report success only when every driver supports AER (Vijay Pandarathil)" Fix up trivial conflicts. * tag 'for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (48 commits) PCI: Use phys_addr_t for physical ROM address x86/PCI: Add NumaChip remote PCI support ath9k: Use standard #defines for PCIe Capability ASPM fields iwlwifi: Use standard #defines for PCIe Capability ASPM fields iwlwifi: collapse wrapper for pcie_capability_read_word() iwlegacy: Use standard #defines for PCIe Capability ASPM fields iwlegacy: collapse wrapper for pcie_capability_read_word() cxgb3: Use standard #defines for PCIe Capability ASPM fields PCI: Add standard PCIe Capability Link ASPM field names PCI/portdrv: Use PCI Express Capability accessors PCI: Use standard PCIe Capability Link register field names x86: Use PCI setup data PCI: Add support for non-BAR ROMs PCI: Add pcibios_add_device EFI: Stash ROMs if they're not in the PCI BAR PCI: Add and use standard PCI-X Capability register names PCI/PM: Keep runtime PM enabled for unbound PCI devices xen-pcifront: Handle backend CLOSED without CLOSING PCI: SRIOV control and status via sysfs (documentation) PCI/AER: Report success only when every device has AER-aware driver ...
Showing the changes to include/uapi/linux (1 of 45 files). Show all
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| @@ -349,7 +349,7 @@ · 348 unmodified lines | |||
| 349 | #define PCI_AF_STATUS_TP 0x01 | 349 | #define PCI_AF_STATUS_TP 0x01 |
| 350 | #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ | 350 | #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ |
| 351 | 351 | ||
| 352 | /* PCI-X registers */ | 352 | /* PCI-X registers (Type 0 (non-bridge) devices) */ |
| 353 | 353 | ||
| 354 | #define PCI_X_CMD 2 /* Modes & Features */ | 354 | #define PCI_X_CMD 2 /* Modes & Features */ |
| 355 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ | 355 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
| @@ -389,6 +389,19 @@ · 33 unmodified lines | |||
| 389 | #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ | 389 | #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ |
| 390 | #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ | 390 | #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ |
| 391 | 391 | ||
| 392 | /* PCI-X registers (Type 1 (bridge) devices) */ | ||
| 393 | |||
| 394 | #define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ | ||
| 395 | #define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ | ||
| 396 | #define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ | ||
| 397 | #define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ | ||
| 398 | #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ | ||
| 399 | #define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ | ||
| 400 | #define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ | ||
| 401 | #define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ | ||
| 402 | #define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ | ||
| 403 | #define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ | ||
| 404 | |||
| 392 | /* PCI Bridge Subsystem ID registers */ | 405 | /* PCI Bridge Subsystem ID registers */ |
| 393 | 406 | ||
| 394 | #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ | 407 | #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ |
| @@ -456,6 +469,8 @@ · 61 unmodified lines | |||
| 456 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ | 469 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ |
| 457 | #define PCI_EXP_LNKCTL 16 /* Link Control */ | 470 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
| 458 | #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ | 471 | #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ |
| 472 | #define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */ | ||
| 473 | #define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */ | ||
| 459 | #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ | 474 | #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ |
| 460 | #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ | 475 | #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ |
| 461 | #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ | 476 | #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ |
| @@ -544,9 +559,9 @@ · 82 unmodified lines | |||
| 544 | #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ | 559 | #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
| 545 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ | 560 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ |
| 546 | #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ | 561 | #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ |
| 547 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ | 562 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ |
| 548 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ | 563 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ |
| 549 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */ | 564 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ |
| 550 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ | 565 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ |
| 551 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ | 566 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
| 552 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ | 567 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |