Merge tag 'riscv-for-linus-6.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt: - A fix to match the CSR ASID masking rules when passing ASIDs to firmware - Force GCC to use ISA 2.2, to avoid a host of compatibily issues between toolchains * tag 'riscv-for-linus-6.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Handle zicsr/zifencei issues between clang and binutils riscv: mm: Fix incorrect ASID argument when flushing TLB

Linus Torvalds committed 3 years ago

Commit 19a6b662 parents 2495697 e89c2e85 files · +32 −6Browse files

Unified · Split

5 files

arch/riscv/Kconfig +22 −0
arch/riscv/Makefile +6 −4
arch/riscv/include/asm/tlbflush.h +2 −0
arch/riscv/mm/context.c +1 −1
arch/riscv/mm/tlbflush.c +1 −1

arch/riscv/Kconfig+22−0

@@ -464,6 +464,28 @@ config TOOLCHAIN_HAS_ZIHINTPAUSE · 463 unmodified lines
464	464	depends on !32BIT \|\| $(cc-option,-mabi=ilp32 -march=rv32ima_zihintpause)
465	465	depends on LLD_VERSION >= 150000 \|\| LD_VERSION >= 23600
466	466
	467	+config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
	468	+ def_bool y
	469	+ # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
	470	+ depends on AS_IS_GNU && AS_VERSION >= 23800
	471	+ help
	472	+ Newer binutils versions default to ISA spec version 20191213 which
	473	+ moves some instructions from the I extension to the Zicsr and Zifencei
	474	+ extensions.
	475	+
	476	+config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
	477	+ def_bool y
	478	+ depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
	479	+ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
	480	+ depends on CC_IS_CLANG && CLANG_VERSION < 170000
	481	+ help
	482	+ Certain versions of clang do not support zicsr and zifencei via -march
	483	+ but newer versions of binutils require it for the reasons noted in the
	484	+ help text of CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. This
	485	+ option causes an older ISA spec compatible with these older versions
	486	+ of clang to be passed to GAS, which has the same result as passing zicsr
	487	+ and zifencei to -march.
	488	+
467	489	config FPU
468	490	bool "FPU support"
469	491	default y

arch/riscv/Makefile+6−4

@@ -57,10 +57,12 @@ riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima · 56 unmodified lines
57	57	riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
58	58	riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
59	59
60		−# Newer binutils versions default to ISA spec version 20191213 which moves some
61		−# instructions from the I extension to the Zicsr and Zifencei extensions.
62		−toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
63		−riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
	60	+ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC
	61	+KBUILD_CFLAGS += -Wa,-misa-spec=2.2
	62	+KBUILD_AFLAGS += -Wa,-misa-spec=2.2
	63	+else
	64	+riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
	65	+endif
64	66
65	67	# Check if the toolchain supports Zihintpause extension
66	68	riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause

arch/riscv/include/asm/tlbflush.h+2−0

@@ -12,6 +12,8 @@ · 11 unmodified lines
12	12	#include <asm/errata_list.h>
13	13
14	14	#ifdef CONFIG_MMU
	15	+extern unsigned long asid_mask;
	16	+
15	17	static inline void local_flush_tlb_all(void)
16	18	{
17	19	__asm__ __volatile__ ("sfence.vma" : : : "memory");

arch/riscv/mm/context.c+1−1

@@ -22,7 +22,7 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); · 21 unmodified lines
22	22
23	23	static unsigned long asid_bits;
24	24	static unsigned long num_asids;
25		−static unsigned long asid_mask;
	25	+unsigned long asid_mask;
26	26
27	27	static atomic_long_t current_version;
28	28

arch/riscv/mm/tlbflush.c+1−1

@@ -42,7 +42,7 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, · 41 unmodified lines
42	42	/* check if the tlbflush needs to be sent to other CPUs */
43	43	broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
44	44	if (static_branch_unlikely(&use_asid_allocator)) {
45		− unsigned long asid = atomic_long_read(&mm->context.id);
	45	+ unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask;
46	46
47	47	if (broadcast) {
48	48	sbi_remote_sfence_vma_asid(cmask, start, size, asid);

Merge tag 'riscv-for-linus-6.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

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