Add L1 PM Substates Control 2 Register fields (PCI_L1SS_CTL2_*).
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| @@ -1088,6 +1088,8 @@ · 1087 unmodified lines | ||
| 1088 | 1088 | #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ |
| 1089 | 1089 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ |
| 1090 | 1090 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ |
| 1091 | +#define PCI_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */ | |
| 1092 | +#define PCI_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */ | |
| 1091 | 1093 | |
| 1092 | 1094 | /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ |
| 1093 | 1095 | #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ |