Merge tag 'dma-fence-deadline' into HEAD

This series adds a deadline hint to fences, so realtime deadlines such as vblank can be communicated to the fence signaller for power/ frequency management decisions. This is partially inspired by a trick i915 does, but implemented via dma-fence for a couple of reasons: 1) To continue to be able to use the atomic helpers 2) To support cases where display and gpu are different drivers See https://patchwork.freedesktop.org/series/93035/ This does not yet add any UAPI, although this will be needed in a number of cases: 1) Workloads "ping-ponging" between CPU and GPU, where we don't want the GPU freq governor to interpret time stalled waiting for GPU as "idle" time 2) Cases where the compositor is waiting for fences to be signaled before issuing the atomic ioctl, for example to maintain 60fps cursor updates even when the GPU is not able to maintain that framerate.

Rob Clark committed 3 years ago

Commit 1ad05102 parents 8559da8 d39e48c14 files · +303 −34Browse files

Unified · Split

14 files

Documentation/driver-api/dma-buf.rst +14 −2
drivers/dma-buf/dma-fence-array.c +11 −0
drivers/dma-buf/dma-fence-chain.c +12 −0
drivers/dma-buf/dma-fence.c +59 −0
drivers/dma-buf/dma-resv.c +22 −0
drivers/gpu/drm/drm_atomic_helper.c +37 −0
drivers/gpu/drm/drm_vblank.c +44 −9
drivers/gpu/drm/scheduler/sched_fence.c +46 −0
drivers/gpu/drm/scheduler/sched_main.c +1 −1
include/drm/drm_vblank.h +1 −0
include/drm/gpu_scheduler.h +17 −0
include/linux/dma-fence.h +22 −0
include/linux/dma-resv.h +2 −0
include/uapi/linux/sync_file.h +15 −22

Documentation/driver-api/dma-buf.rst+14−2

@@ -164,6 +164,12 @@ DMA Fence Signalling Annotations · 163 unmodified lines
164	164	.. kernel-doc:: drivers/dma-buf/dma-fence.c
165	165	:doc: fence signalling annotation
166	166
	167	+DMA Fence Deadline Hints
	168	+~~~~~~~~~~~~~~~~~~~~~~~~
	169	+
	170	+.. kernel-doc:: drivers/dma-buf/dma-fence.c
	171	+ :doc: deadline hints
	172	+
167	173	DMA Fences Functions Reference
168	174	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
169	175
@@ -197,8 +203,8 @@ DMA Fence unwrap · 27 unmodified lines
197	203	.. kernel-doc:: include/linux/dma-fence-unwrap.h
198	204	:internal:
199	205
200		−DMA Fence uABI/Sync File
201		−~~~~~~~~~~~~~~~~~~~~~~~~
	206	+DMA Fence Sync File
	207	+~~~~~~~~~~~~~~~~~~~
202	208
203	209	.. kernel-doc:: drivers/dma-buf/sync_file.c
204	210	:export:
@@ -206,6 +212,12 @@ DMA Fence uABI/Sync File · 1 unmodified line
206	212	.. kernel-doc:: include/linux/sync_file.h
207	213	:internal:
208	214
	215	+DMA Fence Sync File uABI
	216	+~~~~~~~~~~~~~~~~~~~~~~~~
	217	+
	218	+.. kernel-doc:: include/uapi/linux/sync_file.h
	219	+ :internal:
	220	+
209	221	Indefinite DMA Fences
210	222	~~~~~~~~~~~~~~~~~~~~~
211	223

drivers/dma-buf/dma-fence-array.c+11−0

@@ -123,12 +123,23 @@ static void dma_fence_array_release(struct dma_fence *fence) · 122 unmodified lines
123	123	dma_fence_free(fence);
124	124	}
125	125
	126	+static void dma_fence_array_set_deadline(struct dma_fence *fence,
	127	+ ktime_t deadline)
	128	+{
	129	+ struct dma_fence_array *array = to_dma_fence_array(fence);
	130	+ unsigned i;
	131	+
	132	+ for (i = 0; i < array->num_fences; ++i)
	133	+ dma_fence_set_deadline(array->fences[i], deadline);
	134	+}
	135	+
126	136	const struct dma_fence_ops dma_fence_array_ops = {
127	137	.get_driver_name = dma_fence_array_get_driver_name,
128	138	.get_timeline_name = dma_fence_array_get_timeline_name,
129	139	.enable_signaling = dma_fence_array_enable_signaling,
130	140	.signaled = dma_fence_array_signaled,
131	141	.release = dma_fence_array_release,
	142	+ .set_deadline = dma_fence_array_set_deadline,
132	143	};
133	144	EXPORT_SYMBOL(dma_fence_array_ops);
134	145

drivers/dma-buf/dma-fence-chain.c+12−0

@@ -206,6 +206,17 @@ static void dma_fence_chain_release(struct dma_fence *fence) · 205 unmodified lines
206	206	dma_fence_free(fence);
207	207	}
208	208
	209	+
	210	+static void dma_fence_chain_set_deadline(struct dma_fence *fence,
	211	+ ktime_t deadline)
	212	+{
	213	+ dma_fence_chain_for_each(fence, fence) {
	214	+ struct dma_fence *f = dma_fence_chain_contained(fence);
	215	+
	216	+ dma_fence_set_deadline(f, deadline);
	217	+ }
	218	+}
	219	+
209	220	const struct dma_fence_ops dma_fence_chain_ops = {
210	221	.use_64bit_seqno = true,
211	222	.get_driver_name = dma_fence_chain_get_driver_name,
@@ -213,6 +224,7 @@ const struct dma_fence_ops dma_fence_chain_ops = { · 1 unmodified line
213	224	.enable_signaling = dma_fence_chain_enable_signaling,
214	225	.signaled = dma_fence_chain_signaled,
215	226	.release = dma_fence_chain_release,
	227	+ .set_deadline = dma_fence_chain_set_deadline,
216	228	};
217	229	EXPORT_SYMBOL(dma_fence_chain_ops);
218	230

drivers/dma-buf/dma-fence.c+59−0

@@ -912,6 +912,65 @@ err_free_cb: · 911 unmodified lines
912	912	}
913	913	EXPORT_SYMBOL(dma_fence_wait_any_timeout);
914	914
	915	+/**
	916	+ * DOC: deadline hints
	917	+ *
	918	+ * In an ideal world, it would be possible to pipeline a workload sufficiently
	919	+ * that a utilization based device frequency governor could arrive at a minimum
	920	+ * frequency that meets the requirements of the use-case, in order to minimize
	921	+ * power consumption. But in the real world there are many workloads which
	922	+ * defy this ideal. For example, but not limited to:
	923	+ *
	924	+ * * Workloads that ping-pong between device and CPU, with alternating periods
	925	+ * of CPU waiting for device, and device waiting on CPU. This can result in
	926	+ * devfreq and cpufreq seeing idle time in their respective domains and in
	927	+ * result reduce frequency.
	928	+ *
	929	+ * * Workloads that interact with a periodic time based deadline, such as double
	930	+ * buffered GPU rendering vs vblank sync'd page flipping. In this scenario,
	931	+ * missing a vblank deadline results in an increase in idle time on the GPU
	932	+ * (since it has to wait an additional vblank period), sending a signal to
	933	+ * the GPU's devfreq to reduce frequency, when in fact the opposite is what is
	934	+ * needed.
	935	+ *
	936	+ * To this end, deadline hint(s) can be set on a &dma_fence via &dma_fence_set_deadline.
	937	+ * The deadline hint provides a way for the waiting driver, or userspace, to
	938	+ * convey an appropriate sense of urgency to the signaling driver.
	939	+ *
	940	+ * A deadline hint is given in absolute ktime (CLOCK_MONOTONIC for userspace
	941	+ * facing APIs). The time could either be some point in the future (such as
	942	+ * the vblank based deadline for page-flipping, or the start of a compositor's
	943	+ * composition cycle), or the current time to indicate an immediate deadline
	944	+ * hint (Ie. forward progress cannot be made until this fence is signaled).
	945	+ *
	946	+ * Multiple deadlines may be set on a given fence, even in parallel. See the
	947	+ * documentation for &dma_fence_ops.set_deadline.
	948	+ *
	949	+ * The deadline hint is just that, a hint. The driver that created the fence
	950	+ * may react by increasing frequency, making different scheduling choices, etc.
	951	+ * Or doing nothing at all.
	952	+ */
	953	+
	954	+/**
	955	+ * dma_fence_set_deadline - set desired fence-wait deadline hint
	956	+ * @fence: the fence that is to be waited on
	957	+ * @deadline: the time by which the waiter hopes for the fence to be
	958	+ * signaled
	959	+ *
	960	+ * Give the fence signaler a hint about an upcoming deadline, such as
	961	+ * vblank, by which point the waiter would prefer the fence to be
	962	+ * signaled by. This is intended to give feedback to the fence signaler
	963	+ * to aid in power management decisions, such as boosting GPU frequency
	964	+ * if a periodic vblank deadline is approaching but the fence is not
	965	+ * yet signaled..
	966	+ */
	967	+void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
	968	+{
	969	+ if (fence->ops->set_deadline && !dma_fence_is_signaled(fence))
	970	+ fence->ops->set_deadline(fence, deadline);
	971	+}
	972	+EXPORT_SYMBOL(dma_fence_set_deadline);
	973	+
915	974	/**
916	975	* dma_fence_describe - Dump fence describtion into seq_file
917	976	* @fence: the 6fence to describe

drivers/dma-buf/dma-resv.c+22−0

@@ -684,6 +684,28 @@ long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage, · 683 unmodified lines
684	684	}
685	685	EXPORT_SYMBOL_GPL(dma_resv_wait_timeout);
686	686
	687	+/**
	688	+ * dma_resv_set_deadline - Set a deadline on reservation's objects fences
	689	+ * @obj: the reservation object
	690	+ * @usage: controls which fences to include, see enum dma_resv_usage.
	691	+ * @deadline: the requested deadline (MONOTONIC)
	692	+ *
	693	+ * May be called without holding the dma_resv lock. Sets @deadline on
	694	+ * all fences filtered by @usage.
	695	+ */
	696	+void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage,
	697	+ ktime_t deadline)
	698	+{
	699	+ struct dma_resv_iter cursor;
	700	+ struct dma_fence *fence;
	701	+
	702	+ dma_resv_iter_begin(&cursor, obj, usage);
	703	+ dma_resv_for_each_fence_unlocked(&cursor, fence) {
	704	+ dma_fence_set_deadline(fence, deadline);
	705	+ }
	706	+ dma_resv_iter_end(&cursor);
	707	+}
	708	+EXPORT_SYMBOL_GPL(dma_resv_set_deadline);
687	709
688	710	/**
689	711	* dma_resv_test_signaled - Test if a reservation object's fences have been

drivers/gpu/drm/drm_atomic_helper.c+37−0

@@ -1511,6 +1511,41 @@ void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, · 1510 unmodified lines
1511	1511	}
1512	1512	EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables);
1513	1513
	1514	+/*
	1515	+ * For atomic updates which touch just a single CRTC, calculate the time of the
	1516	+ * next vblank, and inform all the fences of the deadline.
	1517	+ */
	1518	+static void set_fence_deadline(struct drm_device *dev,
	1519	+ struct drm_atomic_state *state)
	1520	+{
	1521	+ struct drm_crtc *crtc;
	1522	+ struct drm_crtc_state *new_crtc_state;
	1523	+ struct drm_plane *plane;
	1524	+ struct drm_plane_state *new_plane_state;
	1525	+ ktime_t vbltime = 0;
	1526	+ int i;
	1527	+
	1528	+ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
	1529	+ ktime_t v;
	1530	+
	1531	+ if (drm_crtc_next_vblank_start(crtc, &v))
	1532	+ continue;
	1533	+
	1534	+ if (!vbltime \|\| ktime_before(v, vbltime))
	1535	+ vbltime = v;
	1536	+ }
	1537	+
	1538	+ /* If no CRTCs updated, then nothing to do: */
	1539	+ if (!vbltime)
	1540	+ return;
	1541	+
	1542	+ for_each_new_plane_in_state (state, plane, new_plane_state, i) {
	1543	+ if (!new_plane_state->fence)
	1544	+ continue;
	1545	+ dma_fence_set_deadline(new_plane_state->fence, vbltime);
	1546	+ }
	1547	+}
	1548	+
1514	1549	/**
1515	1550	* drm_atomic_helper_wait_for_fences - wait for fences stashed in plane state
1516	1551	* @dev: DRM device
@@ -1540,6 +1575,8 @@ int drm_atomic_helper_wait_for_fences(struct drm_device *dev, · 23 unmodified lines
1540	1575	struct drm_plane_state *new_plane_state;
1541	1576	int i, ret;
1542	1577
	1578	+ set_fence_deadline(dev, state);
	1579	+
1543	1580	for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1544	1581	if (!new_plane_state->fence)
1545	1582	continue;

drivers/gpu/drm/drm_vblank.c+44−9

@@ -844,10 +844,9 @@ bool drm_crtc_vblank_helper_get_vblank_timestamp(struct drm_crtc *crtc, · 843 unmodified lines
844	844	EXPORT_SYMBOL(drm_crtc_vblank_helper_get_vblank_timestamp);
845	845
846	846	/**
847		− * drm_get_last_vbltimestamp - retrieve raw timestamp for the most recent
848		− * vblank interval
849		− * @dev: DRM device
850		− * @pipe: index of CRTC whose vblank timestamp to retrieve
	847	+ * drm_crtc_get_last_vbltimestamp - retrieve raw timestamp for the most
	848	+ * recent vblank interval
	849	+ * @crtc: CRTC whose vblank timestamp to retrieve
851	850	* @tvblank: Pointer to target time which should receive the timestamp
852	851	* @in_vblank_irq:
853	852	* True when called from drm_crtc_handle_vblank(). Some drivers
@@ -865,10 +864,9 @@ EXPORT_SYMBOL(drm_crtc_vblank_helper_get_vblank_timestamp); · 11 unmodified lines
865	864	* True if timestamp is considered to be very precise, false otherwise.
866	865	*/
867	866	static bool
868		−drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
869		− ktime_t *tvblank, bool in_vblank_irq)
	867	+drm_crtc_get_last_vbltimestamp(struct drm_crtc crtc, ktime_t tvblank,
	868	+ bool in_vblank_irq)
870	869	{
871		− struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
872	870	bool ret = false;
873	871
874	872	/* Define requested maximum error on timestamps (nanoseconds). */
@@ -876,8 +874,6 @@ drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe, · 1 unmodified line
876	874
877	875	/* Query driver if possible and precision timestamping enabled. */
878	876	if (crtc && crtc->funcs->get_vblank_timestamp && max_error > 0) {
879		− struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
880		−
881	877	ret = crtc->funcs->get_vblank_timestamp(crtc, &max_error,
882	878	tvblank, in_vblank_irq);
883	879	}
@@ -891,6 +887,15 @@ drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe, · 7 unmodified lines
891	887	return ret;
892	888	}
893	889
	890	+static bool
	891	+drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
	892	+ ktime_t *tvblank, bool in_vblank_irq)
	893	+{
	894	+ struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
	895	+
	896	+ return drm_crtc_get_last_vbltimestamp(crtc, tvblank, in_vblank_irq);
	897	+}
	898	+
894	899	/**
895	900	* drm_crtc_vblank_count - retrieve "cooked" vblank counter value
896	901	* @crtc: which counter to retrieve
@@ -980,6 +985,36 @@ u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc, · 83 unmodified lines
980	985	}
981	986	EXPORT_SYMBOL(drm_crtc_vblank_count_and_time);
982	987
	988	+/**
	989	+ * drm_crtc_next_vblank_start - calculate the time of the next vblank
	990	+ * @crtc: the crtc for which to calculate next vblank time
	991	+ * @vblanktime: pointer to time to receive the next vblank timestamp.
	992	+ *
	993	+ * Calculate the expected time of the start of the next vblank period,
	994	+ * based on time of previous vblank and frame duration
	995	+ */
	996	+int drm_crtc_next_vblank_start(struct drm_crtc crtc, ktime_t vblanktime)
	997	+{
	998	+ unsigned int pipe = drm_crtc_index(crtc);
	999	+ struct drm_vblank_crtc *vblank = &crtc->dev->vblank[pipe];
	1000	+ struct drm_display_mode *mode = &vblank->hwmode;
	1001	+ u64 vblank_start;
	1002	+
	1003	+ if (!vblank->framedur_ns \|\| !vblank->linedur_ns)
	1004	+ return -EINVAL;
	1005	+
	1006	+ if (!drm_crtc_get_last_vbltimestamp(crtc, vblanktime, false))
	1007	+ return -EINVAL;
	1008	+
	1009	+ vblank_start = DIV_ROUND_DOWN_ULL(
	1010	+ (u64)vblank->framedur_ns * mode->crtc_vblank_start,
	1011	+ mode->crtc_vtotal);
	1012	+ vblanktime = ktime_add(vblanktime, ns_to_ktime(vblank_start));
	1013	+
	1014	+ return 0;
	1015	+}
	1016	+EXPORT_SYMBOL(drm_crtc_next_vblank_start);
	1017	+
983	1018	static void send_vblank_event(struct drm_device *dev,
984	1019	struct drm_pending_vblank_event *e,
985	1020	u64 seq, ktime_t now)

drivers/gpu/drm/scheduler/sched_fence.c+46−0

@@ -123,6 +123,37 @@ static void drm_sched_fence_release_finished(struct dma_fence *f) · 122 unmodified lines
123	123	dma_fence_put(&fence->scheduled);
124	124	}
125	125
	126	+static void drm_sched_fence_set_deadline_finished(struct dma_fence *f,
	127	+ ktime_t deadline)
	128	+{
	129	+ struct drm_sched_fence *fence = to_drm_sched_fence(f);
	130	+ struct dma_fence *parent;
	131	+ unsigned long flags;
	132	+
	133	+ spin_lock_irqsave(&fence->lock, flags);
	134	+
	135	+ /* If we already have an earlier deadline, keep it: */
	136	+ if (test_bit(DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags) &&
	137	+ ktime_before(fence->deadline, deadline)) {
	138	+ spin_unlock_irqrestore(&fence->lock, flags);
	139	+ return;
	140	+ }
	141	+
	142	+ fence->deadline = deadline;
	143	+ set_bit(DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags);
	144	+
	145	+ spin_unlock_irqrestore(&fence->lock, flags);
	146	+
	147	+ /*
	148	+ * smp_load_aquire() to ensure that if we are racing another
	149	+ * thread calling drm_sched_fence_set_parent(), that we see
	150	+ * the parent set before it calls test_bit(HAS_DEADLINE_BIT)
	151	+ */
	152	+ parent = smp_load_acquire(&fence->parent);
	153	+ if (parent)
	154	+ dma_fence_set_deadline(parent, deadline);
	155	+}
	156	+
126	157	static const struct dma_fence_ops drm_sched_fence_ops_scheduled = {
127	158	.get_driver_name = drm_sched_fence_get_driver_name,
128	159	.get_timeline_name = drm_sched_fence_get_timeline_name,
@@ -133,6 +164,7 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = { · 4 unmodified lines
133	164	.get_driver_name = drm_sched_fence_get_driver_name,
134	165	.get_timeline_name = drm_sched_fence_get_timeline_name,
135	166	.release = drm_sched_fence_release_finished,
	167	+ .set_deadline = drm_sched_fence_set_deadline_finished,
136	168	};
137	169
138	170	struct drm_sched_fence to_drm_sched_fence(struct dma_fence f)
@@ -147,6 +179,20 @@ struct drm_sched_fence to_drm_sched_fence(struct dma_fence f) · 8 unmodified lines
147	179	}
148	180	EXPORT_SYMBOL(to_drm_sched_fence);
149	181
	182	+void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence,
	183	+ struct dma_fence *fence)
	184	+{
	185	+ /*
	186	+ * smp_store_release() to ensure another thread racing us
	187	+ * in drm_sched_fence_set_deadline_finished() sees the
	188	+ * fence's parent set before test_bit()
	189	+ */
	190	+ smp_store_release(&s_fence->parent, dma_fence_get(fence));
	191	+ if (test_bit(DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT,
	192	+ &s_fence->finished.flags))
	193	+ dma_fence_set_deadline(fence, s_fence->deadline);
	194	+}
	195	+
150	196	struct drm_sched_fence drm_sched_fence_alloc(struct drm_sched_entity entity,
151	197	void *owner)
152	198	{

drivers/gpu/drm/scheduler/sched_main.c+1−1

@@ -1048,7 +1048,7 @@ static int drm_sched_main(void *param) · 1047 unmodified lines
1048	1048	drm_sched_fence_scheduled(s_fence);
1049	1049
1050	1050	if (!IS_ERR_OR_NULL(fence)) {
1051		− s_fence->parent = dma_fence_get(fence);
	1051	+ drm_sched_fence_set_parent(s_fence, fence);
1052	1052	/* Drop for original kref_init of the fence */
1053	1053	dma_fence_put(fence);
1054	1054

include/drm/drm_vblank.h+1−0

@@ -230,6 +230,7 @@ bool drm_dev_has_vblank(const struct drm_device *dev); · 229 unmodified lines
230	230	u64 drm_crtc_vblank_count(struct drm_crtc *crtc);
231	231	u64 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
232	232	ktime_t *vblanktime);
	233	+int drm_crtc_next_vblank_start(struct drm_crtc crtc, ktime_t vblanktime);
233	234	void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
234	235	struct drm_pending_vblank_event *e);
235	236	void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,

include/drm/gpu_scheduler.h+17−0

@@ -41,6 +41,15 @@ · 40 unmodified lines
41	41	*/
42	42	#define DRM_SCHED_FENCE_DONT_PIPELINE DMA_FENCE_FLAG_USER_BITS
43	43
	44	+/**
	45	+ * DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT - A fence deadline hint has been set
	46	+ *
	47	+ * Because we could have a deadline hint can be set before the backing hw
	48	+ * fence is created, we need to keep track of whether a deadline has already
	49	+ * been set.
	50	+ */
	51	+#define DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT (DMA_FENCE_FLAG_USER_BITS + 1)
	52	+
44	53	enum dma_resv_usage;
45	54	struct dma_resv;
46	55	struct drm_gem_object;
@@ -282,6 +291,12 @@ struct drm_sched_fence { · 235 unmodified lines
282	291	*/
283	292	struct dma_fence finished;
284	293
	294	+ /**
	295	+ * @deadline: deadline set on &drm_sched_fence.finished which
	296	+ * potentially needs to be propagated to &drm_sched_fence.parent
	297	+ */
	298	+ ktime_t deadline;
	299	+
285	300	/**
286	301	* @parent: the fence returned by &drm_sched_backend_ops.run_job
287	302	* when scheduling the job on hardware. We signal the
@@ -574,6 +589,8 @@ void drm_sched_entity_set_priority(struct drm_sched_entity *entity, · 286 unmodified lines
574	589	enum drm_sched_priority priority);
575	590	bool drm_sched_entity_is_ready(struct drm_sched_entity *entity);
576	591
	592	+void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence,
	593	+ struct dma_fence *fence);
577	594	struct drm_sched_fence *drm_sched_fence_alloc(
578	595	struct drm_sched_entity s_entity, void owner);
579	596	void drm_sched_fence_init(struct drm_sched_fence *fence,

include/linux/dma-fence.h+22−0

@@ -257,6 +257,26 @@ struct dma_fence_ops { · 256 unmodified lines
257	257	*/
258	258	void (timeline_value_str)(struct dma_fence fence,
259	259	char *str, int size);
	260	+
	261	+ /**
	262	+ * @set_deadline:
	263	+ *
	264	+ * Callback to allow a fence waiter to inform the fence signaler of
	265	+ * an upcoming deadline, such as vblank, by which point the waiter
	266	+ * would prefer the fence to be signaled by. This is intended to
	267	+ * give feedback to the fence signaler to aid in power management
	268	+ * decisions, such as boosting GPU frequency.
	269	+ *
	270	+ * This is called without &dma_fence.lock held, it can be called
	271	+ * multiple times and from any context. Locking is up to the callee
	272	+ * if it has some state to manage. If multiple deadlines are set,
	273	+ * the expectation is to track the soonest one. If the deadline is
	274	+ * before the current time, it should be interpreted as an immediate
	275	+ * deadline.
	276	+ *
	277	+ * This callback is optional.
	278	+ */
	279	+ void (set_deadline)(struct dma_fence fence, ktime_t deadline);
260	280	};
261	281
262	282	void dma_fence_init(struct dma_fence fence, const struct dma_fence_ops ops,
@@ -583,6 +603,8 @@ static inline signed long dma_fence_wait(struct dma_fence *fence, bool intr) · 320 unmodified lines
583	603	return ret < 0 ? ret : 0;
584	604	}
585	605
	606	+void dma_fence_set_deadline(struct dma_fence *fence, ktime_t deadline);
	607	+
586	608	struct dma_fence *dma_fence_get_stub(void);
587	609	struct dma_fence *dma_fence_allocate_private_stub(void);
588	610	u64 dma_fence_context_alloc(unsigned num);

include/linux/dma-resv.h+2−0

@@ -479,6 +479,8 @@ int dma_resv_get_singleton(struct dma_resv *obj, enum dma_resv_usage usage, · 478 unmodified lines
479	479	int dma_resv_copy_fences(struct dma_resv dst, struct dma_resv src);
480	480	long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage,
481	481	bool intr, unsigned long timeout);
	482	+void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage,
	483	+ ktime_t deadline);
482	484	bool dma_resv_test_signaled(struct dma_resv *obj, enum dma_resv_usage usage);
483	485	void dma_resv_describe(struct dma_resv obj, struct seq_file seq);
484	486

include/uapi/linux/sync_file.h+15−22

@@ -16,12 +16,16 @@ · 15 unmodified lines
16	16	#include <linux/types.h>
17	17
18	18	/**
19		− * struct sync_merge_data - data passed to merge ioctl
	19	+ * struct sync_merge_data - SYNC_IOC_MERGE: merge two fences
20	20	* @name: name of new fence
21	21	* @fd2: file descriptor of second fence
22	22	* @fence: returns the fd of the new fence to userspace
23	23	* @flags: merge_data flags
24	24	* @pad: padding for 64-bit alignment, should always be zero
	25	+ *
	26	+ * Creates a new fence containing copies of the sync_pts in both
	27	+ * the calling fd and sync_merge_data.fd2. Returns the new fence's
	28	+ * fd in sync_merge_data.fence
25	29	*/
26	30	struct sync_merge_data {
27	31	char name[32];
@@ -34,8 +38,8 @@ struct sync_merge_data { · 6 unmodified lines
34	38	/**
35	39	* struct sync_fence_info - detailed fence information
36	40	* @obj_name: name of parent sync_timeline
37		−* @driver_name: name of driver implementing the parent
38		−* @status: status of the fence 0:active 1:signaled <0:error
	41	+ * @driver_name: name of driver implementing the parent
	42	+ * @status: status of the fence 0:active 1:signaled <0:error
39	43	* @flags: fence_info flags
40	44	* @timestamp_ns: timestamp of status change in nanoseconds
41	45	*/
@@ -48,14 +52,19 @@ struct sync_fence_info { · 6 unmodified lines
48	52	};
49	53
50	54	/**
51		− * struct sync_file_info - data returned from fence info ioctl
	55	+ * struct sync_file_info - SYNC_IOC_FILE_INFO: get detailed information on a sync_file
52	56	* @name: name of fence
53	57	* @status: status of fence. 1: signaled 0:active <0:error
54	58	* @flags: sync_file_info flags
55	59	* @num_fences number of fences in the sync_file
56	60	* @pad: padding for 64-bit alignment, should always be zero
57		− * @sync_fence_info: pointer to array of structs sync_fence_info with all
	61	+ * @sync_fence_info: pointer to array of struct &sync_fence_info with all
58	62	* fences in the sync_file
	63	+ *
	64	+ * Takes a struct sync_file_info. If num_fences is 0, the field is updated
	65	+ * with the actual number of fences. If num_fences is > 0, the system will
	66	+ * use the pointer provided on sync_fence_info to return up to num_fences of
	67	+ * struct sync_fence_info, with detailed fence information.
59	68	*/
60	69	struct sync_file_info {
61	70	char name[32];
@@ -69,30 +78,14 @@ struct sync_file_info { · 7 unmodified lines
69	78
70	79	#define SYNC_IOC_MAGIC '>'
71	80
72		−/**
	81	+/*
73	82	* Opcodes 0, 1 and 2 were burned during a API change to avoid users of the
74	83	* old API to get weird errors when trying to handling sync_files. The API
75	84	* change happened during the de-stage of the Sync Framework when there was
76	85	* no upstream users available.
77	86	*/
78	87
79		−/**
80		− * DOC: SYNC_IOC_MERGE - merge two fences
81		− *
82		− * Takes a struct sync_merge_data. Creates a new fence containing copies of
83		− * the sync_pts in both the calling fd and sync_merge_data.fd2. Returns the
84		− * new fence's fd in sync_merge_data.fence
85		− */
86	88	#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 3, struct sync_merge_data)
87		−
88		−/**
89		− * DOC: SYNC_IOC_FILE_INFO - get detailed information on a sync_file
90		− *
91		− * Takes a struct sync_file_info. If num_fences is 0, the field is updated
92		− * with the actual number of fences. If num_fences is > 0, the system will
93		− * use the pointer provided on sync_fence_info to return up to num_fences of
94		− * struct sync_fence_info, with detailed fence information.
95		− */
96	89	#define SYNC_IOC_FILE_INFO _IOWR(SYNC_IOC_MAGIC, 4, struct sync_file_info)
97	90
98	91	#endif /* _UAPI_LINUX_SYNC_H */

Merge tag 'dma-fence-deadline' into HEAD

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