Pull PCI updates from Bjorn Helgaas: - detach driver before tearing down procfs/sysfs (Alex Williamson) - disable PCIe services during shutdown (Sinan Kaya) - fix ASPM oops on systems with no Root Ports (Ard Biesheuvel) - fix ASPM LTR_L1.2_THRESHOLD programming (Bjorn Helgaas) - fix ASPM Common_Mode_Restore_Time computation (Bjorn Helgaas) - fix portdrv MSI/MSI-X vector allocation (Dongdong Liu, Bjorn Helgaas) - report non-fatal AER errors only to the affected endpoint (Gabriele Paoloni) - distribute bus numbers, MMIO, and I/O space among hotplug bridges to allow more devices to be hot-added (Mika Westerberg) - fix pciehp races during initialization and surprise link down (Mika Westerberg) - handle surprise-removed devices in PME handling (Qiang) - support resizable BARs for large graphics devices (Christian König) - expose SR-IOV offset, stride, and VF device ID via sysfs (Filippo Sironi) - create SR-IOV virtfn/physfn sysfs links before attaching driver (Stuart Hayes) - fix SR-IOV "ARI Capable Hierarchy" restore issue (Tony Nguyen) - enforce Kconfig IOV/REALLOC dependency (Sascha El-Sharkawy) - avoid slot reset if bridge itself is broken (Jan Glauber) - clean up pci_reset_function() path (Jan H. Schönherr) - make pci_map_rom() fail if the option ROM is invalid (Changbin Du) - convert timers to timer_setup() (Kees Cook) - move PCI_QUIRKS to PCI bus Kconfig menu (Randy Dunlap) - constify pci_dev_type and intel_mid_pci_ops (Bhumika Goyal) - remove unnecessary pci_dev, pci_bus, resource, pcibios_set_master() declarations (Bjorn Helgaas) - fix endpoint framework overflows and BUG()s (Dan Carpenter) - fix endpoint framework issues (Kishon Vijay Abraham I) - avoid broken Cavium CN8xxx bus reset behavior (David Daney) - extend Cavium ACS capability quirks (Vadim Lomovtsev) - support Synopsys DesignWare RC in ECAM mode (Ard Biesheuvel) - turn off dra7xx clocks cleanly on shutdown (Keerthy) - fix Faraday probe error path (Wei Yongjun) - support HiSilicon STB SoC PCIe host controller (Jianguo Sun) - fix Hyper-V interrupt affinity issue (Dexuan Cui) - remove useless ACPI warning for Hyper-V pass-through devices (Vitaly Kuznetsov) - support multiple MSI on iProc (Sandor Bodo-Merle) - support Layerscape LS1012a and LS1046a PCIe host controllers (Hou Zhiqiang) - fix Layerscape default error response (Minghuan Lian) - support MSI on Tango host controller (Marc Gonzalez) - support Tegra186 PCIe host controller (Manikanta Maddireddy) - use generic accessors on Tegra when possible (Thierry Reding) - support V3 Semiconductor PCI host controller (Linus Walleij) * tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (85 commits) PCI/ASPM: Add L1 Substates definitions PCI/ASPM: Reformat ASPM register definitions PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time PCI: xgene: Rename xgene_pcie_probe_bridge() to xgene_pcie_probe() PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up() PCI: altera: Rename altera_pcie_link_is_up() to altera_pcie_link_up() PCI: Fix kernel-doc build warning PCI: Fail pci_map_rom() if the option ROM is invalid PCI: Move pci_map_rom() error path PCI: Move PCI_QUIRKS to the PCI bus menu alpha/PCI: Make pdev_save_srm_config() static PCI: Remove unused declarations PCI: Remove redundant pci_dev, pci_bus, resource declarations PCI: Remove redundant pcibios_set_master() declarations PCI/PME: Handle invalid data when reading Root Status PCI: hv: Use effective affinity mask PCI: pciehp: Do not clear Presence Detect Changed during initialization PCI: pciehp: Fix race condition handling surprise link down PCI: Distribute available resources to hotplug-capable bridges ...
Showing the changes to include/uapi/linux (1 of 87 files). Show all
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| @@ -747,6 +747,7 @@ · 746 unmodified lines | ||
| 747 | 747 | #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ |
| 748 | 748 | #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ |
| 749 | 749 | #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ |
| 750 | +#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ | |
| 750 | 751 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
| 751 | 752 | |
| 752 | 753 | /* Virtual Channel */ |
| @@ -940,9 +941,13 @@ · 187 unmodified lines | ||
| 940 | 941 | #define PCI_SATA_SIZEOF_LONG 16 |
| 941 | 942 | |
| 942 | 943 | /* Resizable BARs */ |
| 944 | +#define PCI_REBAR_CAP 4 /* capability register */ | |
| 945 | +#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */ | |
| 943 | 946 | #define PCI_REBAR_CTRL 8 /* control register */ |
| 944 | −#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ | |
| 945 | −#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ | |
| 947 | +#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ | |
| 948 | +#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ | |
| 949 | +#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ | |
| 950 | +#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ | |
| 946 | 951 | |
| 947 | 952 | /* Dynamic Power Allocation */ |
| 948 | 953 | #define PCI_DPA_CAP 4 /* capability register */ |
| @@ -961,6 +966,7 @@ · 12 unmodified lines | ||
| 961 | 966 | |
| 962 | 967 | /* Downstream Port Containment */ |
| 963 | 968 | #define PCI_EXP_DPC_CAP 4 /* DPC Capability */ |
| 969 | +#define PCI_EXP_DPC_IRQ 0x1f /* DPC Interrupt Message Number */ | |
| 964 | 970 | #define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */ |
| 965 | 971 | #define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */ |
| 966 | 972 | #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */ |
| @@ -996,19 +1002,25 @@ · 29 unmodified lines | ||
| 996 | 1002 | #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ |
| 997 | 1003 | #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ |
| 998 | 1004 | |
| 999 | −/* L1 PM Substates */ | |
| 1000 | −#define PCI_L1SS_CAP 4 /* capability register */ | |
| 1001 | −#define PCI_L1SS_CAP_PCIPM_L1_2 1 /* PCI PM L1.2 Support */ | |
| 1002 | −#define PCI_L1SS_CAP_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ | |
| 1003 | −#define PCI_L1SS_CAP_ASPM_L1_2 4 /* ASPM L1.2 Support */ | |
| 1004 | −#define PCI_L1SS_CAP_ASPM_L1_1 8 /* ASPM L1.1 Support */ | |
| 1005 | −#define PCI_L1SS_CAP_L1_PM_SS 16 /* L1 PM Substates Support */ | |
| 1006 | −#define PCI_L1SS_CTL1 8 /* Control Register 1 */ | |
| 1007 | −#define PCI_L1SS_CTL1_PCIPM_L1_2 1 /* PCI PM L1.2 Enable */ | |
| 1008 | −#define PCI_L1SS_CTL1_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ | |
| 1009 | −#define PCI_L1SS_CTL1_ASPM_L1_2 4 /* ASPM L1.2 Support */ | |
| 1010 | −#define PCI_L1SS_CTL1_ASPM_L1_1 8 /* ASPM L1.1 Support */ | |
| 1011 | −#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000F | |
| 1012 | −#define PCI_L1SS_CTL2 0xC /* Control Register 2 */ | |
| 1005 | +/* ASPM L1 PM Substates */ | |
| 1006 | +#define PCI_L1SS_CAP 0x04 /* Capabilities Register */ | |
| 1007 | +#define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ | |
| 1008 | +#define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ | |
| 1009 | +#define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ | |
| 1010 | +#define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ | |
| 1011 | +#define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ | |
| 1012 | +#define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ | |
| 1013 | +#define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ | |
| 1014 | +#define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ | |
| 1015 | +#define PCI_L1SS_CTL1 0x08 /* Control 1 Register */ | |
| 1016 | +#define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ | |
| 1017 | +#define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ | |
| 1018 | +#define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ | |
| 1019 | +#define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ | |
| 1020 | +#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f | |
| 1021 | +#define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ | |
| 1022 | +#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ | |
| 1023 | +#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ | |
| 1024 | +#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ | |
| 1013 | 1025 | |
| 1014 | 1026 | #endif /* LINUX_PCI_REGS_H */ |