History

Merge tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver fixes from Greg Kroah-Hartman: "Here are some small char/misc driver fixes that resolve issues recently reported against the 3.9-rc kernels. All have been in linux-next for a while." * tag 'char-misc-3.9-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: VMCI: Fix process-to-process DRGAMs. mei: ME hardware reset needs to be synchronized mei: add mei_stop function to stop mei device extcon: max77693: Initialize register of MUIC device to bring up it without platform data extcon: max77693: Fix bug of wrong pointer when platform data is not used extcon: max8997: Check the pointer of platform data to protect null pointer error

Linus Torvalds committed 13 years ago

Commit 1b6a4db2 parents dfca53f 347e0898 files · +186 −100Browse files

Unified · Split

8 files
  1. drivers/extcon/extcon-max77693.c +80 −23
  2. drivers/extcon/extcon-max8997.c +34 −22
  3. drivers/misc/mei/hw-me.c +20 −9
  4. drivers/misc/mei/init.c +18 −0
  5. drivers/misc/mei/mei_dev.h +1 −0
  6. drivers/misc/mei/pci-me.c +7 −45
  7. drivers/misc/vmw_vmci/vmci_datagram.c +3 −1
  8. include/linux/mfd/max77693-private.h +23 −0
drivers/extcon/extcon-max77693.c+80−23
@@ -32,6 +32,38 @@ · 31 unmodified lines
3232 #define DEV_NAME "max77693-muic"
3333 #define DELAY_MS_DEFAULT 20000 /* unit: millisecond */
3434
35+/*
36+ * Default value of MAX77693 register to bring up MUIC device.
37+ * If user don't set some initial value for MUIC device through platform data,
38+ * extcon-max77693 driver use 'default_init_data' to bring up base operation
39+ * of MAX77693 MUIC device.
40+ */
41+struct max77693_reg_data default_init_data[] = {
42+ {
43+ /* STATUS2 - [3]ChgDetRun */
44+ .addr = MAX77693_MUIC_REG_STATUS2,
45+ .data = STATUS2_CHGDETRUN_MASK,
46+ }, {
47+ /* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */
48+ .addr = MAX77693_MUIC_REG_INTMASK1,
49+ .data = INTMASK1_ADC1K_MASK
50+ | INTMASK1_ADC_MASK,
51+ }, {
52+ /* INTMASK2 - Unmask [0]ChgTypM */
53+ .addr = MAX77693_MUIC_REG_INTMASK2,
54+ .data = INTMASK2_CHGTYP_MASK,
55+ }, {
56+ /* INTMASK3 - Mask all of interrupts */
57+ .addr = MAX77693_MUIC_REG_INTMASK3,
58+ .data = 0x0,
59+ }, {
60+ /* CDETCTRL2 */
61+ .addr = MAX77693_MUIC_REG_CDETCTRL2,
62+ .data = CDETCTRL2_VIDRMEN_MASK
63+ | CDETCTRL2_DXOVPEN_MASK,
64+ },
65+};
66+
3567 enum max77693_muic_adc_debounce_time {
3668 ADC_DEBOUNCE_TIME_5MS = 0,
3769 ADC_DEBOUNCE_TIME_10MS,
@@ -1045,8 +1077,9 @@ static int max77693_muic_probe(struct platform_device *pdev) · 1007 unmodified lines
10451077 {
10461078 struct max77693_dev *max77693 = dev_get_drvdata(pdev->dev.parent);
10471079 struct max77693_platform_data *pdata = dev_get_platdata(max77693->dev);
1048− struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
10491080 struct max77693_muic_info *info;
1081+ struct max77693_reg_data *init_data;
1082+ int num_init_data;
10501083 int delay_jiffies;
10511084 int ret;
10521085 int i;
@@ -1145,15 +1178,25 @@ static int max77693_muic_probe(struct platform_device *pdev) · 92 unmodified lines
11451178 goto err_irq;
11461179 }
11471180
1148− /* Initialize MUIC register by using platform data */
1149− for (i = 0 ; i < muic_pdata->num_init_data ; i++) {
1150− enum max77693_irq_source irq_src = MAX77693_IRQ_GROUP_NR;
1181+
1182+ /* Initialize MUIC register by using platform data or default data */
1183+ if (pdata->muic_data) {
1184+ init_data = pdata->muic_data->init_data;
1185+ num_init_data = pdata->muic_data->num_init_data;
1186+ } else {
1187+ init_data = default_init_data;
1188+ num_init_data = ARRAY_SIZE(default_init_data);
1189+ }
1190+
1191+ for (i = 0 ; i < num_init_data ; i++) {
1192+ enum max77693_irq_source irq_src
1193+ = MAX77693_IRQ_GROUP_NR;
11511194
11521195 max77693_write_reg(info->max77693->regmap_muic,
1153− muic_pdata->init_data[i].addr,
1154− muic_pdata->init_data[i].data);
1196+ init_data[i].addr,
1197+ init_data[i].data);
11551198
1156− switch (muic_pdata->init_data[i].addr) {
1199+ switch (init_data[i].addr) {
11571200 case MAX77693_MUIC_REG_INTMASK1:
11581201 irq_src = MUIC_INT1;
11591202 break;
@@ -1167,22 +1210,40 @@ static int max77693_muic_probe(struct platform_device *pdev) · 7 unmodified lines
11671210
11681211 if (irq_src < MAX77693_IRQ_GROUP_NR)
11691212 info->max77693->irq_masks_cur[irq_src]
1170− = muic_pdata->init_data[i].data;
1213+ = init_data[i].data;
11711214 }
11721215
1173− /*
1174− * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
1175− * h/w path of COMP2/COMN1 on CONTROL1 register.
1176− */
1177− if (muic_pdata->path_uart)
1178− info->path_uart = muic_pdata->path_uart;
1179− else
1180− info->path_uart = CONTROL1_SW_UART;
1216+ if (pdata->muic_data) {
1217+ struct max77693_muic_platform_data *muic_pdata = pdata->muic_data;
11811218
1182− if (muic_pdata->path_usb)
1183− info->path_usb = muic_pdata->path_usb;
1184− else
1219+ /*
1220+ * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
1221+ * h/w path of COMP2/COMN1 on CONTROL1 register.
1222+ */
1223+ if (muic_pdata->path_uart)
1224+ info->path_uart = muic_pdata->path_uart;
1225+ else
1226+ info->path_uart = CONTROL1_SW_UART;
1227+
1228+ if (muic_pdata->path_usb)
1229+ info->path_usb = muic_pdata->path_usb;
1230+ else
1231+ info->path_usb = CONTROL1_SW_USB;
1232+
1233+ /*
1234+ * Default delay time for detecting cable state
1235+ * after certain time.
1236+ */
1237+ if (muic_pdata->detcable_delay_ms)
1238+ delay_jiffies =
1239+ msecs_to_jiffies(muic_pdata->detcable_delay_ms);
1240+ else
1241+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
1242+ } else {
11851243 info->path_usb = CONTROL1_SW_USB;
1244+ info->path_uart = CONTROL1_SW_UART;
1245+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
1246+ }
11861247
11871248 /* Set initial path for UART */
11881249 max77693_muic_set_path(info, info->path_uart, true);
@@ -1208,10 +1269,6 @@ static int max77693_muic_probe(struct platform_device *pdev) · 19 unmodified lines
12081269 * driver should notify cable state to upper layer.
12091270 */
12101271 INIT_DELAYED_WORK(&info->wq_detcable, max77693_muic_detect_cable_wq);
1211− if (muic_pdata->detcable_delay_ms)
1212− delay_jiffies = msecs_to_jiffies(muic_pdata->detcable_delay_ms);
1213− else
1214− delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
12151272 schedule_delayed_work(&info->wq_detcable, delay_jiffies);
12161273
12171274 return ret;
drivers/extcon/extcon-max8997.c+34−22
@@ -712,29 +712,45 @@ static int max8997_muic_probe(struct platform_device *pdev) · 711 unmodified lines
712712 goto err_irq;
713713 }
714714
715− /* Initialize registers according to platform data */
716715 if (pdata->muic_pdata) {
717− struct max8997_muic_platform_data *mdata = info->muic_pdata;
718−
719− for (i = 0; i < mdata->num_init_data; i++) {
720− max8997_write_reg(info->muic, mdata->init_data[i].addr,
721− mdata->init_data[i].data);
716+ struct max8997_muic_platform_data *muic_pdata
717+ = pdata->muic_pdata;
718+
719+ /* Initialize registers according to platform data */
720+ for (i = 0; i < muic_pdata->num_init_data; i++) {
721+ max8997_write_reg(info->muic,
722+ muic_pdata->init_data[i].addr,
723+ muic_pdata->init_data[i].data);
722724 }
723− }
724725
725− /*
726− * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
727− * h/w path of COMP2/COMN1 on CONTROL1 register.
728− */
729− if (pdata->muic_pdata->path_uart)
730− info->path_uart = pdata->muic_pdata->path_uart;
731− else
732− info->path_uart = CONTROL1_SW_UART;
726+ /*
727+ * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
728+ * h/w path of COMP2/COMN1 on CONTROL1 register.
729+ */
730+ if (muic_pdata->path_uart)
731+ info->path_uart = muic_pdata->path_uart;
732+ else
733+ info->path_uart = CONTROL1_SW_UART;
733734
734− if (pdata->muic_pdata->path_usb)
735− info->path_usb = pdata->muic_pdata->path_usb;
736− else
735+ if (muic_pdata->path_usb)
736+ info->path_usb = muic_pdata->path_usb;
737+ else
738+ info->path_usb = CONTROL1_SW_USB;
739+
740+ /*
741+ * Default delay time for detecting cable state
742+ * after certain time.
743+ */
744+ if (muic_pdata->detcable_delay_ms)
745+ delay_jiffies =
746+ msecs_to_jiffies(muic_pdata->detcable_delay_ms);
747+ else
748+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
749+ } else {
750+ info->path_uart = CONTROL1_SW_UART;
737751 info->path_usb = CONTROL1_SW_USB;
752+ delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
753+ }
738754
739755 /* Set initial path for UART */
740756 max8997_muic_set_path(info, info->path_uart, true);
@@ -751,10 +767,6 @@ static int max8997_muic_probe(struct platform_device *pdev) · 10 unmodified lines
751767 * driver should notify cable state to upper layer.
752768 */
753769 INIT_DELAYED_WORK(&info->wq_detcable, max8997_muic_detect_cable_wq);
754− if (pdata->muic_pdata->detcable_delay_ms)
755− delay_jiffies = msecs_to_jiffies(pdata->muic_pdata->detcable_delay_ms);
756− else
757− delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
758770 schedule_delayed_work(&info->wq_detcable, delay_jiffies);
759771
760772 return 0;
drivers/misc/mei/hw-me.c+20−9
@@ -151,6 +151,20 @@ static void mei_me_intr_disable(struct mei_device *dev) · 150 unmodified lines
151151 mei_hcsr_set(hw, hcsr);
152152 }
153153
154+/**
155+ * mei_me_hw_reset_release - release device from the reset
156+ *
157+ * @dev: the device structure
158+ */
159+static void mei_me_hw_reset_release(struct mei_device *dev)
160+{
161+ struct mei_me_hw *hw = to_me_hw(dev);
162+ u32 hcsr = mei_hcsr_read(hw);
163+
164+ hcsr |= H_IG;
165+ hcsr &= ~H_RST;
166+ mei_hcsr_set(hw, hcsr);
167+}
154168 /**
155169 * mei_me_hw_reset - resets fw via mei csr register.
156170 *
@@ -169,18 +183,14 @@ static void mei_me_hw_reset(struct mei_device *dev, bool intr_enable) · 12 unmodified lines
169183 if (intr_enable)
170184 hcsr |= H_IE;
171185 else
172− hcsr &= ~H_IE;
173−
174− mei_hcsr_set(hw, hcsr);
175−
176− hcsr = mei_hcsr_read(hw) | H_IG;
177− hcsr &= ~H_RST;
186+ hcsr |= ~H_IE;
178187
179188 mei_hcsr_set(hw, hcsr);
180189
181− hcsr = mei_hcsr_read(hw);
190+ if (dev->dev_state == MEI_DEV_POWER_DOWN)
191+ mei_me_hw_reset_release(dev);
182192
183− dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr);
193+ dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", mei_hcsr_read(hw));
184194 }
185195
186196 /**
@@ -466,7 +476,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) · 279 unmodified lines
466476 mutex_unlock(&dev->device_lock);
467477 return IRQ_HANDLED;
468478 } else {
469− dev_dbg(&dev->pdev->dev, "FW not ready.\n");
479+ dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
480+ mei_me_hw_reset_release(dev);
470481 mutex_unlock(&dev->device_lock);
471482 return IRQ_HANDLED;
472483 }
drivers/misc/mei/init.c+18−0
@@ -183,6 +183,24 @@ void mei_reset(struct mei_device *dev, int interrupts_enabled) · 182 unmodified lines
183183 mei_cl_all_write_clear(dev);
184184 }
185185
186+void mei_stop(struct mei_device *dev)
187+{
188+ dev_dbg(&dev->pdev->dev, "stopping the device.\n");
189+
190+ mutex_lock(&dev->device_lock);
191+
192+ cancel_delayed_work(&dev->timer_work);
193+
194+ mei_wd_stop(dev);
195+
196+ dev->dev_state = MEI_DEV_POWER_DOWN;
197+ mei_reset(dev, 0);
198+
199+ mutex_unlock(&dev->device_lock);
200+
201+ flush_scheduled_work();
202+}
203+
186204
187205
188206
drivers/misc/mei/mei_dev.h+1−0
@@ -381,6 +381,7 @@ static inline unsigned long mei_secs_to_jiffies(unsigned long sec) · 380 unmodified lines
381381 void mei_device_init(struct mei_device *dev);
382382 void mei_reset(struct mei_device *dev, int interrupts);
383383 int mei_hw_init(struct mei_device *dev);
384+void mei_stop(struct mei_device *dev);
384385
385386 /*
386387 * MEI interrupt functions prototype
drivers/misc/mei/pci-me.c+7−45
@@ -247,44 +247,14 @@ static void mei_remove(struct pci_dev *pdev) · 246 unmodified lines
247247
248248 hw = to_me_hw(dev);
249249
250− mutex_lock(&dev->device_lock);
251−
252− cancel_delayed_work(&dev->timer_work);
253250
254− mei_wd_stop(dev);
251+ dev_err(&pdev->dev, "stop\n");
252+ mei_stop(dev);
255253
256254 mei_pdev = NULL;
257255
258− if (dev->iamthif_cl.state == MEI_FILE_CONNECTED) {
259− dev->iamthif_cl.state = MEI_FILE_DISCONNECTING;
260− mei_cl_disconnect(&dev->iamthif_cl);
261− }
262− if (dev->wd_cl.state == MEI_FILE_CONNECTED) {
263− dev->wd_cl.state = MEI_FILE_DISCONNECTING;
264− mei_cl_disconnect(&dev->wd_cl);
265− }
266−
267− /* Unregistering watchdog device */
268256 mei_watchdog_unregister(dev);
269257
270− /* remove entry if already in list */
271− dev_dbg(&pdev->dev, "list del iamthif and wd file list.\n");
272−
273− if (dev->open_handle_count > 0)
274− dev->open_handle_count--;
275− mei_cl_unlink(&dev->wd_cl);
276−
277− if (dev->open_handle_count > 0)
278− dev->open_handle_count--;
279− mei_cl_unlink(&dev->iamthif_cl);
280−
281− dev->iamthif_current_cb = NULL;
282− dev->me_clients_num = 0;
283−
284− mutex_unlock(&dev->device_lock);
285−
286− flush_scheduled_work();
287−
288258 /* disable interrupts */
289259 mei_disable_interrupts(dev);
290260
@@ -308,28 +278,20 @@ static int mei_pci_suspend(struct device *device) · 17 unmodified lines
308278 {
309279 struct pci_dev *pdev = to_pci_dev(device);
310280 struct mei_device *dev = pci_get_drvdata(pdev);
311− int err;
312281
313282 if (!dev)
314283 return -ENODEV;
315− mutex_lock(&dev->device_lock);
316284
317− cancel_delayed_work(&dev->timer_work);
285+ dev_err(&pdev->dev, "suspend\n");
318286
319− /* Stop watchdog if exists */
320− err = mei_wd_stop(dev);
321− /* Set new mei state */
322− if (dev->dev_state == MEI_DEV_ENABLED ||
323− dev->dev_state == MEI_DEV_RECOVERING_FROM_RESET) {
324− dev->dev_state = MEI_DEV_POWER_DOWN;
325− mei_reset(dev, 0);
326− }
327− mutex_unlock(&dev->device_lock);
287+ mei_stop(dev);
288+
289+ mei_disable_interrupts(dev);
328290
329291 free_irq(pdev->irq, dev);
330292 pci_disable_msi(pdev);
331293
332− return err;
294+ return 0;
333295 }
334296
335297 static int mei_pci_resume(struct device *device)
drivers/misc/vmw_vmci/vmci_datagram.c+3−1
@@ -42,9 +42,11 @@ struct datagram_entry { · 41 unmodified lines
4242
4343 struct delayed_datagram_info {
4444 struct datagram_entry *entry;
45− struct vmci_datagram msg;
4645 struct work_struct work;
4746 bool in_dg_host_queue;
47+ /* msg and msg_payload must be together. */
48+ struct vmci_datagram msg;
49+ u8 msg_payload[];
4850 };
4951
5052 /* Number of in-flight host->host datagrams */
include/linux/mfd/max77693-private.h+23−0
@@ -106,6 +106,29 @@ enum max77693_muic_reg { · 105 unmodified lines
106106 MAX77693_MUIC_REG_END,
107107 };
108108
109+/* MAX77693 INTMASK1~2 Register */
110+#define INTMASK1_ADC1K_SHIFT 3
111+#define INTMASK1_ADCERR_SHIFT 2
112+#define INTMASK1_ADCLOW_SHIFT 1
113+#define INTMASK1_ADC_SHIFT 0
114+#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
115+#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
116+#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
117+#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
118+
119+#define INTMASK2_VIDRM_SHIFT 5
120+#define INTMASK2_VBVOLT_SHIFT 4
121+#define INTMASK2_DXOVP_SHIFT 3
122+#define INTMASK2_DCDTMR_SHIFT 2
123+#define INTMASK2_CHGDETRUN_SHIFT 1
124+#define INTMASK2_CHGTYP_SHIFT 0
125+#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
126+#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
127+#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
128+#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
129+#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
130+#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
131+
109132 /* MAX77693 MUIC - STATUS1~3 Register */
110133 #define STATUS1_ADC_SHIFT (0)
111134 #define STATUS1_ADCLOW_SHIFT (5)