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Merge tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai: "At this time, it's an interesting mixture of changes for both old and new stuff. Majority of changes are about ASoC (lots of systematic changes for converting remove callbacks to void, and cleanups), while we got the fixes and the enhancements of very old PCI cards, too. Here are some highlights: ALSA/ASoC Core: - Continued effort of more ASoC core cleanups - Minor improvements for XRUN handling in indirect PCM helpers - Code refactoring of PCM core code ASoC: - Continued feature and simplification work on SOF, including addition of a no-DSP mode for bringup, HDA MLink and extensions to the IPC4 protocol - Hibernation support for CS35L45 - More DT binding conversions - Support for Cirrus Logic CS35L56, Freescale QMC, Maxim MAX98363, nVidia systems with MAX9809x and RT5631, Realtek RT712, Renesas R-Car Gen4, Rockchip RK3588 and TI TAS5733 ALSA: - Lots of works for legacy emu10k1 and ymfpci PCI drivers - PCM kselftest fixes and enhancements" * tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (586 commits) ALSA: emu10k1: use high-level I/O in set_filterQ() ALSA: emu10k1: use high-level I/O functions also during init ALSA: emu10k1: fix error handling in snd_audigy_i2c_volume_put() ALSA: emu10k1: don't stop DSP in _snd_emu10k1_{,audigy_}init_efx() ALSA: emu10k1: fix SNDRV_EMU10K1_IOCTL_SINGLE_STEP ALSA: emu10k1: skip Sound Blaster-specific hacks for E-MU cards ALSA: emu10k1: fixup DSP defines ALSA: emu10k1: pull in some register definitions from kX-project ALSA: emu10k1: remove some bogus defines ALSA: emu10k1: eliminate some unused defines ALSA: emu10k1: fix lineup of EMU_HANA_* defines ALSA: emu10k1: comment updates ALSA: emu10k1: fix snd_emu1010_fpga_read() input masking for rev2 cards ALSA: emu10k1: remove unused emu->pcm_playback_efx_substream field ALSA: emu10k1: remove unused `resume` parameter from snd_emu10k1_init() ALSA: emu10k1: minor optimizations ALSA: emu10k1: remove remaining cruft from snd_emu10k1_emu1010_init() ALSA: emu10k1: remove apparently pointless EMU_HANA_OPTION_CARDS reads ALSA: emu10k1: remove apparently pointless FPGA reads ALSA: emu10k1: stop doing weird things with HCFG in snd_emu10k1_emu1010_init() ...

Linus Torvalds committed 3 years ago

Commit 1c15ca42 parents 34b62f1 baa6584520 files · +19877 −6275Browse files

Showing the changes to include/uapi (5 of 520 files). Show all

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5 files
  1. include/uapi/sound/asound.h +10 −4
  2. include/uapi/sound/emu10k1.h +96 −54
  3. include/uapi/sound/sof/abi.h +2 −0
  4. include/uapi/sound/sof/header.h +19 −8
  5. include/uapi/sound/sof/tokens.h +13 −8
include/uapi/sound/asound.h+10−4
@@ -429,9 +429,14 @@ struct snd_pcm_sw_params { · 428 unmodified lines
429 snd_pcm_uframes_t avail_min; /* min avail frames for wakeup */429 snd_pcm_uframes_t avail_min; /* min avail frames for wakeup */
430 snd_pcm_uframes_t xfer_align; /* obsolete: xfer size need to be a multiple */430 snd_pcm_uframes_t xfer_align; /* obsolete: xfer size need to be a multiple */
431 snd_pcm_uframes_t start_threshold; /* min hw_avail frames for automatic start */431 snd_pcm_uframes_t start_threshold; /* min hw_avail frames for automatic start */
432 snd_pcm_uframes_t stop_threshold; /* min avail frames for automatic stop */432 /*
433 snd_pcm_uframes_t silence_threshold; /* min distance from noise for silence filling */433 * The following two thresholds alleviate playback buffer underruns; when
434 snd_pcm_uframes_t silence_size; /* silence block size */434 * hw_avail drops below the threshold, the respective action is triggered:
435 */
436 snd_pcm_uframes_t stop_threshold; /* - stop playback */
437 snd_pcm_uframes_t silence_threshold; /* - pre-fill buffer with silence */
438 snd_pcm_uframes_t silence_size; /* max size of silence pre-fill; when >= boundary,
439 * fill played area with silence immediately */
435 snd_pcm_uframes_t boundary; /* pointers wrap point */440 snd_pcm_uframes_t boundary; /* pointers wrap point */
436 unsigned int proto; /* protocol version */441 unsigned int proto; /* protocol version */
437 unsigned int tstamp_type; /* timestamp type (req. proto >= 2.0.12) */442 unsigned int tstamp_type; /* timestamp type (req. proto >= 2.0.12) */
@@ -570,7 +575,8 @@ struct __snd_pcm_mmap_status64 { · 132 unmodified lines
570struct __snd_pcm_mmap_control64 {575struct __snd_pcm_mmap_control64 {
571 __pad_before_uframe __pad1;576 __pad_before_uframe __pad1;
572 snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */577 snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */
573 __pad_before_uframe __pad2;578 __pad_before_uframe __pad2; // This should be __pad_after_uframe, but binary
579 // backwards compatibility constraints prevent a fix.
574 580
575 __pad_before_uframe __pad3;581 __pad_before_uframe __pad3;
576 snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */582 snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */
include/uapi/sound/emu10k1.h+96−54
@@ -15,9 +15,6 @@ · 14 unmodified lines
15 * ---- FX8010 ----15 * ---- FX8010 ----
16 */16 */
17 17
18#define EMU10K1_CARD_CREATIVE 0x00000000
19#define EMU10K1_CARD_EMUAPS 0x00000001
20
21#define EMU10K1_FX8010_PCM_COUNT 818#define EMU10K1_FX8010_PCM_COUNT 8
22 19
23/*20/*
@@ -46,6 +43,19 @@ · 22 unmodified lines
46#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */43#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
47#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */44#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
48 45
46#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
47#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
48#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
49#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
50#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
51
52/* Audigy Soundcards have a different instruction format */
53#define A_LOWORD_OPX_MASK 0x007ff000
54#define A_LOWORD_OPY_MASK 0x000007ff
55#define A_HIWORD_OPCODE_MASK 0x0f000000
56#define A_HIWORD_RESULT_MASK 0x007ff000
57#define A_HIWORD_OPA_MASK 0x000007ff
58
49/* GPRs */59/* GPRs */
50#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */60#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
51#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */61#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
@@ -53,6 +63,16 @@ · 1 unmodified line
53#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */63#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
54 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */64 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
55 65
66#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
67#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
68#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
69#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
70#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
71#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" */
72#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_01 - _0F" */
73#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x1f "EMU32_IN_00 - _1F" - Only when .device = 0x0008 */
74#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x1f "EMU32_OUT_00 - _1F" - Only when .device = 0x0008 */
75
56#define C_00000000 0x4076#define C_00000000 0x40
57#define C_00000001 0x4177#define C_00000001 0x41
58#define C_00000002 0x4278#define C_00000002 0x42
@@ -81,12 +101,66 @@ · 22 unmodified lines
81#define GPR_NOISE1 0x59 /* noise source */101#define GPR_NOISE1 0x59 /* noise source */
82#define GPR_IRQ 0x5a /* IRQ register */102#define GPR_IRQ 0x5a /* IRQ register */
83#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */103#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
104
105/* Audigy constants */
106#define A_C_00000000 0xc0
107#define A_C_00000001 0xc1
108#define A_C_00000002 0xc2
109#define A_C_00000003 0xc3
110#define A_C_00000004 0xc4
111#define A_C_00000008 0xc5
112#define A_C_00000010 0xc6
113#define A_C_00000020 0xc7
114#define A_C_00000100 0xc8
115#define A_C_00010000 0xc9
116#define A_C_00000800 0xca
117#define A_C_10000000 0xcb
118#define A_C_20000000 0xcc
119#define A_C_40000000 0xcd
120#define A_C_80000000 0xce
121#define A_C_7fffffff 0xcf
122#define A_C_ffffffff 0xd0
123#define A_C_fffffffe 0xd1
124#define A_C_c0000000 0xd2
125#define A_C_4f1bbcdc 0xd3
126#define A_C_5a7ef9db 0xd4
127#define A_C_00100000 0xd5
128#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
129#define A_GPR_COND 0xd7 /* CCR, condition register */
130#define A_GPR_NOISE0 0xd8 /* noise source */
131#define A_GPR_NOISE1 0xd9 /* noise source */
132#define A_GPR_IRQ 0xda /* IRQ register */
133#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
134#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
135
136/* Each FX general purpose register is 32 bits in length, all bits are used */
137#define FXGPREGBASE 0x100 /* FX general purpose registers base */
138#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
139
140#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
141#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
142
143/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
144/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
145/* locations are for external TRAM. */
146#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
147#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
148
149/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
150#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
151#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
152#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
153#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
154#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
155#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
156
84#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */157#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
85#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */158#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
86#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */159#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
87#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */160#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
88#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */161#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
89 162
163#define A_GPR(x) (A_FXGPREGBASE + (x))
90#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */164#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
91#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */165#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
92#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */166#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
@@ -94,17 +168,6 @@ · 1 unmodified line
94#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */168#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
95#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */169#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
96 170
97#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
98#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
99#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
100#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
101#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
102#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
103#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
104#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
105#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
106#define A_GPR(x) (A_FXGPREGBASE + (x))
107
108/* cc_reg constants */171/* cc_reg constants */
109#define CC_REG_NORMALIZED C_00000001172#define CC_REG_NORMALIZED C_00000001
110#define CC_REG_BORROW C_00000002173#define CC_REG_BORROW C_00000002
@@ -113,7 +176,17 @@ · 2 unmodified lines
113#define CC_REG_SATURATE C_00000010176#define CC_REG_SATURATE C_00000010
114#define CC_REG_NONZERO C_00000100177#define CC_REG_NONZERO C_00000100
115 178
179#define A_CC_REG_NORMALIZED A_C_00000001
180#define A_CC_REG_BORROW A_C_00000002
181#define A_CC_REG_MINUS A_C_00000004
182#define A_CC_REG_ZERO A_C_00000008
183#define A_CC_REG_SATURATE A_C_00000010
184#define A_CC_REG_NONZERO A_C_00000100
185
116/* FX buses */186/* FX buses */
187// These are arbitrary mappings; our DSP code simply expects
188// the config files to route the channels this way.
189// The numbers are documented in {audigy,sb-live}-mixer.rst.
117#define FXBUS_PCM_LEFT 0x00190#define FXBUS_PCM_LEFT 0x00
118#define FXBUS_PCM_RIGHT 0x01191#define FXBUS_PCM_RIGHT 0x01
119#define FXBUS_PCM_LEFT_REAR 0x02192#define FXBUS_PCM_LEFT_REAR 0x02
@@ -203,38 +276,7 @@ · 83 unmodified lines
203#define A_EXTOUT_ADC_CAP_R 0x17 /* right */276#define A_EXTOUT_ADC_CAP_R 0x17 /* right */
204#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */277#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
205 278
206/* Audigy constants */279/* Definitions for debug register. Note that these are for emu10k1 ONLY. */
207#define A_C_00000000 0xc0
208#define A_C_00000001 0xc1
209#define A_C_00000002 0xc2
210#define A_C_00000003 0xc3
211#define A_C_00000004 0xc4
212#define A_C_00000008 0xc5
213#define A_C_00000010 0xc6
214#define A_C_00000020 0xc7
215#define A_C_00000100 0xc8
216#define A_C_00010000 0xc9
217#define A_C_00000800 0xca
218#define A_C_10000000 0xcb
219#define A_C_20000000 0xcc
220#define A_C_40000000 0xcd
221#define A_C_80000000 0xce
222#define A_C_7fffffff 0xcf
223#define A_C_ffffffff 0xd0
224#define A_C_fffffffe 0xd1
225#define A_C_c0000000 0xd2
226#define A_C_4f1bbcdc 0xd3
227#define A_C_5a7ef9db 0xd4
228#define A_C_00100000 0xd5
229#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
230#define A_GPR_COND 0xd7 /* CCR, condition register */
231#define A_GPR_NOISE0 0xd8 /* noise source */
232#define A_GPR_NOISE1 0xd9 /* noise source */
233#define A_GPR_IRQ 0xda /* IRQ register */
234#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
235#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
236
237/* definitions for debug register */
238#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */280#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
239#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */281#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
240#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */282#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
@@ -243,14 +285,14 @@ · 2 unmodified lines
243#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */285#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
244#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */286#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
245 287
246/* tank memory address line */288/* Definitions for emu10k2 debug register. */
247#ifndef __KERNEL__289#define A_DBG_ZC 0x40000000 /* zero tram counter */
248#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */290#define A_DBG_SATURATION_OCCURED 0x20000000
249#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */291#define A_DBG_SATURATION_ADDR 0x0ffc0000
250#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */292#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
251#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */293#define A_DBG_STEP 0x00010000
252#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */294#define A_DBG_CONDITION_CODE 0x0000f800
253#endif295#define A_DBG_STEP_ADDR 0x000003ff
254 296
255struct snd_emu10k1_fx8010_info {297struct snd_emu10k1_fx8010_info {
256 unsigned int internal_tram_size; /* in samples */298 unsigned int internal_tram_size; /* in samples */
include/uapi/sound/sof/abi.h+2−0
@@ -60,5 +60,7 @@ · 59 unmodified lines
60 60
61/* SOF ABI magic number "SOF\0". */61/* SOF ABI magic number "SOF\0". */
62#define SOF_ABI_MAGIC 0x00464F5362#define SOF_ABI_MAGIC 0x00464F53
63/* SOF IPC4 ABI magic number "SOF4". */
64#define SOF_IPC4_ABI_MAGIC 0x34464F53
63 65
64#endif66#endif
include/uapi/sound/sof/header.h+19−8
@@ -11,19 +11,30 @@ · 10 unmodified lines
11 11
12#include <linux/types.h>12#include <linux/types.h>
13 13
14/*14/**
15 * Header for all non IPC ABI data.15 * struct sof_abi_hdr - Header for all non IPC ABI data.
16 * @magic: Magic number for validation
17 * for IPC3 data: 0x00464F53 ('S', 'O', 'F', '\0')
18 * for IPC4 data: 0x34464F53 ('S', 'O', 'F', '4')
19 * @type: module specific parameter
20 * for IPC3: Component specific type
21 * for IPC4: parameter ID (param_id) of the data
22 * @size: The size in bytes of the data, excluding this struct
23 * @abi: SOF ABI version. The version is valid in scope of the 'magic', IPC3 and
24 * IPC4 ABI version numbers have no relationship.
25 * @reserved: Reserved for future use
26 * @data: Component data - opaque to core
16 *27 *
17 * Identifies data type, size and ABI.28 * Identifies data type, size and ABI.
18 * Used by any bespoke component data structures or binary blobs.29 * Used by any bespoke component data structures or binary blobs.
19 */30 */
20struct sof_abi_hdr {31struct sof_abi_hdr {
21 __u32 magic; /**< 'S', 'O', 'F', '\0' */32 __u32 magic;
22 __u32 type; /**< component specific type */33 __u32 type;
23 __u32 size; /**< size in bytes of data excl. this struct */34 __u32 size;
24 __u32 abi; /**< SOF ABI version */35 __u32 abi;
25 __u32 reserved[4]; /**< reserved for future use */36 __u32 reserved[4];
26 __u32 data[]; /**< Component data - opaque to core */37 __u32 data[];
27} __packed;38} __packed;
28 39
29#define SOF_MANIFEST_DATA_TYPE_NHLT 140#define SOF_MANIFEST_DATA_TYPE_NHLT 1
include/uapi/sound/sof/tokens.h+13−8
@@ -54,6 +54,7 @@ · 53 unmodified lines
54#define SOF_TKN_SCHED_DYNAMIC_PIPELINE 20654#define SOF_TKN_SCHED_DYNAMIC_PIPELINE 206
55#define SOF_TKN_SCHED_LP_MODE 20755#define SOF_TKN_SCHED_LP_MODE 207
56#define SOF_TKN_SCHED_MEM_USAGE 20856#define SOF_TKN_SCHED_MEM_USAGE 208
57#define SOF_TKN_SCHED_USE_CHAIN_DMA 209
57 58
58/* volume */59/* volume */
59#define SOF_TKN_VOLUME_RAMP_STEP_TYPE 25060#define SOF_TKN_VOLUME_RAMP_STEP_TYPE 250
@@ -88,14 +89,16 @@ · 28 unmodified lines
88#define SOF_TKN_COMP_CPC 40689#define SOF_TKN_COMP_CPC 406
89#define SOF_TKN_COMP_IS_PAGES 40990#define SOF_TKN_COMP_IS_PAGES 409
90#define SOF_TKN_COMP_NUM_AUDIO_FORMATS 41091#define SOF_TKN_COMP_NUM_AUDIO_FORMATS 410
91#define SOF_TKN_COMP_NUM_SINK_PINS 41192#define SOF_TKN_COMP_NUM_INPUT_PINS 411
92#define SOF_TKN_COMP_NUM_SOURCE_PINS 41293#define SOF_TKN_COMP_NUM_OUTPUT_PINS 412
93/*94/*
94 * The token for sink/source pin binding, it specifies the widget95 * The token for input/output pin binding, it specifies the widget
95 * name that the sink/source pin is connected from/to.96 * name that the input/output pin is connected from/to.
96 */97 */
97#define SOF_TKN_COMP_SINK_PIN_BINDING_WNAME 41398#define SOF_TKN_COMP_INPUT_PIN_BINDING_WNAME 413
98#define SOF_TKN_COMP_SRC_PIN_BINDING_WNAME 41499#define SOF_TKN_COMP_OUTPUT_PIN_BINDING_WNAME 414
100#define SOF_TKN_COMP_NUM_INPUT_AUDIO_FORMATS 415
101#define SOF_TKN_COMP_NUM_OUTPUT_AUDIO_FORMATS 416
99 102
100 103
101/* SSP */104/* SSP */
@@ -173,17 +176,18 @@ · 71 unmodified lines
173/* CAVS AUDIO FORMAT */176/* CAVS AUDIO FORMAT */
174#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_RATE 1900177#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_RATE 1900
175#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_BIT_DEPTH 1901178#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_BIT_DEPTH 1901
176#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_VALID_BIT 1902179#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_VALID_BIT_DEPTH 1902
177#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_CHANNELS 1903180#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_CHANNELS 1903
178#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_CH_MAP 1904181#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_CH_MAP 1904
179#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_CH_CFG 1905182#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_CH_CFG 1905
180#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_INTERLEAVING_STYLE 1906183#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_INTERLEAVING_STYLE 1906
181#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_FMT_CFG 1907184#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_FMT_CFG 1907
182#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_SAMPLE_TYPE 1908185#define SOF_TKN_CAVS_AUDIO_FORMAT_IN_SAMPLE_TYPE 1908
186#define SOF_TKN_CAVS_AUDIO_FORMAT_PIN_INDEX 1909
183/* intentional token numbering discontinuity, reserved for future use */187/* intentional token numbering discontinuity, reserved for future use */
184#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_RATE 1930188#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_RATE 1930
185#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_BIT_DEPTH 1931189#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_BIT_DEPTH 1931
186#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_VALID_BIT 1932190#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_VALID_BIT_DEPTH 1932
187#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CHANNELS 1933191#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CHANNELS 1933
188#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CH_MAP 1934192#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CH_MAP 1934
189#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CH_CFG 1935193#define SOF_TKN_CAVS_AUDIO_FORMAT_OUT_CH_CFG 1935
@@ -197,6 +201,7 @@ · 7 unmodified lines
197 201
198/* COPIER */202/* COPIER */
199#define SOF_TKN_INTEL_COPIER_NODE_TYPE 1980203#define SOF_TKN_INTEL_COPIER_NODE_TYPE 1980
204#define SOF_TKN_INTEL_COPIER_DEEP_BUFFER_DMA_MS 1981
200 205
201/* ACP I2S */206/* ACP I2S */
202#define SOF_TKN_AMD_ACPI2S_RATE 1700207#define SOF_TKN_AMD_ACPI2S_RATE 1700