Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.4 Highlights - new SoCs (G12B family): S922X, A311D - new SoCs (SM1 family): S905X3 - new board: SEI Robotics SEI610 (SM1/S905X3) - new board: Khadas VIM3 (G12B/A311D) - DVFS/CPUfreq support on G12[AB] family * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits) arm64: dts: add support for SM1 based SEI Robotics SEI610 dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings dt-bindings: arm: amlogic: add SM1 bindings arm64: dts: meson-g12b-odroid-n2: enable DVFS arm64: dts: meson-g12b-khadas-vim3: add initial device-tree dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml arm64: dts: amlogic: g12 CPU timers stop in suspend arm64: dts: meson-g12b: support a311d and s922x cpu operating points dt-bindings: arm: amlogic: add support for the Khadas VIM3 dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC arm64: dts: meson: add video decoder entries arm64: dts: meson-gx: add video decoder entry dt-bindings: media: amlogic,vdec: add default compatible arm64: dts: meson: add ethernet fifo sizes arm64: dts: meson-g12b: add cpus OPP tables arm64: dts: meson-g12a: enable DVFS on G12A boards arm64: dts: meson-g12a: add cpus OPP table arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi ...

Arnd Bergmann committed 7 years ago

Commit 1c92b322 parents 8ad83e3 e9a12e145 files · +6660 −3672Browse files

Unified · Split

45 files

Documentation/devicetree/bindings/arm/amlogic.yaml +17 −3
Documentation/devicetree/bindings/media/amlogic,vdec.txt +3 −2
arch/arm64/boot/dts/amlogic/Makefile +3 −0
arch/arm64/boot/dts/amlogic/meson-axg.dtsi +2 −0
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +2420 −0
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +61 −0
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +54 −0
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +52 −0
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +40 −2377
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts +15 −0
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +149 −0
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +544 −0
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +98 −1
arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts +15 −0
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +124 −0
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +27 −3
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +16 −0
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +11 −0
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +11 −0
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +4 −0
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +300 −0
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +68 −0
drivers/clk/clk.c +6 −0
drivers/clk/meson/Kconfig +5 −6
drivers/clk/meson/Makefile +1 −1
drivers/clk/meson/axg-aoclk.c +37 −26
drivers/clk/meson/axg-audio.c +120 −141
drivers/clk/meson/axg.c +147 −60
drivers/clk/meson/clk-cpu-dyndiv.c +73 −0
drivers/clk/meson/clk-cpu-dyndiv.h +20 −0
drivers/clk/meson/clk-input.c +0 −49
drivers/clk/meson/clk-input.h +0 −19
drivers/clk/meson/clk-regmap.h +6 −6
drivers/clk/meson/g12a-aoclk.c +50 −31
drivers/clk/meson/g12a.c +1179 −447
drivers/clk/meson/g12a.h +0 −1
drivers/clk/meson/gxbb-aoclk.c +27 −28
drivers/clk/meson/gxbb.c +454 −203
drivers/clk/meson/meson-aoclk.c +0 −37
drivers/clk/meson/meson-aoclk.h +0 −8
drivers/clk/meson/meson-eeclk.c +0 −10
drivers/clk/meson/meson-eeclk.h +0 −2
drivers/clk/meson/meson8b.c +499 −211
include/dt-bindings/clock/g12a-clkc.h +1 −0
include/linux/clk-provider.h +1 −0

Documentation/devicetree/bindings/arm/amlogic.yaml+17−3

       - description: Boards with the Amlogic Meson GXL S905X SoC
         items:
           - enum:
-              - amediatech,x96-max
               - amlogic,p212
               - hwacom,amazetv
               - khadas,vim
               - libretech,cc
               - nexbox,a95x
-              - seirobotics,sei510
           - const: amlogic,s905x
           - const: amlogic,meson-gxl
           - const: amlogic,a113d
           - const: amlogic,meson-axg
-      - description: Boards with the Amlogic Meson G12A S905D2 SoC
+      - description: Boards with the Amlogic Meson G12A S905D2/X2/Y2 SoC
         items:
           - enum:
+              - amediatech,x96-max
               - amlogic,u200
+              - seirobotics,sei510
           - const: amlogic,g12a
+      - description: Boards with the Amlogic Meson G12B A311D SoC
+        items:
+          - enum:
+              - khadas,vim3
+          - const: amlogic,a311d
+          - const: amlogic,g12b
       - description: Boards with the Amlogic Meson G12B S922X SoC
         items:
           - enum:
               - hardkernel,odroid-n2
+              - khadas,vim3
+          - const: amlogic,s922x
           - const: amlogic,g12b
+      - description: Boards with the Amlogic Meson SM1 S905X3 SoC
+        items:
+          - enum:
+              - seirobotics,sei610
+          - const: amlogic,sm1
 ...

Documentation/devicetree/bindings/media/amlogic,vdec.txt+3−2

 	- GXBB (S905) : "amlogic,gxbb-vdec"
 	- GXL (S905X, S905D) : "amlogic,gxl-vdec"
 	- GXM (S912) : "amlogic,gxm-vdec"
+	followed by the common "amlogic,gx-vdec"
 - reg: base address and size of he following memory-mapped regions :
 	- dos
 	- esparser
 Example:
-vdec: video-decoder@c8820000 {
+vdec: video-codec@c8820000 {
-	compatible = "amlogic,gxbb-vdec";
+	compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
 	reg = <0x0 0xc8820000 0x0 0x10000>,
 	      <0x0 0xc110a580 0x0 0xe4>;
 	reg-names = "dos", "esparser";

arch/arm64/boot/dts/amlogic/Makefile+3−0

 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb

arch/arm64/boot/dts/amlogic/meson-axg.dtsi+2−0

@@ -182,6 +182,8 @@ · 181 unmodified lines
182	<&clkc CLKID_FCLK_DIV2>,	182	<&clkc CLKID_FCLK_DIV2>,
183	<&clkc CLKID_MPLL2>;	183	<&clkc CLKID_MPLL2>;
184	clock-names = "stmmaceth", "clkin0", "clkin1";	184	clock-names = "stmmaceth", "clkin0", "clkin1";
		185	rx-fifo-depth = <4096>;
		186	tx-fifo-depth = <2048>;
185	status = "disabled";	187	status = "disabled";
186	};	188	};
187		189

arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi+2420−0

@@ -0,0 +1,2420 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
	4	*/
	5
	6	#include <dt-bindings/phy/phy.h>
	7	#include <dt-bindings/gpio/gpio.h>
	8	#include <dt-bindings/clock/axg-audio-clkc.h>
	9	#include <dt-bindings/clock/g12a-clkc.h>
	10	#include <dt-bindings/clock/g12a-aoclkc.h>
	11	#include <dt-bindings/interrupt-controller/irq.h>
	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
	13	#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
	14	#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18	#address-cells = <2>;
	19	#size-cells = <2>;
	20
	21	tdmif_a: audio-controller-0 {
	22	compatible = "amlogic,axg-tdm-iface";
	23	#sound-dai-cells = <0>;
	24	sound-name-prefix = "TDM_A";
	25	clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
	26	<&clkc_audio AUD_CLKID_MST_A_SCLK>,
	27	<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
	28	clock-names = "mclk", "sclk", "lrclk";
	29	status = "disabled";
	30	};
	31
	32	tdmif_b: audio-controller-1 {
	33	compatible = "amlogic,axg-tdm-iface";
	34	#sound-dai-cells = <0>;
	35	sound-name-prefix = "TDM_B";
	36	clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
	37	<&clkc_audio AUD_CLKID_MST_B_SCLK>,
	38	<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
	39	clock-names = "mclk", "sclk", "lrclk";
	40	status = "disabled";
	41	};
	42
	43	tdmif_c: audio-controller-2 {
	44	compatible = "amlogic,axg-tdm-iface";
	45	#sound-dai-cells = <0>;
	46	sound-name-prefix = "TDM_C";
	47	clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
	48	<&clkc_audio AUD_CLKID_MST_C_SCLK>,
	49	<&clkc_audio AUD_CLKID_MST_C_LRCLK>;
	50	clock-names = "mclk", "sclk", "lrclk";
	51	status = "disabled";
	52	};
	53
	54	efuse: efuse {
	55	compatible = "amlogic,meson-gxbb-efuse";
	56	clocks = <&clkc CLKID_EFUSE>;
	57	#address-cells = <1>;
	58	#size-cells = <1>;
	59	read-only;
	60	};
	61
	62	psci {
	63	compatible = "arm,psci-1.0";
	64	method = "smc";
	65	};
	66
	67	reserved-memory {
	68	#address-cells = <2>;
	69	#size-cells = <2>;
	70	ranges;
	71
	72	/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
	73	secmon_reserved: secmon@5000000 {
	74	reg = <0x0 0x05000000 0x0 0x300000>;
	75	no-map;
	76	};
	77
	78	linux,cma {
	79	compatible = "shared-dma-pool";
	80	reusable;
	81	size = <0x0 0x10000000>;
	82	alignment = <0x0 0x400000>;
	83	linux,cma-default;
	84	};
	85	};
	86
	87	sm: secure-monitor {
	88	compatible = "amlogic,meson-gxbb-sm";
	89	};
	90
	91	soc {
	92	compatible = "simple-bus";
	93	#address-cells = <2>;
	94	#size-cells = <2>;
	95	ranges;
	96
	97	ethmac: ethernet@ff3f0000 {
	98	compatible = "amlogic,meson-axg-dwmac",
	99	"snps,dwmac-3.70a",
	100	"snps,dwmac";
	101	reg = <0x0 0xff3f0000 0x0 0x10000
	102	0x0 0xff634540 0x0 0x8>;
	103	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	104	interrupt-names = "macirq";
	105	clocks = <&clkc CLKID_ETH>,
	106	<&clkc CLKID_FCLK_DIV2>,
	107	<&clkc CLKID_MPLL2>;
	108	clock-names = "stmmaceth", "clkin0", "clkin1";
	109	rx-fifo-depth = <4096>;
	110	tx-fifo-depth = <2048>;
	111	status = "disabled";
	112
	113	mdio0: mdio {
	114	#address-cells = <1>;
	115	#size-cells = <0>;
	116	compatible = "snps,dwmac-mdio";
	117	};
	118	};
	119
	120	apb: bus@ff600000 {
	121	compatible = "simple-bus";
	122	reg = <0x0 0xff600000 0x0 0x200000>;
	123	#address-cells = <2>;
	124	#size-cells = <2>;
	125	ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
	126
	127	hdmi_tx: hdmi-tx@0 {
	128	compatible = "amlogic,meson-g12a-dw-hdmi";
	129	reg = <0x0 0x0 0x0 0x10000>;
	130	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
	131	resets = <&reset RESET_HDMITX_CAPB3>,
	132	<&reset RESET_HDMITX_PHY>,
	133	<&reset RESET_HDMITX>;
	134	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	135	clocks = <&clkc CLKID_HDMI>,
	136	<&clkc CLKID_HTX_PCLK>,
	137	<&clkc CLKID_VPU_INTR>;
	138	clock-names = "isfr", "iahb", "venci";
	139	#address-cells = <1>;
	140	#size-cells = <0>;
	141	#sound-dai-cells = <0>;
	142	status = "disabled";
	143
	144	/* VPU VENC Input */
	145	hdmi_tx_venc_port: port@0 {
	146	reg = <0>;
	147
	148	hdmi_tx_in: endpoint {
	149	remote-endpoint = <&hdmi_tx_out>;
	150	};
	151	};
	152
	153	/* TMDS Output */
	154	hdmi_tx_tmds_port: port@1 {
	155	reg = <1>;
	156	};
	157	};
	158
	159	apb_efuse: bus@30000 {
	160	compatible = "simple-bus";
	161	reg = <0x0 0x30000 0x0 0x2000>;
	162	#address-cells = <2>;
	163	#size-cells = <2>;
	164	ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
	165
	166	hwrng: rng@218 {
	167	compatible = "amlogic,meson-rng";
	168	reg = <0x0 0x218 0x0 0x4>;
	169	};
	170	};
	171
	172	periphs: bus@34400 {
	173	compatible = "simple-bus";
	174	reg = <0x0 0x34400 0x0 0x400>;
	175	#address-cells = <2>;
	176	#size-cells = <2>;
	177	ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
	178
	179	periphs_pinctrl: pinctrl@40 {
	180	compatible = "amlogic,meson-g12a-periphs-pinctrl";
	181	#address-cells = <2>;
	182	#size-cells = <2>;
	183	ranges;
	184
	185	gpio: bank@40 {
	186	reg = <0x0 0x40 0x0 0x4c>,
	187	<0x0 0xe8 0x0 0x18>,
	188	<0x0 0x120 0x0 0x18>,
	189	<0x0 0x2c0 0x0 0x40>,
	190	<0x0 0x340 0x0 0x1c>;
	191	reg-names = "gpio",
	192	"pull",
	193	"pull-enable",
	194	"mux",
	195	"ds";
	196	gpio-controller;
	197	#gpio-cells = <2>;
	198	gpio-ranges = <&periphs_pinctrl 0 0 86>;
	199	};
	200
	201	cec_ao_a_h_pins: cec_ao_a_h {
	202	mux {
	203	groups = "cec_ao_a_h";
	204	function = "cec_ao_a_h";
	205	bias-disable;
	206	};
	207	};
	208
	209	cec_ao_b_h_pins: cec_ao_b_h {
	210	mux {
	211	groups = "cec_ao_b_h";
	212	function = "cec_ao_b_h";
	213	bias-disable;
	214	};
	215	};
	216
	217	emmc_pins: emmc {
	218	mux-0 {
	219	groups = "emmc_nand_d0",
	220	"emmc_nand_d1",
	221	"emmc_nand_d2",
	222	"emmc_nand_d3",
	223	"emmc_nand_d4",
	224	"emmc_nand_d5",
	225	"emmc_nand_d6",
	226	"emmc_nand_d7",
	227	"emmc_cmd";
	228	function = "emmc";
	229	bias-pull-up;
	230	drive-strength-microamp = <4000>;
	231	};
	232
	233	mux-1 {
	234	groups = "emmc_clk";
	235	function = "emmc";
	236	bias-disable;
	237	drive-strength-microamp = <4000>;
	238	};
	239	};
	240
	241	emmc_ds_pins: emmc-ds {
	242	mux {
	243	groups = "emmc_nand_ds";
	244	function = "emmc";
	245	bias-pull-down;
	246	drive-strength-microamp = <4000>;
	247	};
	248	};
	249
	250	emmc_clk_gate_pins: emmc_clk_gate {
	251	mux {
	252	groups = "BOOT_8";
	253	function = "gpio_periphs";
	254	bias-pull-down;
	255	drive-strength-microamp = <4000>;
	256	};
	257	};
	258
	259	hdmitx_ddc_pins: hdmitx_ddc {
	260	mux {
	261	groups = "hdmitx_sda",
	262	"hdmitx_sck";
	263	function = "hdmitx";
	264	bias-disable;
	265	drive-strength-microamp = <4000>;
	266	};
	267	};
	268
	269	hdmitx_hpd_pins: hdmitx_hpd {
	270	mux {
	271	groups = "hdmitx_hpd_in";
	272	function = "hdmitx";
	273	bias-disable;
	274	};
	275	};
	276
	277
	278	i2c0_sda_c_pins: i2c0-sda-c {
	279	mux {
	280	groups = "i2c0_sda_c";
	281	function = "i2c0";
	282	bias-disable;
	283	drive-strength-microamp = <3000>;
	284
	285	};
	286	};
	287
	288	i2c0_sck_c_pins: i2c0-sck-c {
	289	mux {
	290	groups = "i2c0_sck_c";
	291	function = "i2c0";
	292	bias-disable;
	293	drive-strength-microamp = <3000>;
	294	};
	295	};
	296
	297	i2c0_sda_z0_pins: i2c0-sda-z0 {
	298	mux {
	299	groups = "i2c0_sda_z0";
	300	function = "i2c0";
	301	bias-disable;
	302	drive-strength-microamp = <3000>;
	303	};
	304	};
	305
	306	i2c0_sck_z1_pins: i2c0-sck-z1 {
	307	mux {
	308	groups = "i2c0_sck_z1";
	309	function = "i2c0";
	310	bias-disable;
	311	drive-strength-microamp = <3000>;
	312	};
	313	};
	314
	315	i2c0_sda_z7_pins: i2c0-sda-z7 {
	316	mux {
	317	groups = "i2c0_sda_z7";
	318	function = "i2c0";
	319	bias-disable;
	320	drive-strength-microamp = <3000>;
	321	};
	322	};
	323
	324	i2c0_sda_z8_pins: i2c0-sda-z8 {
	325	mux {
	326	groups = "i2c0_sda_z8";
	327	function = "i2c0";
	328	bias-disable;
	329	drive-strength-microamp = <3000>;
	330	};
	331	};
	332
	333	i2c1_sda_x_pins: i2c1-sda-x {
	334	mux {
	335	groups = "i2c1_sda_x";
	336	function = "i2c1";
	337	bias-disable;
	338	drive-strength-microamp = <3000>;
	339	};
	340	};
	341
	342	i2c1_sck_x_pins: i2c1-sck-x {
	343	mux {
	344	groups = "i2c1_sck_x";
	345	function = "i2c1";
	346	bias-disable;
	347	drive-strength-microamp = <3000>;
	348	};
	349	};
	350
	351	i2c1_sda_h2_pins: i2c1-sda-h2 {
	352	mux {
	353	groups = "i2c1_sda_h2";
	354	function = "i2c1";
	355	bias-disable;
	356	drive-strength-microamp = <3000>;
	357	};
	358	};
	359
	360	i2c1_sck_h3_pins: i2c1-sck-h3 {
	361	mux {
	362	groups = "i2c1_sck_h3";
	363	function = "i2c1";
	364	bias-disable;
	365	drive-strength-microamp = <3000>;
	366	};
	367	};
	368
	369	i2c1_sda_h6_pins: i2c1-sda-h6 {
	370	mux {
	371	groups = "i2c1_sda_h6";
	372	function = "i2c1";
	373	bias-disable;
	374	drive-strength-microamp = <3000>;
	375	};
	376	};
	377
	378	i2c1_sck_h7_pins: i2c1-sck-h7 {
	379	mux {
	380	groups = "i2c1_sck_h7";
	381	function = "i2c1";
	382	bias-disable;
	383	drive-strength-microamp = <3000>;
	384	};
	385	};
	386
	387	i2c2_sda_x_pins: i2c2-sda-x {
	388	mux {
	389	groups = "i2c2_sda_x";
	390	function = "i2c2";
	391	bias-disable;
	392	drive-strength-microamp = <3000>;
	393	};
	394	};
	395
	396	i2c2_sck_x_pins: i2c2-sck-x {
	397	mux {
	398	groups = "i2c2_sck_x";
	399	function = "i2c2";
	400	bias-disable;
	401	drive-strength-microamp = <3000>;
	402	};
	403	};
	404
	405	i2c2_sda_z_pins: i2c2-sda-z {
	406	mux {
	407	groups = "i2c2_sda_z";
	408	function = "i2c2";
	409	bias-disable;
	410	drive-strength-microamp = <3000>;
	411	};
	412	};
	413
	414	i2c2_sck_z_pins: i2c2-sck-z {
	415	mux {
	416	groups = "i2c2_sck_z";
	417	function = "i2c2";
	418	bias-disable;
	419	drive-strength-microamp = <3000>;
	420	};
	421	};
	422
	423	i2c3_sda_h_pins: i2c3-sda-h {
	424	mux {
	425	groups = "i2c3_sda_h";
	426	function = "i2c3";
	427	bias-disable;
	428	drive-strength-microamp = <3000>;
	429	};
	430	};
	431
	432	i2c3_sck_h_pins: i2c3-sck-h {
	433	mux {
	434	groups = "i2c3_sck_h";
	435	function = "i2c3";
	436	bias-disable;
	437	drive-strength-microamp = <3000>;
	438	};
	439	};
	440
	441	i2c3_sda_a_pins: i2c3-sda-a {
	442	mux {
	443	groups = "i2c3_sda_a";
	444	function = "i2c3";
	445	bias-disable;
	446	drive-strength-microamp = <3000>;
	447	};
	448	};
	449
	450	i2c3_sck_a_pins: i2c3-sck-a {
	451	mux {
	452	groups = "i2c3_sck_a";
	453	function = "i2c3";
	454	bias-disable;
	455	drive-strength-microamp = <3000>;
	456	};
	457	};
	458
	459	mclk0_a_pins: mclk0-a {
	460	mux {
	461	groups = "mclk0_a";
	462	function = "mclk0";
	463	bias-disable;
	464	drive-strength-microamp = <3000>;
	465	};
	466	};
	467
	468	mclk1_a_pins: mclk1-a {
	469	mux {
	470	groups = "mclk1_a";
	471	function = "mclk1";
	472	bias-disable;
	473	drive-strength-microamp = <3000>;
	474	};
	475	};
	476
	477	mclk1_x_pins: mclk1-x {
	478	mux {
	479	groups = "mclk1_x";
	480	function = "mclk1";
	481	bias-disable;
	482	drive-strength-microamp = <3000>;
	483	};
	484	};
	485
	486	mclk1_z_pins: mclk1-z {
	487	mux {
	488	groups = "mclk1_z";
	489	function = "mclk1";
	490	bias-disable;
	491	drive-strength-microamp = <3000>;
	492	};
	493	};
	494
	495	pdm_din0_a_pins: pdm-din0-a {
	496	mux {
	497	groups = "pdm_din0_a";
	498	function = "pdm";
	499	bias-disable;
	500	};
	501	};
	502
	503	pdm_din0_c_pins: pdm-din0-c {
	504	mux {
	505	groups = "pdm_din0_c";
	506	function = "pdm";
	507	bias-disable;
	508	};
	509	};
	510
	511	pdm_din0_x_pins: pdm-din0-x {
	512	mux {
	513	groups = "pdm_din0_x";
	514	function = "pdm";
	515	bias-disable;
	516	};
	517	};
	518
	519	pdm_din0_z_pins: pdm-din0-z {
	520	mux {
	521	groups = "pdm_din0_z";
	522	function = "pdm";
	523	bias-disable;
	524	};
	525	};
	526
	527	pdm_din1_a_pins: pdm-din1-a {
	528	mux {
	529	groups = "pdm_din1_a";
	530	function = "pdm";
	531	bias-disable;
	532	};
	533	};
	534
	535	pdm_din1_c_pins: pdm-din1-c {
	536	mux {
	537	groups = "pdm_din1_c";
	538	function = "pdm";
	539	bias-disable;
	540	};
	541	};
	542
	543	pdm_din1_x_pins: pdm-din1-x {
	544	mux {
	545	groups = "pdm_din1_x";
	546	function = "pdm";
	547	bias-disable;
	548	};
	549	};
	550
	551	pdm_din1_z_pins: pdm-din1-z {
	552	mux {
	553	groups = "pdm_din1_z";
	554	function = "pdm";
	555	bias-disable;
	556	};
	557	};
	558
	559	pdm_din2_a_pins: pdm-din2-a {
	560	mux {
	561	groups = "pdm_din2_a";
	562	function = "pdm";
	563	bias-disable;
	564	};
	565	};
	566
	567	pdm_din2_c_pins: pdm-din2-c {
	568	mux {
	569	groups = "pdm_din2_c";
	570	function = "pdm";
	571	bias-disable;
	572	};
	573	};
	574
	575	pdm_din2_x_pins: pdm-din2-x {
	576	mux {
	577	groups = "pdm_din2_x";
	578	function = "pdm";
	579	bias-disable;
	580	};
	581	};
	582
	583	pdm_din2_z_pins: pdm-din2-z {
	584	mux {
	585	groups = "pdm_din2_z";
	586	function = "pdm";
	587	bias-disable;
	588	};
	589	};
	590
	591	pdm_din3_a_pins: pdm-din3-a {
	592	mux {
	593	groups = "pdm_din3_a";
	594	function = "pdm";
	595	bias-disable;
	596	};
	597	};
	598
	599	pdm_din3_c_pins: pdm-din3-c {
	600	mux {
	601	groups = "pdm_din3_c";
	602	function = "pdm";
	603	bias-disable;
	604	};
	605	};
	606
	607	pdm_din3_x_pins: pdm-din3-x {
	608	mux {
	609	groups = "pdm_din3_x";
	610	function = "pdm";
	611	bias-disable;
	612	};
	613	};
	614
	615	pdm_din3_z_pins: pdm-din3-z {
	616	mux {
	617	groups = "pdm_din3_z";
	618	function = "pdm";
	619	bias-disable;
	620	};
	621	};
	622
	623	pdm_dclk_a_pins: pdm-dclk-a {
	624	mux {
	625	groups = "pdm_dclk_a";
	626	function = "pdm";
	627	bias-disable;
	628	drive-strength-microamp = <500>;
	629	};
	630	};
	631
	632	pdm_dclk_c_pins: pdm-dclk-c {
	633	mux {
	634	groups = "pdm_dclk_c";
	635	function = "pdm";
	636	bias-disable;
	637	drive-strength-microamp = <500>;
	638	};
	639	};
	640
	641	pdm_dclk_x_pins: pdm-dclk-x {
	642	mux {
	643	groups = "pdm_dclk_x";
	644	function = "pdm";
	645	bias-disable;
	646	drive-strength-microamp = <500>;
	647	};
	648	};
	649
	650	pdm_dclk_z_pins: pdm-dclk-z {
	651	mux {
	652	groups = "pdm_dclk_z";
	653	function = "pdm";
	654	bias-disable;
	655	drive-strength-microamp = <500>;
	656	};
	657	};
	658
	659	pwm_a_pins: pwm-a {
	660	mux {
	661	groups = "pwm_a";
	662	function = "pwm_a";
	663	bias-disable;
	664	};
	665	};
	666
	667	pwm_b_x7_pins: pwm-b-x7 {
	668	mux {
	669	groups = "pwm_b_x7";
	670	function = "pwm_b";
	671	bias-disable;
	672	};
	673	};
	674
	675	pwm_b_x19_pins: pwm-b-x19 {
	676	mux {
	677	groups = "pwm_b_x19";
	678	function = "pwm_b";
	679	bias-disable;
	680	};
	681	};
	682
	683	pwm_c_c_pins: pwm-c-c {
	684	mux {
	685	groups = "pwm_c_c";
	686	function = "pwm_c";
	687	bias-disable;
	688	};
	689	};
	690
	691	pwm_c_x5_pins: pwm-c-x5 {
	692	mux {
	693	groups = "pwm_c_x5";
	694	function = "pwm_c";
	695	bias-disable;
	696	};
	697	};
	698
	699	pwm_c_x8_pins: pwm-c-x8 {
	700	mux {
	701	groups = "pwm_c_x8";
	702	function = "pwm_c";
	703	bias-disable;
	704	};
	705	};
	706
	707	pwm_d_x3_pins: pwm-d-x3 {
	708	mux {
	709	groups = "pwm_d_x3";
	710	function = "pwm_d";
	711	bias-disable;
	712	};
	713	};
	714
	715	pwm_d_x6_pins: pwm-d-x6 {
	716	mux {
	717	groups = "pwm_d_x6";
	718	function = "pwm_d";
	719	bias-disable;
	720	};
	721	};
	722
	723	pwm_e_pins: pwm-e {
	724	mux {
	725	groups = "pwm_e";
	726	function = "pwm_e";
	727	bias-disable;
	728	};
	729	};
	730
	731	pwm_f_x_pins: pwm-f-x {
	732	mux {
	733	groups = "pwm_f_x";
	734	function = "pwm_f";
	735	bias-disable;
	736	};
	737	};
	738
	739	pwm_f_h_pins: pwm-f-h {
	740	mux {
	741	groups = "pwm_f_h";
	742	function = "pwm_f";
	743	bias-disable;
	744	};
	745	};
	746
	747	sdcard_c_pins: sdcard_c {
	748	mux-0 {
	749	groups = "sdcard_d0_c",
	750	"sdcard_d1_c",
	751	"sdcard_d2_c",
	752	"sdcard_d3_c",
	753	"sdcard_cmd_c";
	754	function = "sdcard";
	755	bias-pull-up;
	756	drive-strength-microamp = <4000>;
	757	};
	758
	759	mux-1 {
	760	groups = "sdcard_clk_c";
	761	function = "sdcard";
	762	bias-disable;
	763	drive-strength-microamp = <4000>;
	764	};
	765	};
	766
	767	sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
	768	mux {
	769	groups = "GPIOC_4";
	770	function = "gpio_periphs";
	771	bias-pull-down;
	772	drive-strength-microamp = <4000>;
	773	};
	774	};
	775
	776	sdcard_z_pins: sdcard_z {
	777	mux-0 {
	778	groups = "sdcard_d0_z",
	779	"sdcard_d1_z",
	780	"sdcard_d2_z",
	781	"sdcard_d3_z",
	782	"sdcard_cmd_z";
	783	function = "sdcard";
	784	bias-pull-up;
	785	drive-strength-microamp = <4000>;
	786	};
	787
	788	mux-1 {
	789	groups = "sdcard_clk_z";
	790	function = "sdcard";
	791	bias-disable;
	792	drive-strength-microamp = <4000>;
	793	};
	794	};
	795
	796	sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
	797	mux {
	798	groups = "GPIOZ_6";
	799	function = "gpio_periphs";
	800	bias-pull-down;
	801	drive-strength-microamp = <4000>;
	802	};
	803	};
	804
	805	sdio_pins: sdio {
	806	mux {
	807	groups = "sdio_d0",
	808	"sdio_d1",
	809	"sdio_d2",
	810	"sdio_d3",
	811	"sdio_clk",
	812	"sdio_cmd";
	813	function = "sdio";
	814	bias-disable;
	815	drive-strength-microamp = <4000>;
	816	};
	817	};
	818
	819	sdio_clk_gate_pins: sdio_clk_gate {
	820	mux {
	821	groups = "GPIOX_4";
	822	function = "gpio_periphs";
	823	bias-pull-down;
	824	drive-strength-microamp = <4000>;
	825	};
	826	};
	827
	828	spdif_in_a10_pins: spdif-in-a10 {
	829	mux {
	830	groups = "spdif_in_a10";
	831	function = "spdif_in";
	832	bias-disable;
	833	};
	834	};
	835
	836	spdif_in_a12_pins: spdif-in-a12 {
	837	mux {
	838	groups = "spdif_in_a12";
	839	function = "spdif_in";
	840	bias-disable;
	841	};
	842	};
	843
	844	spdif_in_h_pins: spdif-in-h {
	845	mux {
	846	groups = "spdif_in_h";
	847	function = "spdif_in";
	848	bias-disable;
	849	};
	850	};
	851
	852	spdif_out_h_pins: spdif-out-h {
	853	mux {
	854	groups = "spdif_out_h";
	855	function = "spdif_out";
	856	drive-strength-microamp = <500>;
	857	bias-disable;
	858	};
	859	};
	860
	861	spdif_out_a11_pins: spdif-out-a11 {
	862	mux {
	863	groups = "spdif_out_a11";
	864	function = "spdif_out";
	865	drive-strength-microamp = <500>;
	866	bias-disable;
	867	};
	868	};
	869
	870	spdif_out_a13_pins: spdif-out-a13 {
	871	mux {
	872	groups = "spdif_out_a13";
	873	function = "spdif_out";
	874	drive-strength-microamp = <500>;
	875	bias-disable;
	876	};
	877	};
	878
	879	tdm_a_din0_pins: tdm-a-din0 {
	880	mux {
	881	groups = "tdm_a_din0";
	882	function = "tdm_a";
	883	bias-disable;
	884	};
	885	};
	886
	887
	888	tdm_a_din1_pins: tdm-a-din1 {
	889	mux {
	890	groups = "tdm_a_din1";
	891	function = "tdm_a";
	892	bias-disable;
	893	};
	894	};
	895
	896	tdm_a_dout0_pins: tdm-a-dout0 {
	897	mux {
	898	groups = "tdm_a_dout0";
	899	function = "tdm_a";
	900	bias-disable;
	901	drive-strength-microamp = <3000>;
	902	};
	903	};
	904
	905	tdm_a_dout1_pins: tdm-a-dout1 {
	906	mux {
	907	groups = "tdm_a_dout1";
	908	function = "tdm_a";
	909	bias-disable;
	910	drive-strength-microamp = <3000>;
	911	};
	912	};
	913
	914	tdm_a_fs_pins: tdm-a-fs {
	915	mux {
	916	groups = "tdm_a_fs";
	917	function = "tdm_a";
	918	bias-disable;
	919	drive-strength-microamp = <3000>;
	920	};
	921	};
	922
	923	tdm_a_sclk_pins: tdm-a-sclk {
	924	mux {
	925	groups = "tdm_a_sclk";
	926	function = "tdm_a";
	927	bias-disable;
	928	drive-strength-microamp = <3000>;
	929	};
	930	};
	931
	932	tdm_a_slv_fs_pins: tdm-a-slv-fs {
	933	mux {
	934	groups = "tdm_a_slv_fs";
	935	function = "tdm_a";
	936	bias-disable;
	937	};
	938	};
	939
	940
	941	tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
	942	mux {
	943	groups = "tdm_a_slv_sclk";
	944	function = "tdm_a";
	945	bias-disable;
	946	};
	947	};
	948
	949	tdm_b_din0_pins: tdm-b-din0 {
	950	mux {
	951	groups = "tdm_b_din0";
	952	function = "tdm_b";
	953	bias-disable;
	954	};
	955	};
	956
	957	tdm_b_din1_pins: tdm-b-din1 {
	958	mux {
	959	groups = "tdm_b_din1";
	960	function = "tdm_b";
	961	bias-disable;
	962	};
	963	};
	964
	965	tdm_b_din2_pins: tdm-b-din2 {
	966	mux {
	967	groups = "tdm_b_din2";
	968	function = "tdm_b";
	969	bias-disable;
	970	};
	971	};
	972
	973	tdm_b_din3_a_pins: tdm-b-din3-a {
	974	mux {
	975	groups = "tdm_b_din3_a";
	976	function = "tdm_b";
	977	bias-disable;
	978	};
	979	};
	980
	981	tdm_b_din3_h_pins: tdm-b-din3-h {
	982	mux {
	983	groups = "tdm_b_din3_h";
	984	function = "tdm_b";
	985	bias-disable;
	986	};
	987	};
	988
	989	tdm_b_dout0_pins: tdm-b-dout0 {
	990	mux {
	991	groups = "tdm_b_dout0";
	992	function = "tdm_b";
	993	bias-disable;
	994	drive-strength-microamp = <3000>;
	995	};
	996	};
	997
	998	tdm_b_dout1_pins: tdm-b-dout1 {
	999	mux {
	1000	groups = "tdm_b_dout1";
	1001	function = "tdm_b";
	1002	bias-disable;
	1003	drive-strength-microamp = <3000>;
	1004	};
	1005	};
	1006
	1007	tdm_b_dout2_pins: tdm-b-dout2 {
	1008	mux {
	1009	groups = "tdm_b_dout2";
	1010	function = "tdm_b";
	1011	bias-disable;
	1012	drive-strength-microamp = <3000>;
	1013	};
	1014	};
	1015
	1016	tdm_b_dout3_a_pins: tdm-b-dout3-a {
	1017	mux {
	1018	groups = "tdm_b_dout3_a";
	1019	function = "tdm_b";
	1020	bias-disable;
	1021	drive-strength-microamp = <3000>;
	1022	};
	1023	};
	1024
	1025	tdm_b_dout3_h_pins: tdm-b-dout3-h {
	1026	mux {
	1027	groups = "tdm_b_dout3_h";
	1028	function = "tdm_b";
	1029	bias-disable;
	1030	drive-strength-microamp = <3000>;
	1031	};
	1032	};
	1033
	1034	tdm_b_fs_pins: tdm-b-fs {
	1035	mux {
	1036	groups = "tdm_b_fs";
	1037	function = "tdm_b";
	1038	bias-disable;
	1039	drive-strength-microamp = <3000>;
	1040	};
	1041	};
	1042
	1043	tdm_b_sclk_pins: tdm-b-sclk {
	1044	mux {
	1045	groups = "tdm_b_sclk";
	1046	function = "tdm_b";
	1047	bias-disable;
	1048	drive-strength-microamp = <3000>;
	1049	};
	1050	};
	1051
	1052	tdm_b_slv_fs_pins: tdm-b-slv-fs {
	1053	mux {
	1054	groups = "tdm_b_slv_fs";
	1055	function = "tdm_b";
	1056	bias-disable;
	1057	};
	1058	};
	1059
	1060	tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
	1061	mux {
	1062	groups = "tdm_b_slv_sclk";
	1063	function = "tdm_b";
	1064	bias-disable;
	1065	};
	1066	};
	1067
	1068	tdm_c_din0_a_pins: tdm-c-din0-a {
	1069	mux {
	1070	groups = "tdm_c_din0_a";
	1071	function = "tdm_c";
	1072	bias-disable;
	1073	};
	1074	};
	1075
	1076	tdm_c_din0_z_pins: tdm-c-din0-z {
	1077	mux {
	1078	groups = "tdm_c_din0_z";
	1079	function = "tdm_c";
	1080	bias-disable;
	1081	};
	1082	};
	1083
	1084	tdm_c_din1_a_pins: tdm-c-din1-a {
	1085	mux {
	1086	groups = "tdm_c_din1_a";
	1087	function = "tdm_c";
	1088	bias-disable;
	1089	};
	1090	};
	1091
	1092	tdm_c_din1_z_pins: tdm-c-din1-z {
	1093	mux {
	1094	groups = "tdm_c_din1_z";
	1095	function = "tdm_c";
	1096	bias-disable;
	1097	};
	1098	};
	1099
	1100	tdm_c_din2_a_pins: tdm-c-din2-a {
	1101	mux {
	1102	groups = "tdm_c_din2_a";
	1103	function = "tdm_c";
	1104	bias-disable;
	1105	};
	1106	};
	1107
	1108	eth_leds_pins: eth-leds {
	1109	mux {
	1110	groups = "eth_link_led",
	1111	"eth_act_led";
	1112	function = "eth";
	1113	bias-disable;
	1114	};
	1115	};
	1116
	1117	eth_pins: eth {
	1118	mux {
	1119	groups = "eth_mdio",
	1120	"eth_mdc",
	1121	"eth_rgmii_rx_clk",
	1122	"eth_rx_dv",
	1123	"eth_rxd0",
	1124	"eth_rxd1",
	1125	"eth_txen",
	1126	"eth_txd0",
	1127	"eth_txd1";
	1128	function = "eth";
	1129	drive-strength-microamp = <4000>;
	1130	bias-disable;
	1131	};
	1132	};
	1133
	1134	eth_rgmii_pins: eth-rgmii {
	1135	mux {
	1136	groups = "eth_rxd2_rgmii",
	1137	"eth_rxd3_rgmii",
	1138	"eth_rgmii_tx_clk",
	1139	"eth_txd2_rgmii",
	1140	"eth_txd3_rgmii";
	1141	function = "eth";
	1142	drive-strength-microamp = <4000>;
	1143	bias-disable;
	1144	};
	1145	};
	1146
	1147	tdm_c_din2_z_pins: tdm-c-din2-z {
	1148	mux {
	1149	groups = "tdm_c_din2_z";
	1150	function = "tdm_c";
	1151	bias-disable;
	1152	};
	1153	};
	1154
	1155	tdm_c_din3_a_pins: tdm-c-din3-a {
	1156	mux {
	1157	groups = "tdm_c_din3_a";
	1158	function = "tdm_c";
	1159	bias-disable;
	1160	};
	1161	};
	1162
	1163	tdm_c_din3_z_pins: tdm-c-din3-z {
	1164	mux {
	1165	groups = "tdm_c_din3_z";
	1166	function = "tdm_c";
	1167	bias-disable;
	1168	};
	1169	};
	1170
	1171	tdm_c_dout0_a_pins: tdm-c-dout0-a {
	1172	mux {
	1173	groups = "tdm_c_dout0_a";
	1174	function = "tdm_c";
	1175	bias-disable;
	1176	drive-strength-microamp = <3000>;
	1177	};
	1178	};
	1179
	1180	tdm_c_dout0_z_pins: tdm-c-dout0-z {
	1181	mux {
	1182	groups = "tdm_c_dout0_z";
	1183	function = "tdm_c";
	1184	bias-disable;
	1185	drive-strength-microamp = <3000>;
	1186	};
	1187	};
	1188
	1189	tdm_c_dout1_a_pins: tdm-c-dout1-a {
	1190	mux {
	1191	groups = "tdm_c_dout1_a";
	1192	function = "tdm_c";
	1193	bias-disable;
	1194	drive-strength-microamp = <3000>;
	1195	};
	1196	};
	1197
	1198	tdm_c_dout1_z_pins: tdm-c-dout1-z {
	1199	mux {
	1200	groups = "tdm_c_dout1_z";
	1201	function = "tdm_c";
	1202	bias-disable;
	1203	drive-strength-microamp = <3000>;
	1204	};
	1205	};
	1206
	1207	tdm_c_dout2_a_pins: tdm-c-dout2-a {
	1208	mux {
	1209	groups = "tdm_c_dout2_a";
	1210	function = "tdm_c";
	1211	bias-disable;
	1212	drive-strength-microamp = <3000>;
	1213	};
	1214	};
	1215
	1216	tdm_c_dout2_z_pins: tdm-c-dout2-z {
	1217	mux {
	1218	groups = "tdm_c_dout2_z";
	1219	function = "tdm_c";
	1220	bias-disable;
	1221	drive-strength-microamp = <3000>;
	1222	};
	1223	};
	1224
	1225	tdm_c_dout3_a_pins: tdm-c-dout3-a {
	1226	mux {
	1227	groups = "tdm_c_dout3_a";
	1228	function = "tdm_c";
	1229	bias-disable;
	1230	drive-strength-microamp = <3000>;
	1231	};
	1232	};
	1233
	1234	tdm_c_dout3_z_pins: tdm-c-dout3-z {
	1235	mux {
	1236	groups = "tdm_c_dout3_z";
	1237	function = "tdm_c";
	1238	bias-disable;
	1239	drive-strength-microamp = <3000>;
	1240	};
	1241	};
	1242
	1243	tdm_c_fs_a_pins: tdm-c-fs-a {
	1244	mux {
	1245	groups = "tdm_c_fs_a";
	1246	function = "tdm_c";
	1247	bias-disable;
	1248	drive-strength-microamp = <3000>;
	1249	};
	1250	};
	1251
	1252	tdm_c_fs_z_pins: tdm-c-fs-z {
	1253	mux {
	1254	groups = "tdm_c_fs_z";
	1255	function = "tdm_c";
	1256	bias-disable;
	1257	drive-strength-microamp = <3000>;
	1258	};
	1259	};
	1260
	1261	tdm_c_sclk_a_pins: tdm-c-sclk-a {
	1262	mux {
	1263	groups = "tdm_c_sclk_a";
	1264	function = "tdm_c";
	1265	bias-disable;
	1266	drive-strength-microamp = <3000>;
	1267	};
	1268	};
	1269
	1270	tdm_c_sclk_z_pins: tdm-c-sclk-z {
	1271	mux {
	1272	groups = "tdm_c_sclk_z";
	1273	function = "tdm_c";
	1274	bias-disable;
	1275	drive-strength-microamp = <3000>;
	1276	};
	1277	};
	1278
	1279	tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
	1280	mux {
	1281	groups = "tdm_c_slv_fs_a";
	1282	function = "tdm_c";
	1283	bias-disable;
	1284	};
	1285	};
	1286
	1287	tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
	1288	mux {
	1289	groups = "tdm_c_slv_fs_z";
	1290	function = "tdm_c";
	1291	bias-disable;
	1292	};
	1293	};
	1294
	1295	tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
	1296	mux {
	1297	groups = "tdm_c_slv_sclk_a";
	1298	function = "tdm_c";
	1299	bias-disable;
	1300	};
	1301	};
	1302
	1303	tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
	1304	mux {
	1305	groups = "tdm_c_slv_sclk_z";
	1306	function = "tdm_c";
	1307	bias-disable;
	1308	};
	1309	};
	1310
	1311	uart_a_pins: uart-a {
	1312	mux {
	1313	groups = "uart_a_tx",
	1314	"uart_a_rx";
	1315	function = "uart_a";
	1316	bias-disable;
	1317	};
	1318	};
	1319
	1320	uart_a_cts_rts_pins: uart-a-cts-rts {
	1321	mux {
	1322	groups = "uart_a_cts",
	1323	"uart_a_rts";
	1324	function = "uart_a";
	1325	bias-disable;
	1326	};
	1327	};
	1328
	1329	uart_b_pins: uart-b {
	1330	mux {
	1331	groups = "uart_b_tx",
	1332	"uart_b_rx";
	1333	function = "uart_b";
	1334	bias-disable;
	1335	};
	1336	};
	1337
	1338	uart_c_pins: uart-c {
	1339	mux {
	1340	groups = "uart_c_tx",
	1341	"uart_c_rx";
	1342	function = "uart_c";
	1343	bias-disable;
	1344	};
	1345	};
	1346
	1347	uart_c_cts_rts_pins: uart-c-cts-rts {
	1348	mux {
	1349	groups = "uart_c_cts",
	1350	"uart_c_rts";
	1351	function = "uart_c";
	1352	bias-disable;
	1353	};
	1354	};
	1355	};
	1356	};
	1357
	1358	usb2_phy0: phy@36000 {
	1359	compatible = "amlogic,g12a-usb2-phy";
	1360	reg = <0x0 0x36000 0x0 0x2000>;
	1361	clocks = <&xtal>;
	1362	clock-names = "xtal";
	1363	resets = <&reset RESET_USB_PHY20>;
	1364	reset-names = "phy";
	1365	#phy-cells = <0>;
	1366	};
	1367
	1368	dmc: bus@38000 {
	1369	compatible = "simple-bus";
	1370	reg = <0x0 0x38000 0x0 0x400>;
	1371	#address-cells = <2>;
	1372	#size-cells = <2>;
	1373	ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
	1374
	1375	canvas: video-lut@48 {
	1376	compatible = "amlogic,canvas";
	1377	reg = <0x0 0x48 0x0 0x14>;
	1378	};
	1379	};
	1380
	1381	usb2_phy1: phy@3a000 {
	1382	compatible = "amlogic,g12a-usb2-phy";
	1383	reg = <0x0 0x3a000 0x0 0x2000>;
	1384	clocks = <&xtal>;
	1385	clock-names = "xtal";
	1386	resets = <&reset RESET_USB_PHY21>;
	1387	reset-names = "phy";
	1388	#phy-cells = <0>;
	1389	};
	1390
	1391	hiu: bus@3c000 {
	1392	compatible = "simple-bus";
	1393	reg = <0x0 0x3c000 0x0 0x1400>;
	1394	#address-cells = <2>;
	1395	#size-cells = <2>;
	1396	ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
	1397
	1398	hhi: system-controller@0 {
	1399	compatible = "amlogic,meson-gx-hhi-sysctrl",
	1400	"simple-mfd", "syscon";
	1401	reg = <0 0 0 0x400>;
	1402
	1403	clkc: clock-controller {
	1404	compatible = "amlogic,g12a-clkc";
	1405	#clock-cells = <1>;
	1406	clocks = <&xtal>;
	1407	clock-names = "xtal";
	1408	};
	1409	};
	1410	};
	1411
	1412	pdm: audio-controller@40000 {
	1413	compatible = "amlogic,g12a-pdm",
	1414	"amlogic,axg-pdm";
	1415	reg = <0x0 0x40000 0x0 0x34>;
	1416	#sound-dai-cells = <0>;
	1417	sound-name-prefix = "PDM";
	1418	clocks = <&clkc_audio AUD_CLKID_PDM>,
	1419	<&clkc_audio AUD_CLKID_PDM_DCLK>,
	1420	<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
	1421	clock-names = "pclk", "dclk", "sysclk";
	1422	status = "disabled";
	1423	};
	1424
	1425	audio: bus@42000 {
	1426	compatible = "simple-bus";
	1427	reg = <0x0 0x42000 0x0 0x2000>;
	1428	#address-cells = <2>;
	1429	#size-cells = <2>;
	1430	ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
	1431
	1432	clkc_audio: clock-controller@0 {
	1433	status = "disabled";
	1434	compatible = "amlogic,g12a-audio-clkc";
	1435	reg = <0x0 0x0 0x0 0xb4>;
	1436	#clock-cells = <1>;
	1437
	1438	clocks = <&clkc CLKID_AUDIO>,
	1439	<&clkc CLKID_MPLL0>,
	1440	<&clkc CLKID_MPLL1>,
	1441	<&clkc CLKID_MPLL2>,
	1442	<&clkc CLKID_MPLL3>,
	1443	<&clkc CLKID_HIFI_PLL>,
	1444	<&clkc CLKID_FCLK_DIV3>,
	1445	<&clkc CLKID_FCLK_DIV4>,
	1446	<&clkc CLKID_GP0_PLL>;
	1447	clock-names = "pclk",
	1448	"mst_in0",
	1449	"mst_in1",
	1450	"mst_in2",
	1451	"mst_in3",
	1452	"mst_in4",
	1453	"mst_in5",
	1454	"mst_in6",
	1455	"mst_in7";
	1456
	1457	resets = <&reset RESET_AUDIO>;
	1458	};
	1459
	1460	toddr_a: audio-controller@100 {
	1461	compatible = "amlogic,g12a-toddr",
	1462	"amlogic,axg-toddr";
	1463	reg = <0x0 0x100 0x0 0x1c>;
	1464	#sound-dai-cells = <0>;
	1465	sound-name-prefix = "TODDR_A";
	1466	interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
	1467	clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
	1468	resets = <&arb AXG_ARB_TODDR_A>;
	1469	status = "disabled";
	1470	};
	1471
	1472	toddr_b: audio-controller@140 {
	1473	compatible = "amlogic,g12a-toddr",
	1474	"amlogic,axg-toddr";
	1475	reg = <0x0 0x140 0x0 0x1c>;
	1476	#sound-dai-cells = <0>;
	1477	sound-name-prefix = "TODDR_B";
	1478	interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
	1479	clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
	1480	resets = <&arb AXG_ARB_TODDR_B>;
	1481	status = "disabled";
	1482	};
	1483
	1484	toddr_c: audio-controller@180 {
	1485	compatible = "amlogic,g12a-toddr",
	1486	"amlogic,axg-toddr";
	1487	reg = <0x0 0x180 0x0 0x1c>;
	1488	#sound-dai-cells = <0>;
	1489	sound-name-prefix = "TODDR_C";
	1490	interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
	1491	clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
	1492	resets = <&arb AXG_ARB_TODDR_C>;
	1493	status = "disabled";
	1494	};
	1495
	1496	frddr_a: audio-controller@1c0 {
	1497	compatible = "amlogic,g12a-frddr",
	1498	"amlogic,axg-frddr";
	1499	reg = <0x0 0x1c0 0x0 0x1c>;
	1500	#sound-dai-cells = <0>;
	1501	sound-name-prefix = "FRDDR_A";
	1502	interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
	1503	clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
	1504	resets = <&arb AXG_ARB_FRDDR_A>;
	1505	status = "disabled";
	1506	};
	1507
	1508	frddr_b: audio-controller@200 {
	1509	compatible = "amlogic,g12a-frddr",
	1510	"amlogic,axg-frddr";
	1511	reg = <0x0 0x200 0x0 0x1c>;
	1512	#sound-dai-cells = <0>;
	1513	sound-name-prefix = "FRDDR_B";
	1514	interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
	1515	clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
	1516	resets = <&arb AXG_ARB_FRDDR_B>;
	1517	status = "disabled";
	1518	};
	1519
	1520	frddr_c: audio-controller@240 {
	1521	compatible = "amlogic,g12a-frddr",
	1522	"amlogic,axg-frddr";
	1523	reg = <0x0 0x240 0x0 0x1c>;
	1524	#sound-dai-cells = <0>;
	1525	sound-name-prefix = "FRDDR_C";
	1526	interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
	1527	clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
	1528	resets = <&arb AXG_ARB_FRDDR_C>;
	1529	status = "disabled";
	1530	};
	1531
	1532	arb: reset-controller@280 {
	1533	status = "disabled";
	1534	compatible = "amlogic,meson-axg-audio-arb";
	1535	reg = <0x0 0x280 0x0 0x4>;
	1536	#reset-cells = <1>;
	1537	clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
	1538	};
	1539
	1540	tdmin_a: audio-controller@300 {
	1541	compatible = "amlogic,g12a-tdmin",
	1542	"amlogic,axg-tdmin";
	1543	reg = <0x0 0x300 0x0 0x40>;
	1544	sound-name-prefix = "TDMIN_A";
	1545	clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
	1546	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
	1547	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
	1548	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
	1549	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
	1550	clock-names = "pclk", "sclk", "sclk_sel",
	1551	"lrclk", "lrclk_sel";
	1552	status = "disabled";
	1553	};
	1554
	1555	tdmin_b: audio-controller@340 {
	1556	compatible = "amlogic,g12a-tdmin",
	1557	"amlogic,axg-tdmin";
	1558	reg = <0x0 0x340 0x0 0x40>;
	1559	sound-name-prefix = "TDMIN_B";
	1560	clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
	1561	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
	1562	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
	1563	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
	1564	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
	1565	clock-names = "pclk", "sclk", "sclk_sel",
	1566	"lrclk", "lrclk_sel";
	1567	status = "disabled";
	1568	};
	1569
	1570	tdmin_c: audio-controller@380 {
	1571	compatible = "amlogic,g12a-tdmin",
	1572	"amlogic,axg-tdmin";
	1573	reg = <0x0 0x380 0x0 0x40>;
	1574	sound-name-prefix = "TDMIN_C";
	1575	clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
	1576	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
	1577	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
	1578	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
	1579	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
	1580	clock-names = "pclk", "sclk", "sclk_sel",
	1581	"lrclk", "lrclk_sel";
	1582	status = "disabled";
	1583	};
	1584
	1585	tdmin_lb: audio-controller@3c0 {
	1586	compatible = "amlogic,g12a-tdmin",
	1587	"amlogic,axg-tdmin";
	1588	reg = <0x0 0x3c0 0x0 0x40>;
	1589	sound-name-prefix = "TDMIN_LB";
	1590	clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
	1591	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
	1592	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
	1593	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
	1594	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
	1595	clock-names = "pclk", "sclk", "sclk_sel",
	1596	"lrclk", "lrclk_sel";
	1597	status = "disabled";
	1598	};
	1599
	1600	spdifin: audio-controller@400 {
	1601	compatible = "amlogic,g12a-spdifin",
	1602	"amlogic,axg-spdifin";
	1603	reg = <0x0 0x400 0x0 0x30>;
	1604	#sound-dai-cells = <0>;
	1605	sound-name-prefix = "SPDIFIN";
	1606	interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
	1607	clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
	1608	<&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
	1609	clock-names = "pclk", "refclk";
	1610	status = "disabled";
	1611	};
	1612
	1613	spdifout: audio-controller@480 {
	1614	compatible = "amlogic,g12a-spdifout",
	1615	"amlogic,axg-spdifout";
	1616	reg = <0x0 0x480 0x0 0x50>;
	1617	#sound-dai-cells = <0>;
	1618	sound-name-prefix = "SPDIFOUT";
	1619	clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
	1620	<&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
	1621	clock-names = "pclk", "mclk";
	1622	status = "disabled";
	1623	};
	1624
	1625	tdmout_a: audio-controller@500 {
	1626	compatible = "amlogic,g12a-tdmout";
	1627	reg = <0x0 0x500 0x0 0x40>;
	1628	sound-name-prefix = "TDMOUT_A";
	1629	clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
	1630	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
	1631	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
	1632	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
	1633	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
	1634	clock-names = "pclk", "sclk", "sclk_sel",
	1635	"lrclk", "lrclk_sel";
	1636	status = "disabled";
	1637	};
	1638
	1639	tdmout_b: audio-controller@540 {
	1640	compatible = "amlogic,g12a-tdmout";
	1641	reg = <0x0 0x540 0x0 0x40>;
	1642	sound-name-prefix = "TDMOUT_B";
	1643	clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
	1644	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
	1645	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
	1646	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
	1647	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
	1648	clock-names = "pclk", "sclk", "sclk_sel",
	1649	"lrclk", "lrclk_sel";
	1650	status = "disabled";
	1651	};
	1652
	1653	tdmout_c: audio-controller@580 {
	1654	compatible = "amlogic,g12a-tdmout";
	1655	reg = <0x0 0x580 0x0 0x40>;
	1656	sound-name-prefix = "TDMOUT_C";
	1657	clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
	1658	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
	1659	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
	1660	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
	1661	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
	1662	clock-names = "pclk", "sclk", "sclk_sel",
	1663	"lrclk", "lrclk_sel";
	1664	status = "disabled";
	1665	};
	1666
	1667	spdifout_b: audio-controller@680 {
	1668	compatible = "amlogic,g12a-spdifout",
	1669	"amlogic,axg-spdifout";
	1670	reg = <0x0 0x680 0x0 0x50>;
	1671	#sound-dai-cells = <0>;
	1672	sound-name-prefix = "SPDIFOUT_B";
	1673	clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>,
	1674	<&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>;
	1675	clock-names = "pclk", "mclk";
	1676	status = "disabled";
	1677	};
	1678
	1679	tohdmitx: audio-controller@744 {
	1680	compatible = "amlogic,g12a-tohdmitx";
	1681	reg = <0x0 0x744 0x0 0x4>;
	1682	#sound-dai-cells = <1>;
	1683	sound-name-prefix = "TOHDMITX";
	1684	status = "disabled";
	1685	};
	1686	};
	1687
	1688	usb3_pcie_phy: phy@46000 {
	1689	compatible = "amlogic,g12a-usb3-pcie-phy";
	1690	reg = <0x0 0x46000 0x0 0x2000>;
	1691	clocks = <&clkc CLKID_PCIE_PLL>;
	1692	clock-names = "ref_clk";
	1693	resets = <&reset RESET_PCIE_PHY>;
	1694	reset-names = "phy";
	1695	assigned-clocks = <&clkc CLKID_PCIE_PLL>;
	1696	assigned-clock-rates = <100000000>;
	1697	#phy-cells = <1>;
	1698	};
	1699
	1700	eth_phy: mdio-multiplexer@4c000 {
	1701	compatible = "amlogic,g12a-mdio-mux";
	1702	reg = <0x0 0x4c000 0x0 0xa4>;
	1703	clocks = <&clkc CLKID_ETH_PHY>,
	1704	<&xtal>,
	1705	<&clkc CLKID_MPLL_50M>;
	1706	clock-names = "pclk", "clkin0", "clkin1";
	1707	mdio-parent-bus = <&mdio0>;
	1708	#address-cells = <1>;
	1709	#size-cells = <0>;
	1710
	1711	ext_mdio: mdio@0 {
	1712	reg = <0>;
	1713	#address-cells = <1>;
	1714	#size-cells = <0>;
	1715	};
	1716
	1717	int_mdio: mdio@1 {
	1718	reg = <1>;
	1719	#address-cells = <1>;
	1720	#size-cells = <0>;
	1721
	1722	internal_ephy: ethernet_phy@8 {
	1723	compatible = "ethernet-phy-id0180.3301",
	1724	"ethernet-phy-ieee802.3-c22";
	1725	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	1726	reg = <8>;
	1727	max-speed = <100>;
	1728	};
	1729	};
	1730	};
	1731	};
	1732
	1733	aobus: bus@ff800000 {
	1734	compatible = "simple-bus";
	1735	reg = <0x0 0xff800000 0x0 0x100000>;
	1736	#address-cells = <2>;
	1737	#size-cells = <2>;
	1738	ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
	1739
	1740	rti: sys-ctrl@0 {
	1741	compatible = "amlogic,meson-gx-ao-sysctrl",
	1742	"simple-mfd", "syscon";
	1743	reg = <0x0 0x0 0x0 0x100>;
	1744	#address-cells = <2>;
	1745	#size-cells = <2>;
	1746	ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
	1747
	1748	clkc_AO: clock-controller {
	1749	compatible = "amlogic,meson-g12a-aoclkc";
	1750	#clock-cells = <1>;
	1751	#reset-cells = <1>;
	1752	clocks = <&xtal>, <&clkc CLKID_CLK81>;
	1753	clock-names = "xtal", "mpeg-clk";
	1754	};
	1755
	1756	pwrc_vpu: power-controller-vpu {
	1757	compatible = "amlogic,meson-g12a-pwrc-vpu";
	1758	#power-domain-cells = <0>;
	1759	amlogic,hhi-sysctrl = <&hhi>;
	1760	resets = <&reset RESET_VIU>,
	1761	<&reset RESET_VENC>,
	1762	<&reset RESET_VCBUS>,
	1763	<&reset RESET_BT656>,
	1764	<&reset RESET_RDMA>,
	1765	<&reset RESET_VENCI>,
	1766	<&reset RESET_VENCP>,
	1767	<&reset RESET_VDAC>,
	1768	<&reset RESET_VDI6>,
	1769	<&reset RESET_VENCL>,
	1770	<&reset RESET_VID_LOCK>;
	1771	clocks = <&clkc CLKID_VPU>,
	1772	<&clkc CLKID_VAPB>;
	1773	clock-names = "vpu", "vapb";
	1774	/*
	1775	* VPU clocking is provided by two identical clock paths
	1776	* VPU_0 and VPU_1 muxed to a single clock by a glitch
	1777	* free mux to safely change frequency while running.
	1778	* Same for VAPB but with a final gate after the glitch free mux.
	1779	*/
	1780	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
	1781	<&clkc CLKID_VPU_0>,
	1782	<&clkc CLKID_VPU>, /* Glitch free mux */
	1783	<&clkc CLKID_VAPB_0_SEL>,
	1784	<&clkc CLKID_VAPB_0>,
	1785	<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
	1786	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
	1787	<0>, /* Do Nothing */
	1788	<&clkc CLKID_VPU_0>,
	1789	<&clkc CLKID_FCLK_DIV4>,
	1790	<0>, /* Do Nothing */
	1791	<&clkc CLKID_VAPB_0>;
	1792	assigned-clock-rates = <0>, /* Do Nothing */
	1793	<666666666>,
	1794	<0>, /* Do Nothing */
	1795	<0>, /* Do Nothing */
	1796	<250000000>,
	1797	<0>; /* Do Nothing */
	1798	};
	1799
	1800	ao_pinctrl: pinctrl@14 {
	1801	compatible = "amlogic,meson-g12a-aobus-pinctrl";
	1802	#address-cells = <2>;
	1803	#size-cells = <2>;
	1804	ranges;
	1805
	1806	gpio_ao: bank@14 {
	1807	reg = <0x0 0x14 0x0 0x8>,
	1808	<0x0 0x1c 0x0 0x8>,
	1809	<0x0 0x24 0x0 0x14>;
	1810	reg-names = "mux",
	1811	"ds",
	1812	"gpio";
	1813	gpio-controller;
	1814	#gpio-cells = <2>;
	1815	gpio-ranges = <&ao_pinctrl 0 0 15>;
	1816	};
	1817
	1818	i2c_ao_sck_pins: i2c_ao_sck_pins {
	1819	mux {
	1820	groups = "i2c_ao_sck";
	1821	function = "i2c_ao";
	1822	bias-disable;
	1823	drive-strength-microamp = <3000>;
	1824	};
	1825	};
	1826
	1827	i2c_ao_sda_pins: i2c_ao_sda {
	1828	mux {
	1829	groups = "i2c_ao_sda";
	1830	function = "i2c_ao";
	1831	bias-disable;
	1832	drive-strength-microamp = <3000>;
	1833	};
	1834	};
	1835
	1836	i2c_ao_sck_e_pins: i2c_ao_sck_e {
	1837	mux {
	1838	groups = "i2c_ao_sck_e";
	1839	function = "i2c_ao";
	1840	bias-disable;
	1841	drive-strength-microamp = <3000>;
	1842	};
	1843	};
	1844
	1845	i2c_ao_sda_e_pins: i2c_ao_sda_e {
	1846	mux {
	1847	groups = "i2c_ao_sda_e";
	1848	function = "i2c_ao";
	1849	bias-disable;
	1850	drive-strength-microamp = <3000>;
	1851	};
	1852	};
	1853
	1854	mclk0_ao_pins: mclk0-ao {
	1855	mux {
	1856	groups = "mclk0_ao";
	1857	function = "mclk0_ao";
	1858	bias-disable;
	1859	drive-strength-microamp = <3000>;
	1860	};
	1861	};
	1862
	1863	tdm_ao_b_din0_pins: tdm-ao-b-din0 {
	1864	mux {
	1865	groups = "tdm_ao_b_din0";
	1866	function = "tdm_ao_b";
	1867	bias-disable;
	1868	};
	1869	};
	1870
	1871	spdif_ao_out_pins: spdif-ao-out {
	1872	mux {
	1873	groups = "spdif_ao_out";
	1874	function = "spdif_ao_out";
	1875	drive-strength-microamp = <500>;
	1876	bias-disable;
	1877	};
	1878	};
	1879
	1880	tdm_ao_b_din1_pins: tdm-ao-b-din1 {
	1881	mux {
	1882	groups = "tdm_ao_b_din1";
	1883	function = "tdm_ao_b";
	1884	bias-disable;
	1885	};
	1886	};
	1887
	1888	tdm_ao_b_din2_pins: tdm-ao-b-din2 {
	1889	mux {
	1890	groups = "tdm_ao_b_din2";
	1891	function = "tdm_ao_b";
	1892	bias-disable;
	1893	};
	1894	};
	1895
	1896	tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
	1897	mux {
	1898	groups = "tdm_ao_b_dout0";
	1899	function = "tdm_ao_b";
	1900	bias-disable;
	1901	drive-strength-microamp = <3000>;
	1902	};
	1903	};
	1904
	1905	tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
	1906	mux {
	1907	groups = "tdm_ao_b_dout1";
	1908	function = "tdm_ao_b";
	1909	bias-disable;
	1910	drive-strength-microamp = <3000>;
	1911	};
	1912	};
	1913
	1914	tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
	1915	mux {
	1916	groups = "tdm_ao_b_dout2";
	1917	function = "tdm_ao_b";
	1918	bias-disable;
	1919	drive-strength-microamp = <3000>;
	1920	};
	1921	};
	1922
	1923	tdm_ao_b_fs_pins: tdm-ao-b-fs {
	1924	mux {
	1925	groups = "tdm_ao_b_fs";
	1926	function = "tdm_ao_b";
	1927	bias-disable;
	1928	drive-strength-microamp = <3000>;
	1929	};
	1930	};
	1931
	1932	tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
	1933	mux {
	1934	groups = "tdm_ao_b_sclk";
	1935	function = "tdm_ao_b";
	1936	bias-disable;
	1937	drive-strength-microamp = <3000>;
	1938	};
	1939	};
	1940
	1941	tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
	1942	mux {
	1943	groups = "tdm_ao_b_slv_fs";
	1944	function = "tdm_ao_b";
	1945	bias-disable;
	1946	};
	1947	};
	1948
	1949	tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
	1950	mux {
	1951	groups = "tdm_ao_b_slv_sclk";
	1952	function = "tdm_ao_b";
	1953	bias-disable;
	1954	};
	1955	};
	1956
	1957	uart_ao_a_pins: uart-a-ao {
	1958	mux {
	1959	groups = "uart_ao_a_tx",
	1960	"uart_ao_a_rx";
	1961	function = "uart_ao_a";
	1962	bias-disable;
	1963	};
	1964	};
	1965
	1966	uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
	1967	mux {
	1968	groups = "uart_ao_a_cts",
	1969	"uart_ao_a_rts";
	1970	function = "uart_ao_a";
	1971	bias-disable;
	1972	};
	1973	};
	1974
	1975	pwm_a_e_pins: pwm-a-e {
	1976	mux {
	1977	groups = "pwm_a_e";
	1978	function = "pwm_a_e";
	1979	bias-disable;
	1980	};
	1981	};
	1982
	1983	pwm_ao_a_pins: pwm-ao-a {
	1984	mux {
	1985	groups = "pwm_ao_a";
	1986	function = "pwm_ao_a";
	1987	bias-disable;
	1988	};
	1989	};
	1990
	1991	pwm_ao_b_pins: pwm-ao-b {
	1992	mux {
	1993	groups = "pwm_ao_b";
	1994	function = "pwm_ao_b";
	1995	bias-disable;
	1996	};
	1997	};
	1998
	1999	pwm_ao_c_4_pins: pwm-ao-c-4 {
	2000	mux {
	2001	groups = "pwm_ao_c_4";
	2002	function = "pwm_ao_c";
	2003	bias-disable;
	2004	};
	2005	};
	2006
	2007	pwm_ao_c_6_pins: pwm-ao-c-6 {
	2008	mux {
	2009	groups = "pwm_ao_c_6";
	2010	function = "pwm_ao_c";
	2011	bias-disable;
	2012	};
	2013	};
	2014
	2015	pwm_ao_d_5_pins: pwm-ao-d-5 {
	2016	mux {
	2017	groups = "pwm_ao_d_5";
	2018	function = "pwm_ao_d";
	2019	bias-disable;
	2020	};
	2021	};
	2022
	2023	pwm_ao_d_10_pins: pwm-ao-d-10 {
	2024	mux {
	2025	groups = "pwm_ao_d_10";
	2026	function = "pwm_ao_d";
	2027	bias-disable;
	2028	};
	2029	};
	2030
	2031	pwm_ao_d_e_pins: pwm-ao-d-e {
	2032	mux {
	2033	groups = "pwm_ao_d_e";
	2034	function = "pwm_ao_d";
	2035	};
	2036	};
	2037
	2038	remote_input_ao_pins: remote-input-ao {
	2039	mux {
	2040	groups = "remote_ao_input";
	2041	function = "remote_ao_input";
	2042	bias-disable;
	2043	};
	2044	};
	2045	};
	2046	};
	2047
	2048	cec_AO: cec@100 {
	2049	compatible = "amlogic,meson-gx-ao-cec";
	2050	reg = <0x0 0x00100 0x0 0x14>;
	2051	interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
	2052	clocks = <&clkc_AO CLKID_AO_CEC>;
	2053	clock-names = "core";
	2054	status = "disabled";
	2055	};
	2056
	2057	sec_AO: ao-secure@140 {
	2058	compatible = "amlogic,meson-gx-ao-secure", "syscon";
	2059	reg = <0x0 0x140 0x0 0x140>;
	2060	amlogic,has-chip-id;
	2061	};
	2062
	2063	cecb_AO: cec@280 {
	2064	compatible = "amlogic,meson-g12a-ao-cec";
	2065	reg = <0x0 0x00280 0x0 0x1c>;
	2066	interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
	2067	clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
	2068	clock-names = "oscin";
	2069	status = "disabled";
	2070	};
	2071
	2072	pwm_AO_cd: pwm@2000 {
	2073	compatible = "amlogic,meson-g12a-ao-pwm-cd";
	2074	reg = <0x0 0x2000 0x0 0x20>;
	2075	#pwm-cells = <3>;
	2076	status = "disabled";
	2077	};
	2078
	2079	uart_AO: serial@3000 {
	2080	compatible = "amlogic,meson-gx-uart",
	2081	"amlogic,meson-ao-uart";
	2082	reg = <0x0 0x3000 0x0 0x18>;
	2083	interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
	2084	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
	2085	clock-names = "xtal", "pclk", "baud";
	2086	status = "disabled";
	2087	};
	2088
	2089	uart_AO_B: serial@4000 {
	2090	compatible = "amlogic,meson-gx-uart",
	2091	"amlogic,meson-ao-uart";
	2092	reg = <0x0 0x4000 0x0 0x18>;
	2093	interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
	2094	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
	2095	clock-names = "xtal", "pclk", "baud";
	2096	status = "disabled";
	2097	};
	2098
	2099	i2c_AO: i2c@5000 {
	2100	compatible = "amlogic,meson-axg-i2c";
	2101	status = "disabled";
	2102	reg = <0x0 0x05000 0x0 0x20>;
	2103	interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
	2104	#address-cells = <1>;
	2105	#size-cells = <0>;
	2106	clocks = <&clkc CLKID_I2C>;
	2107	};
	2108
	2109	pwm_AO_ab: pwm@7000 {
	2110	compatible = "amlogic,meson-g12a-ao-pwm-ab";
	2111	reg = <0x0 0x7000 0x0 0x20>;
	2112	#pwm-cells = <3>;
	2113	status = "disabled";
	2114	};
	2115
	2116	ir: ir@8000 {
	2117	compatible = "amlogic,meson-gxbb-ir";
	2118	reg = <0x0 0x8000 0x0 0x20>;
	2119	interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
	2120	status = "disabled";
	2121	};
	2122
	2123	saradc: adc@9000 {
	2124	compatible = "amlogic,meson-g12a-saradc",
	2125	"amlogic,meson-saradc";
	2126	reg = <0x0 0x9000 0x0 0x48>;
	2127	#io-channel-cells = <1>;
	2128	interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
	2129	clocks = <&xtal>,
	2130	<&clkc_AO CLKID_AO_SAR_ADC>,
	2131	<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
	2132	<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
	2133	clock-names = "clkin", "core", "adc_clk", "adc_sel";
	2134	status = "disabled";
	2135	};
	2136	};
	2137
	2138	vpu: vpu@ff900000 {
	2139	compatible = "amlogic,meson-g12a-vpu";
	2140	reg = <0x0 0xff900000 0x0 0x100000>,
	2141	<0x0 0xff63c000 0x0 0x1000>;
	2142	reg-names = "vpu", "hhi";
	2143	interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
	2144	#address-cells = <1>;
	2145	#size-cells = <0>;
	2146	amlogic,canvas = <&canvas>;
	2147	power-domains = <&pwrc_vpu>;
	2148
	2149	/* CVBS VDAC output port */
	2150	cvbs_vdac_port: port@0 {
	2151	reg = <0>;
	2152	};
	2153
	2154	/* HDMI-TX output port */
	2155	hdmi_tx_port: port@1 {
	2156	reg = <1>;
	2157
	2158	hdmi_tx_out: endpoint {
	2159	remote-endpoint = <&hdmi_tx_in>;
	2160	};
	2161	};
	2162	};
	2163
	2164	gic: interrupt-controller@ffc01000 {
	2165	compatible = "arm,gic-400";
	2166	reg = <0x0 0xffc01000 0 0x1000>,
	2167	<0x0 0xffc02000 0 0x2000>,
	2168	<0x0 0xffc04000 0 0x2000>,
	2169	<0x0 0xffc06000 0 0x2000>;
	2170	interrupt-controller;
	2171	interrupts = <GIC_PPI 9
	2172	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
	2173	#interrupt-cells = <3>;
	2174	#address-cells = <0>;
	2175	};
	2176
	2177	cbus: bus@ffd00000 {
	2178	compatible = "simple-bus";
	2179	reg = <0x0 0xffd00000 0x0 0x100000>;
	2180	#address-cells = <2>;
	2181	#size-cells = <2>;
	2182	ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
	2183
	2184	reset: reset-controller@1004 {
	2185	compatible = "amlogic,meson-g12a-reset",
	2186	"amlogic,meson-axg-reset";
	2187	reg = <0x0 0x1004 0x0 0x9c>;
	2188	#reset-cells = <1>;
	2189	};
	2190
	2191	gpio_intc: interrupt-controller@f080 {
	2192	compatible = "amlogic,meson-g12a-gpio-intc",
	2193	"amlogic,meson-gpio-intc";
	2194	reg = <0x0 0xf080 0x0 0x10>;
	2195	interrupt-controller;
	2196	#interrupt-cells = <2>;
	2197	amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
	2198	};
	2199
	2200	pwm_ef: pwm@19000 {
	2201	compatible = "amlogic,meson-g12a-ee-pwm";
	2202	reg = <0x0 0x19000 0x0 0x20>;
	2203	#pwm-cells = <3>;
	2204	status = "disabled";
	2205	};
	2206
	2207	pwm_cd: pwm@1a000 {
	2208	compatible = "amlogic,meson-g12a-ee-pwm";
	2209	reg = <0x0 0x1a000 0x0 0x20>;
	2210	#pwm-cells = <3>;
	2211	status = "disabled";
	2212	};
	2213
	2214	pwm_ab: pwm@1b000 {
	2215	compatible = "amlogic,meson-g12a-ee-pwm";
	2216	reg = <0x0 0x1b000 0x0 0x20>;
	2217	#pwm-cells = <3>;
	2218	status = "disabled";
	2219	};
	2220
	2221	i2c3: i2c@1c000 {
	2222	compatible = "amlogic,meson-axg-i2c";
	2223	status = "disabled";
	2224	reg = <0x0 0x1c000 0x0 0x20>;
	2225	interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
	2226	#address-cells = <1>;
	2227	#size-cells = <0>;
	2228	clocks = <&clkc CLKID_I2C>;
	2229	};
	2230
	2231	i2c2: i2c@1d000 {
	2232	compatible = "amlogic,meson-axg-i2c";
	2233	status = "disabled";
	2234	reg = <0x0 0x1d000 0x0 0x20>;
	2235	interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
	2236	#address-cells = <1>;
	2237	#size-cells = <0>;
	2238	clocks = <&clkc CLKID_I2C>;
	2239	};
	2240
	2241	i2c1: i2c@1e000 {
	2242	compatible = "amlogic,meson-axg-i2c";
	2243	status = "disabled";
	2244	reg = <0x0 0x1e000 0x0 0x20>;
	2245	interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
	2246	#address-cells = <1>;
	2247	#size-cells = <0>;
	2248	clocks = <&clkc CLKID_I2C>;
	2249	};
	2250
	2251	i2c0: i2c@1f000 {
	2252	compatible = "amlogic,meson-axg-i2c";
	2253	status = "disabled";
	2254	reg = <0x0 0x1f000 0x0 0x20>;
	2255	interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
	2256	#address-cells = <1>;
	2257	#size-cells = <0>;
	2258	clocks = <&clkc CLKID_I2C>;
	2259	};
	2260
	2261	clk_msr: clock-measure@18000 {
	2262	compatible = "amlogic,meson-g12a-clk-measure";
	2263	reg = <0x0 0x18000 0x0 0x10>;
	2264	};
	2265
	2266	uart_C: serial@22000 {
	2267	compatible = "amlogic,meson-gx-uart";
	2268	reg = <0x0 0x22000 0x0 0x18>;
	2269	interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
	2270	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
	2271	clock-names = "xtal", "pclk", "baud";
	2272	status = "disabled";
	2273	};
	2274
	2275	uart_B: serial@23000 {
	2276	compatible = "amlogic,meson-gx-uart";
	2277	reg = <0x0 0x23000 0x0 0x18>;
	2278	interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
	2279	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
	2280	clock-names = "xtal", "pclk", "baud";
	2281	status = "disabled";
	2282	};
	2283
	2284	uart_A: serial@24000 {
	2285	compatible = "amlogic,meson-gx-uart";
	2286	reg = <0x0 0x24000 0x0 0x18>;
	2287	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	2288	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	2289	clock-names = "xtal", "pclk", "baud";
	2290	status = "disabled";
	2291	};
	2292	};
	2293
	2294	sd_emmc_a: sd@ffe03000 {
	2295	compatible = "amlogic,meson-axg-mmc";
	2296	reg = <0x0 0xffe03000 0x0 0x800>;
	2297	interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
	2298	status = "disabled";
	2299	clocks = <&clkc CLKID_SD_EMMC_A>,
	2300	<&clkc CLKID_SD_EMMC_A_CLK0>,
	2301	<&clkc CLKID_FCLK_DIV2>;
	2302	clock-names = "core", "clkin0", "clkin1";
	2303	resets = <&reset RESET_SD_EMMC_A>;
	2304	};
	2305
	2306	sd_emmc_b: sd@ffe05000 {
	2307	compatible = "amlogic,meson-axg-mmc";
	2308	reg = <0x0 0xffe05000 0x0 0x800>;
	2309	interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
	2310	status = "disabled";
	2311	clocks = <&clkc CLKID_SD_EMMC_B>,
	2312	<&clkc CLKID_SD_EMMC_B_CLK0>,
	2313	<&clkc CLKID_FCLK_DIV2>;
	2314	clock-names = "core", "clkin0", "clkin1";
	2315	resets = <&reset RESET_SD_EMMC_B>;
	2316	};
	2317
	2318	sd_emmc_c: mmc@ffe07000 {
	2319	compatible = "amlogic,meson-axg-mmc";
	2320	reg = <0x0 0xffe07000 0x0 0x800>;
	2321	interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
	2322	status = "disabled";
	2323	clocks = <&clkc CLKID_SD_EMMC_C>,
	2324	<&clkc CLKID_SD_EMMC_C_CLK0>,
	2325	<&clkc CLKID_FCLK_DIV2>;
	2326	clock-names = "core", "clkin0", "clkin1";
	2327	resets = <&reset RESET_SD_EMMC_C>;
	2328	};
	2329
	2330	usb: usb@ffe09000 {
	2331	status = "disabled";
	2332	compatible = "amlogic,meson-g12a-usb-ctrl";
	2333	reg = <0x0 0xffe09000 0x0 0xa0>;
	2334	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	2335	#address-cells = <2>;
	2336	#size-cells = <2>;
	2337	ranges;
	2338
	2339	clocks = <&clkc CLKID_USB>;
	2340	resets = <&reset RESET_USB>;
	2341
	2342	dr_mode = "otg";
	2343
	2344	phys = <&usb2_phy0>, <&usb2_phy1>,
	2345	<&usb3_pcie_phy PHY_TYPE_USB3>;
	2346	phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
	2347
	2348	dwc2: usb@ff400000 {
	2349	compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
	2350	reg = <0x0 0xff400000 0x0 0x40000>;
	2351	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	2352	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
	2353	clock-names = "ddr";
	2354	phys = <&usb2_phy1>;
	2355	phy-names = "usb2-phy";
	2356	dr_mode = "peripheral";
	2357	g-rx-fifo-size = <192>;
	2358	g-np-tx-fifo-size = <128>;
	2359	g-tx-fifo-size = <128 128 16 16 16>;
	2360	};
	2361
	2362	dwc3: usb@ff500000 {
	2363	compatible = "snps,dwc3";
	2364	reg = <0x0 0xff500000 0x0 0x100000>;
	2365	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	2366	dr_mode = "host";
	2367	snps,dis_u2_susphy_quirk;
	2368	snps,quirk-frame-length-adjustment;
	2369	};
	2370	};
	2371
	2372	mali: gpu@ffe40000 {
	2373	compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
	2374	reg = <0x0 0xffe40000 0x0 0x40000>;
	2375	interrupt-parent = <&gic>;
	2376	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	2377	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	2378	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
	2379	interrupt-names = "gpu", "mmu", "job";
	2380	clocks = <&clkc CLKID_MALI>;
	2381	resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
	2382
	2383	/*
	2384	* Mali clocking is provided by two identical clock paths
	2385	* MALI_0 and MALI_1 muxed to a single clock by a glitch
	2386	* free mux to safely change frequency while running.
	2387	*/
	2388	assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
	2389	<&clkc CLKID_MALI_0>,
	2390	<&clkc CLKID_MALI>; /* Glitch free mux */
	2391	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
	2392	<0>, /* Do Nothing */
	2393	<&clkc CLKID_MALI_0>;
	2394	assigned-clock-rates = <0>, /* Do Nothing */
	2395	<800000000>,
	2396	<0>; /* Do Nothing */
	2397	};
	2398	};
	2399
	2400	timer {
	2401	compatible = "arm,armv8-timer";
	2402	interrupts = <GIC_PPI 13
	2403	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	2404	<GIC_PPI 14
	2405	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	2406	<GIC_PPI 11
	2407	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
	2408	<GIC_PPI 10
	2409	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>;
	2410	arm,no-tick-in-suspend;
	2411	};
	2412
	2413	xtal: xtal-clk {
	2414	compatible = "fixed-clock";
	2415	clock-frequency = <24000000>;
	2416	clock-output-names = "xtal";
	2417	#clock-cells = <0>;
	2418	};
	2419
	2420	};

arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts+61−0

@@ -129,6 +129,25 @@ · 128 unmodified lines
129	enable-active-high;	129	enable-active-high;
130	};	130	};
131		131
		132	vddcpu: regulator-vddcpu {
		133	/*
		134	* SY8120B1ABC DC/DC Regulator.
		135	*/
		136	compatible = "pwm-regulator";
		137
		138	regulator-name = "VDDCPU";
		139	regulator-min-microvolt = <721000>;
		140	regulator-max-microvolt = <1022000>;
		141
		142	vin-supply = <&dc_in>;
		143
		144	pwms = <&pwm_AO_cd 1 1250 0>;
		145	pwm-dutycycle-range = <100 0>;
		146
		147	regulator-boot-on;
		148	regulator-always-on;
		149	};
		150
132	vddio_ao1v8: regulator-vddio_ao1v8 {	151	vddio_ao1v8: regulator-vddio_ao1v8 {
133	compatible = "regulator-fixed";	152	compatible = "regulator-fixed";
134	regulator-name = "VDDIO_AO1V8";	153	regulator-name = "VDDIO_AO1V8";
@@ -297,6 +316,34 @@ · 162 unmodified lines
297	status = "okay";	316	status = "okay";
298	};	317	};
299		318
		319	&cpu0 {
		320	cpu-supply = <&vddcpu>;
		321	operating-points-v2 = <&cpu_opp_table>;
		322	clocks = <&clkc CLKID_CPU_CLK>;
		323	clock-latency = <50000>;
		324	};
		325
		326	&cpu1 {
		327	cpu-supply = <&vddcpu>;
		328	operating-points-v2 = <&cpu_opp_table>;
		329	clocks = <&clkc CLKID_CPU_CLK>;
		330	clock-latency = <50000>;
		331	};
		332
		333	&cpu2 {
		334	cpu-supply = <&vddcpu>;
		335	operating-points-v2 = <&cpu_opp_table>;
		336	clocks = <&clkc CLKID_CPU_CLK>;
		337	clock-latency = <50000>;
		338	};
		339
		340	&cpu3 {
		341	cpu-supply = <&vddcpu>;
		342	operating-points-v2 = <&cpu_opp_table>;
		343	clocks = <&clkc CLKID_CPU_CLK>;
		344	clock-latency = <50000>;
		345	};
		346
300	&cvbs_vdac_port {	347	&cvbs_vdac_port {
301	cvbs_vdac_out: endpoint {	348	cvbs_vdac_out: endpoint {
302	remote-endpoint = <&cvbs_connector_in>;	349	remote-endpoint = <&cvbs_connector_in>;
@@ -339,6 +386,20 @@ · 36 unmodified lines
339	pinctrl-names = "default";	386	pinctrl-names = "default";
340	};	387	};
341		388
		389	&ir {
		390	status = "okay";
		391	pinctrl-0 = <&remote_input_ao_pins>;
		392	pinctrl-names = "default";
		393	};
		394
		395	&pwm_AO_cd {
		396	pinctrl-0 = <&pwm_ao_d_e_pins>;
		397	pinctrl-names = "default";
		398	clocks = <&xtal>;
		399	clock-names = "clkin1";
		400	status = "okay";
		401	};
		402
342	&pwm_ef {	403	&pwm_ef {
343	status = "okay";	404	status = "okay";
344	pinctrl-0 = <&pwm_e_pins>;	405	pinctrl-0 = <&pwm_e_pins>;

arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts+54−0

@@ -129,6 +129,24 @@ · 128 unmodified lines
129	regulator-always-on;	129	regulator-always-on;
130	};	130	};
131		131
		132	vddcpu: regulator-vddcpu {
		133	/*
		134	* MP8756GD Regulator.
		135	*/
		136	compatible = "pwm-regulator";
		137
		138	regulator-name = "VDDCPU";
		139	regulator-min-microvolt = <721000>;
		140	regulator-max-microvolt = <1022000>;
		141
		142	vin-supply = <&main_12v>;
		143
		144	pwms = <&pwm_AO_cd 1 1250 0>;
		145	pwm-dutycycle-range = <100 0>;
		146
		147	regulator-boot-on;
		148	regulator-always-on;
		149	};
132	};	150	};
133		151
134	&cec_AO {	152	&cec_AO {
@@ -145,6 +163,34 @@ · 10 unmodified lines
145	hdmi-phandle = <&hdmi_tx>;	163	hdmi-phandle = <&hdmi_tx>;
146	};	164	};
147		165
		166	&cpu0 {
		167	cpu-supply = <&vddcpu>;
		168	operating-points-v2 = <&cpu_opp_table>;
		169	clocks = <&clkc CLKID_CPU_CLK>;
		170	clock-latency = <50000>;
		171	};
		172
		173	&cpu1 {
		174	cpu-supply = <&vddcpu>;
		175	operating-points-v2 = <&cpu_opp_table>;
		176	clocks = <&clkc CLKID_CPU_CLK>;
		177	clock-latency = <50000>;
		178	};
		179
		180	&cpu2 {
		181	cpu-supply = <&vddcpu>;
		182	operating-points-v2 = <&cpu_opp_table>;
		183	clocks = <&clkc CLKID_CPU_CLK>;
		184	clock-latency = <50000>;
		185	};
		186
		187	&cpu3 {
		188	cpu-supply = <&vddcpu>;
		189	operating-points-v2 = <&cpu_opp_table>;
		190	clocks = <&clkc CLKID_CPU_CLK>;
		191	clock-latency = <50000>;
		192	};
		193
148	&cvbs_vdac_port {	194	&cvbs_vdac_port {
149	cvbs_vdac_out: endpoint {	195	cvbs_vdac_out: endpoint {
150	remote-endpoint = <&cvbs_connector_in>;	196	remote-endpoint = <&cvbs_connector_in>;
@@ -197,6 +243,14 @@ · 46 unmodified lines
197	pinctrl-names = "default";	243	pinctrl-names = "default";
198	};	244	};
199		245
		246	&pwm_AO_cd {
		247	pinctrl-0 = <&pwm_ao_d_e_pins>;
		248	pinctrl-names = "default";
		249	clocks = <&xtal>;
		250	clock-names = "clkin1";
		251	status = "okay";
		252	};
		253
200	/* SD card */	254	/* SD card */
201	&sd_emmc_b {	255	&sd_emmc_b {
202	status = "okay";	256	status = "okay";

arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts+52−0

@@ -132,6 +132,22 @@ · 131 unmodified lines
132	regulator-always-on;	132	regulator-always-on;
133	};	133	};
134		134
		135	vddcpu: regulator-vddcpu {
		136	compatible = "pwm-regulator";
		137
		138	regulator-name = "VDDCPU";
		139	regulator-min-microvolt = <721000>;
		140	regulator-max-microvolt = <1022000>;
		141
		142	vin-supply = <&dc_in>;
		143
		144	pwms = <&pwm_AO_cd 1 1250 0>;
		145	pwm-dutycycle-range = <100 0>;
		146
		147	regulator-boot-on;
		148	regulator-always-on;
		149	};
		150
135	sound {	151	sound {
136	compatible = "amlogic,axg-sound-card";	152	compatible = "amlogic,axg-sound-card";
137	model = "G12A-X96-MAX";	153	model = "G12A-X96-MAX";
@@ -242,6 +258,34 @@ · 104 unmodified lines
242	status = "okay";	258	status = "okay";
243	};	259	};
244		260
		261	&cpu0 {
		262	cpu-supply = <&vddcpu>;
		263	operating-points-v2 = <&cpu_opp_table>;
		264	clocks = <&clkc CLKID_CPU_CLK>;
		265	clock-latency = <50000>;
		266	};
		267
		268	&cpu1 {
		269	cpu-supply = <&vddcpu>;
		270	operating-points-v2 = <&cpu_opp_table>;
		271	clocks = <&clkc CLKID_CPU_CLK>;
		272	clock-latency = <50000>;
		273	};
		274
		275	&cpu2 {
		276	cpu-supply = <&vddcpu>;
		277	operating-points-v2 = <&cpu_opp_table>;
		278	clocks = <&clkc CLKID_CPU_CLK>;
		279	clock-latency = <50000>;
		280	};
		281
		282	&cpu3 {
		283	cpu-supply = <&vddcpu>;
		284	operating-points-v2 = <&cpu_opp_table>;
		285	clocks = <&clkc CLKID_CPU_CLK>;
		286	clock-latency = <50000>;
		287	};
		288
245	&cvbs_vdac_port {	289	&cvbs_vdac_port {
246	cvbs_vdac_out: endpoint {	290	cvbs_vdac_out: endpoint {
247	remote-endpoint = <&cvbs_connector_in>;	291	remote-endpoint = <&cvbs_connector_in>;
@@ -279,6 +323,14 @@ · 31 unmodified lines
279	pinctrl-names = "default";	323	pinctrl-names = "default";
280	};	324	};
281		325
		326	&pwm_AO_cd {
		327	pinctrl-0 = <&pwm_ao_d_e_pins>;
		328	pinctrl-names = "default";
		329	clocks = <&xtal>;
		330	clock-names = "clkin1";
		331	status = "okay";
		332	};
		333
282	&ext_mdio {	334	&ext_mdio {
283	external_phy: ethernet-phy@0 {	335	external_phy: ethernet-phy@0 {
284	/* Realtek RTL8211F (0x001cc916) */	336	/* Realtek RTL8211F (0x001cc916) */

arch/arm64/boot/dts/amlogic/meson-g12a.dtsi+40−2377

@@ -3,56 +3,11 @@ · 2 unmodified lines
3	* Copyright (c) 2018 Amlogic, Inc. All rights reserved.	3	* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4	*/	4	*/
5		5
6	#include <dt-bindings/phy/phy.h>	6	#include "meson-g12-common.dtsi"
7	#include <dt-bindings/gpio/gpio.h>
8	#include <dt-bindings/clock/axg-audio-clkc.h>
9	#include <dt-bindings/clock/g12a-clkc.h>
10	#include <dt-bindings/clock/g12a-aoclkc.h>
11	#include <dt-bindings/interrupt-controller/irq.h>
12	#include <dt-bindings/interrupt-controller/arm-gic.h>
13	#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14	#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
15		7
16	/ {	8	/ {
17	compatible = "amlogic,g12a";	9	compatible = "amlogic,g12a";
18		10
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	tdmif_a: audio-controller-0 {
24	compatible = "amlogic,axg-tdm-iface";
25	#sound-dai-cells = <0>;
26	sound-name-prefix = "TDM_A";
27	clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28	<&clkc_audio AUD_CLKID_MST_A_SCLK>,
29	<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30	clock-names = "mclk", "sclk", "lrclk";
31	status = "disabled";
32	};
33
34	tdmif_b: audio-controller-1 {
35	compatible = "amlogic,axg-tdm-iface";
36	#sound-dai-cells = <0>;
37	sound-name-prefix = "TDM_B";
38	clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39	<&clkc_audio AUD_CLKID_MST_B_SCLK>,
40	<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41	clock-names = "mclk", "sclk", "lrclk";
42	status = "disabled";
43	};
44
45	tdmif_c: audio-controller-2 {
46	compatible = "amlogic,axg-tdm-iface";
47	#sound-dai-cells = <0>;
48	sound-name-prefix = "TDM_C";
49	clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50	<&clkc_audio AUD_CLKID_MST_C_SCLK>,
51	<&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52	clock-names = "mclk", "sclk", "lrclk";
53	status = "disabled";
54	};
55
56	cpus {	11	cpus {
57	#address-cells = <0x2>;	12	#address-cells = <0x2>;
58	#size-cells = <0x0>;	13	#size-cells = <0x0>;
@@ -94,2359 +49,67 @@ · 35 unmodified lines
94	};	49	};
95	};	50	};
96		51
97	efuse: efuse {	52	cpu_opp_table: opp-table {
98	compatible = "amlogic,meson-gxbb-efuse";	53	compatible = "operating-points-v2";
99	clocks = <&clkc CLKID_EFUSE>;	54	opp-shared;
100	#address-cells = <1>;
101	#size-cells = <1>;
102	read-only;
103	};
104		55
105	psci {	56	opp-100000000 {
106	compatible = "arm,psci-1.0";	57	opp-hz = /bits/ 64 <100000000>;
107	method = "smc";	58	opp-microvolt = <731000>;
108	};
109
110	reserved-memory {
111	#address-cells = <2>;
112	#size-cells = <2>;
113	ranges;
114
115	/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
116	secmon_reserved: secmon@5000000 {
117	reg = <0x0 0x05000000 0x0 0x300000>;
118	no-map;
119	};	59	};
120		60
121	linux,cma {	61	opp-250000000 {
122	compatible = "shared-dma-pool";	62	opp-hz = /bits/ 64 <250000000>;
123	reusable;	63	opp-microvolt = <731000>;
124	size = <0x0 0x10000000>;
125	alignment = <0x0 0x400000>;
126	linux,cma-default;
127	};	64	};
128	};
129
130	sm: secure-monitor {
131	compatible = "amlogic,meson-gxbb-sm";
132	};
133
134	soc {
135	compatible = "simple-bus";
136	#address-cells = <2>;
137	#size-cells = <2>;
138	ranges;
139		65
140	ethmac: ethernet@ff3f0000 {	66	opp-500000000 {
141	compatible = "amlogic,meson-axg-dwmac",	67	opp-hz = /bits/ 64 <500000000>;
142	"snps,dwmac-3.70a",	68	opp-microvolt = <731000>;
143	"snps,dwmac";
144	reg = <0x0 0xff3f0000 0x0 0x10000
145	0x0 0xff634540 0x0 0x8>;
146	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
147	interrupt-names = "macirq";
148	clocks = <&clkc CLKID_ETH>,
149	<&clkc CLKID_FCLK_DIV2>,
150	<&clkc CLKID_MPLL2>;
151	clock-names = "stmmaceth", "clkin0", "clkin1";
152	status = "disabled";
153
154	mdio0: mdio {
155	#address-cells = <1>;
156	#size-cells = <0>;
157	compatible = "snps,dwmac-mdio";
158	};
159	};	69	};
160		70
161	apb: bus@ff600000 {	71	opp-667000000 {
162	compatible = "simple-bus";	72	opp-hz = /bits/ 64 <666666666>;
163	reg = <0x0 0xff600000 0x0 0x200000>;	73	opp-microvolt = <731000>;
164	#address-cells = <2>;
165	#size-cells = <2>;
166	ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
167
168	hdmi_tx: hdmi-tx@0 {
169	compatible = "amlogic,meson-g12a-dw-hdmi";
170	reg = <0x0 0x0 0x0 0x10000>;
171	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
172	resets = <&reset RESET_HDMITX_CAPB3>,
173	<&reset RESET_HDMITX_PHY>,
174	<&reset RESET_HDMITX>;
175	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
176	clocks = <&clkc CLKID_HDMI>,
177	<&clkc CLKID_HTX_PCLK>,
178	<&clkc CLKID_VPU_INTR>;
179	clock-names = "isfr", "iahb", "venci";
180	#address-cells = <1>;
181	#size-cells = <0>;
182	#sound-dai-cells = <0>;
183	status = "disabled";
184
185	/* VPU VENC Input */
186	hdmi_tx_venc_port: port@0 {
187	reg = <0>;
188
189	hdmi_tx_in: endpoint {
190	remote-endpoint = <&hdmi_tx_out>;
191	};
192	};
193
194	/* TMDS Output */
195	hdmi_tx_tmds_port: port@1 {
196	reg = <1>;
197	};
198	};
199
200	apb_efuse: bus@30000 {
201	compatible = "simple-bus";
202	reg = <0x0 0x30000 0x0 0x2000>;
203	#address-cells = <2>;
204	#size-cells = <2>;
205	ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
206
207	hwrng: rng@218 {
208	compatible = "amlogic,meson-rng";
209	reg = <0x0 0x218 0x0 0x4>;
210	};
211	};
212
213	periphs: bus@34400 {
214	compatible = "simple-bus";
215	reg = <0x0 0x34400 0x0 0x400>;
216	#address-cells = <2>;
217	#size-cells = <2>;
218	ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
219
220	periphs_pinctrl: pinctrl@40 {
221	compatible = "amlogic,meson-g12a-periphs-pinctrl";
222	#address-cells = <2>;
223	#size-cells = <2>;
224	ranges;
225
226	gpio: bank@40 {
227	reg = <0x0 0x40 0x0 0x4c>,
228	<0x0 0xe8 0x0 0x18>,
229	<0x0 0x120 0x0 0x18>,
230	<0x0 0x2c0 0x0 0x40>,
231	<0x0 0x340 0x0 0x1c>;
232	reg-names = "gpio",
233	"pull",
234	"pull-enable",
235	"mux",
236	"ds";
237	gpio-controller;
238	#gpio-cells = <2>;
239	gpio-ranges = <&periphs_pinctrl 0 0 86>;
240	};
241
242	cec_ao_a_h_pins: cec_ao_a_h {
243	mux {
244	groups = "cec_ao_a_h";
245	function = "cec_ao_a_h";
246	bias-disable;
247	};
248	};
249
250	cec_ao_b_h_pins: cec_ao_b_h {
251	mux {
252	groups = "cec_ao_b_h";
253	function = "cec_ao_b_h";
254	bias-disable;
255	};
256	};
257
258	emmc_pins: emmc {
259	mux-0 {
260	groups = "emmc_nand_d0",
261	"emmc_nand_d1",
262	"emmc_nand_d2",
263	"emmc_nand_d3",
264	"emmc_nand_d4",
265	"emmc_nand_d5",
266	"emmc_nand_d6",
267	"emmc_nand_d7",
268	"emmc_cmd";
269	function = "emmc";
270	bias-pull-up;
271	drive-strength-microamp = <4000>;
272	};
273
274	mux-1 {
275	groups = "emmc_clk";
276	function = "emmc";
277	bias-disable;
278	drive-strength-microamp = <4000>;
279	};
280	};
281
282	emmc_ds_pins: emmc-ds {
283	mux {
284	groups = "emmc_nand_ds";
285	function = "emmc";
286	bias-pull-down;
287	drive-strength-microamp = <4000>;
288	};
289	};
290
291	emmc_clk_gate_pins: emmc_clk_gate {
292	mux {
293	groups = "BOOT_8";
294	function = "gpio_periphs";
295	bias-pull-down;
296	drive-strength-microamp = <4000>;
297	};
298	};
299
300	hdmitx_ddc_pins: hdmitx_ddc {
301	mux {
302	groups = "hdmitx_sda",
303	"hdmitx_sck";
304	function = "hdmitx";
305	bias-disable;
306	drive-strength-microamp = <4000>;
307	};
308	};
309
310	hdmitx_hpd_pins: hdmitx_hpd {
311	mux {
312	groups = "hdmitx_hpd_in";
313	function = "hdmitx";
314	bias-disable;
315	};
316	};
317
318
319	i2c0_sda_c_pins: i2c0-sda-c {
320	mux {
321	groups = "i2c0_sda_c";
322	function = "i2c0";
323	bias-disable;
324	drive-strength-microamp = <3000>;
325
326	};
327	};
328
329	i2c0_sck_c_pins: i2c0-sck-c {
330	mux {
331	groups = "i2c0_sck_c";
332	function = "i2c0";
333	bias-disable;
334	drive-strength-microamp = <3000>;
335	};
336	};
337
338	i2c0_sda_z0_pins: i2c0-sda-z0 {
339	mux {
340	groups = "i2c0_sda_z0";
341	function = "i2c0";
342	bias-disable;
343	drive-strength-microamp = <3000>;
344	};
345	};
346
347	i2c0_sck_z1_pins: i2c0-sck-z1 {
348	mux {
349	groups = "i2c0_sck_z1";
350	function = "i2c0";
351	bias-disable;
352	drive-strength-microamp = <3000>;
353	};
354	};
355
356	i2c0_sda_z7_pins: i2c0-sda-z7 {
357	mux {
358	groups = "i2c0_sda_z7";
359	function = "i2c0";
360	bias-disable;
361	drive-strength-microamp = <3000>;
362	};
363	};
364
365	i2c0_sda_z8_pins: i2c0-sda-z8 {
366	mux {
367	groups = "i2c0_sda_z8";
368	function = "i2c0";
369	bias-disable;
370	drive-strength-microamp = <3000>;
371	};
372	};
373
374	i2c1_sda_x_pins: i2c1-sda-x {
375	mux {
376	groups = "i2c1_sda_x";
377	function = "i2c1";
378	bias-disable;
379	drive-strength-microamp = <3000>;
380	};
381	};
382
383	i2c1_sck_x_pins: i2c1-sck-x {
384	mux {
385	groups = "i2c1_sck_x";
386	function = "i2c1";
387	bias-disable;
388	drive-strength-microamp = <3000>;
389	};
390	};
391
392	i2c1_sda_h2_pins: i2c1-sda-h2 {
393	mux {
394	groups = "i2c1_sda_h2";
395	function = "i2c1";
396	bias-disable;
397	drive-strength-microamp = <3000>;
398	};
399	};
400
401	i2c1_sck_h3_pins: i2c1-sck-h3 {
402	mux {
403	groups = "i2c1_sck_h3";
404	function = "i2c1";
405	bias-disable;
406	drive-strength-microamp = <3000>;
407	};
408	};
409
410	i2c1_sda_h6_pins: i2c1-sda-h6 {
411	mux {
412	groups = "i2c1_sda_h6";
413	function = "i2c1";
414	bias-disable;
415	drive-strength-microamp = <3000>;
416	};
417	};
418
419	i2c1_sck_h7_pins: i2c1-sck-h7 {
420	mux {
421	groups = "i2c1_sck_h7";
422	function = "i2c1";
423	bias-disable;
424	drive-strength-microamp = <3000>;
425	};
426	};
427
428	i2c2_sda_x_pins: i2c2-sda-x {
429	mux {
430	groups = "i2c2_sda_x";
431	function = "i2c2";
432	bias-disable;
433	drive-strength-microamp = <3000>;
434	};
435	};
436
437	i2c2_sck_x_pins: i2c2-sck-x {
438	mux {
439	groups = "i2c2_sck_x";
440	function = "i2c2";
441	bias-disable;
442	drive-strength-microamp = <3000>;
443	};
444	};
445
446	i2c2_sda_z_pins: i2c2-sda-z {
447	mux {
448	groups = "i2c2_sda_z";
449	function = "i2c2";
450	bias-disable;
451	drive-strength-microamp = <3000>;
452	};
453	};
454
455	i2c2_sck_z_pins: i2c2-sck-z {
456	mux {
457	groups = "i2c2_sck_z";
458	function = "i2c2";
459	bias-disable;
460	drive-strength-microamp = <3000>;
461	};
462	};
463
464	i2c3_sda_h_pins: i2c3-sda-h {
465	mux {
466	groups = "i2c3_sda_h";
467	function = "i2c3";
468	bias-disable;
469	drive-strength-microamp = <3000>;
470	};
471	};
472
473	i2c3_sck_h_pins: i2c3-sck-h {
474	mux {
475	groups = "i2c3_sck_h";
476	function = "i2c3";
477	bias-disable;
478	drive-strength-microamp = <3000>;
479	};
480	};
481
482	i2c3_sda_a_pins: i2c3-sda-a {
483	mux {
484	groups = "i2c3_sda_a";
485	function = "i2c3";
486	bias-disable;
487	drive-strength-microamp = <3000>;
488	};
489	};
490
491	i2c3_sck_a_pins: i2c3-sck-a {
492	mux {
493	groups = "i2c3_sck_a";
494	function = "i2c3";
495	bias-disable;
496	drive-strength-microamp = <3000>;
497	};
498	};
499
500	mclk0_a_pins: mclk0-a {
501	mux {
502	groups = "mclk0_a";
503	function = "mclk0";
504	bias-disable;
505	drive-strength-microamp = <3000>;
506	};
507	};
508
509	mclk1_a_pins: mclk1-a {
510	mux {
511	groups = "mclk1_a";
512	function = "mclk1";
513	bias-disable;
514	drive-strength-microamp = <3000>;
515	};
516	};
517
518	mclk1_x_pins: mclk1-x {
519	mux {
520	groups = "mclk1_x";
521	function = "mclk1";
522	bias-disable;
523	drive-strength-microamp = <3000>;
524	};
525	};
526
527	mclk1_z_pins: mclk1-z {
528	mux {
529	groups = "mclk1_z";
530	function = "mclk1";
531	bias-disable;
532	drive-strength-microamp = <3000>;
533	};
534	};
535
536	pdm_din0_a_pins: pdm-din0-a {
537	mux {
538	groups = "pdm_din0_a";
539	function = "pdm";
540	bias-disable;
541	};
542	};
543
544	pdm_din0_c_pins: pdm-din0-c {
545	mux {
546	groups = "pdm_din0_c";
547	function = "pdm";
548	bias-disable;
549	};
550	};
551
552	pdm_din0_x_pins: pdm-din0-x {
553	mux {
554	groups = "pdm_din0_x";
555	function = "pdm";
556	bias-disable;
557	};
558	};
559
560	pdm_din0_z_pins: pdm-din0-z {
561	mux {
562	groups = "pdm_din0_z";
563	function = "pdm";
564	bias-disable;
565	};
566	};
567
568	pdm_din1_a_pins: pdm-din1-a {
569	mux {
570	groups = "pdm_din1_a";
571	function = "pdm";
572	bias-disable;
573	};
574	};
575
576	pdm_din1_c_pins: pdm-din1-c {
577	mux {
578	groups = "pdm_din1_c";
579	function = "pdm";
580	bias-disable;
581	};
582	};
583
584	pdm_din1_x_pins: pdm-din1-x {
585	mux {
586	groups = "pdm_din1_x";
587	function = "pdm";
588	bias-disable;
589	};
590	};
591
592	pdm_din1_z_pins: pdm-din1-z {
593	mux {
594	groups = "pdm_din1_z";
595	function = "pdm";
596	bias-disable;
597	};
598	};
599
600	pdm_din2_a_pins: pdm-din2-a {
601	mux {
602	groups = "pdm_din2_a";
603	function = "pdm";
604	bias-disable;
605	};
606	};
607
608	pdm_din2_c_pins: pdm-din2-c {
609	mux {
610	groups = "pdm_din2_c";
611	function = "pdm";
612	bias-disable;
613	};
614	};
615
616	pdm_din2_x_pins: pdm-din2-x {
617	mux {
618	groups = "pdm_din2_x";
619	function = "pdm";
620	bias-disable;
621	};
622	};
623
624	pdm_din2_z_pins: pdm-din2-z {
625	mux {
626	groups = "pdm_din2_z";
627	function = "pdm";
628	bias-disable;
629	};
630	};
631
632	pdm_din3_a_pins: pdm-din3-a {
633	mux {
634	groups = "pdm_din3_a";
635	function = "pdm";
636	bias-disable;
637	};
638	};
639
640	pdm_din3_c_pins: pdm-din3-c {
641	mux {
642	groups = "pdm_din3_c";
643	function = "pdm";
644	bias-disable;
645	};
646	};
647
648	pdm_din3_x_pins: pdm-din3-x {
649	mux {
650	groups = "pdm_din3_x";
651	function = "pdm";
652	bias-disable;
653	};
654	};
655
656	pdm_din3_z_pins: pdm-din3-z {
657	mux {
658	groups = "pdm_din3_z";
659	function = "pdm";
660	bias-disable;
661	};
662	};
663
664	pdm_dclk_a_pins: pdm-dclk-a {
665	mux {
666	groups = "pdm_dclk_a";
667	function = "pdm";
668	bias-disable;
669	drive-strength-microamp = <500>;
670	};
671	};
672
673	pdm_dclk_c_pins: pdm-dclk-c {
674	mux {
675	groups = "pdm_dclk_c";
676	function = "pdm";
677	bias-disable;
678	drive-strength-microamp = <500>;
679	};
680	};
681
682	pdm_dclk_x_pins: pdm-dclk-x {
683	mux {
684	groups = "pdm_dclk_x";
685	function = "pdm";
686	bias-disable;
687	drive-strength-microamp = <500>;
688	};
689	};
690
691	pdm_dclk_z_pins: pdm-dclk-z {
692	mux {
693	groups = "pdm_dclk_z";
694	function = "pdm";
695	bias-disable;
696	drive-strength-microamp = <500>;
697	};
698	};
699
700	pwm_a_pins: pwm-a {
701	mux {
702	groups = "pwm_a";
703	function = "pwm_a";
704	bias-disable;
705	};
706	};
707
708	pwm_b_x7_pins: pwm-b-x7 {
709	mux {
710	groups = "pwm_b_x7";
711	function = "pwm_b";
712	bias-disable;
713	};
714	};
715
716	pwm_b_x19_pins: pwm-b-x19 {
717	mux {
718	groups = "pwm_b_x19";
719	function = "pwm_b";
720	bias-disable;
721	};
722	};
723
724	pwm_c_c_pins: pwm-c-c {
725	mux {
726	groups = "pwm_c_c";
727	function = "pwm_c";
728	bias-disable;
729	};
730	};
731
732	pwm_c_x5_pins: pwm-c-x5 {
733	mux {
734	groups = "pwm_c_x5";
735	function = "pwm_c";
736	bias-disable;
737	};
738	};
739
740	pwm_c_x8_pins: pwm-c-x8 {
741	mux {
742	groups = "pwm_c_x8";
743	function = "pwm_c";
744	bias-disable;
745	};
746	};
747
748	pwm_d_x3_pins: pwm-d-x3 {
749	mux {
750	groups = "pwm_d_x3";
751	function = "pwm_d";
752	bias-disable;
753	};
754	};
755
756	pwm_d_x6_pins: pwm-d-x6 {
757	mux {
758	groups = "pwm_d_x6";
759	function = "pwm_d";
760	bias-disable;
761	};
762	};
763
764	pwm_e_pins: pwm-e {
765	mux {
766	groups = "pwm_e";
767	function = "pwm_e";
768	bias-disable;
769	};
770	};
771
772	pwm_f_x_pins: pwm-f-x {
773	mux {
774	groups = "pwm_f_x";
775	function = "pwm_f";
776	bias-disable;
777	};
778	};
779
780	pwm_f_h_pins: pwm-f-h {
781	mux {
782	groups = "pwm_f_h";
783	function = "pwm_f";
784	bias-disable;
785	};
786	};
787
788	sdcard_c_pins: sdcard_c {
789	mux-0 {
790	groups = "sdcard_d0_c",
791	"sdcard_d1_c",
792	"sdcard_d2_c",
793	"sdcard_d3_c",
794	"sdcard_cmd_c";
795	function = "sdcard";
796	bias-pull-up;
797	drive-strength-microamp = <4000>;
798	};
799
800	mux-1 {
801	groups = "sdcard_clk_c";
802	function = "sdcard";
803	bias-disable;
804	drive-strength-microamp = <4000>;
805	};
806	};
807
808	sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
809	mux {
810	groups = "GPIOC_4";
811	function = "gpio_periphs";
812	bias-pull-down;
813	drive-strength-microamp = <4000>;
814	};
815	};
816
817	sdcard_z_pins: sdcard_z {
818	mux-0 {
819	groups = "sdcard_d0_z",
820	"sdcard_d1_z",
821	"sdcard_d2_z",
822	"sdcard_d3_z",
823	"sdcard_cmd_z";
824	function = "sdcard";
825	bias-pull-up;
826	drive-strength-microamp = <4000>;
827	};
828
829	mux-1 {
830	groups = "sdcard_clk_z";
831	function = "sdcard";
832	bias-disable;
833	drive-strength-microamp = <4000>;
834	};
835	};
836
837	sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
838	mux {
839	groups = "GPIOZ_6";
840	function = "gpio_periphs";
841	bias-pull-down;
842	drive-strength-microamp = <4000>;
843	};
844	};
845
846	sdio_pins: sdio {
847	mux {
848	groups = "sdio_d0",
849	"sdio_d1",
850	"sdio_d2",
851	"sdio_d3",
852	"sdio_clk",
853	"sdio_cmd";
854	function = "sdio";
855	bias-disable;
856	drive-strength-microamp = <4000>;
857	};
858	};
859
860	sdio_clk_gate_pins: sdio_clk_gate {
861	mux {
862	groups = "GPIOX_4";
863	function = "gpio_periphs";
864	bias-pull-down;
865	drive-strength-microamp = <4000>;
866	};
867	};
868
869	spdif_in_a10_pins: spdif-in-a10 {
870	mux {
871	groups = "spdif_in_a10";
872	function = "spdif_in";
873	bias-disable;
874	};
875	};
876
877	spdif_in_a12_pins: spdif-in-a12 {
878	mux {
879	groups = "spdif_in_a12";
880	function = "spdif_in";
881	bias-disable;
882	};
883	};
884
885	spdif_in_h_pins: spdif-in-h {
886	mux {
887	groups = "spdif_in_h";
888	function = "spdif_in";
889	bias-disable;
890	};
891	};
892
893	spdif_out_h_pins: spdif-out-h {
894	mux {
895	groups = "spdif_out_h";
896	function = "spdif_out";
897	drive-strength-microamp = <500>;
898	bias-disable;
899	};
900	};
901
902	spdif_out_a11_pins: spdif-out-a11 {
903	mux {
904	groups = "spdif_out_a11";
905	function = "spdif_out";
906	drive-strength-microamp = <500>;
907	bias-disable;
908	};
909	};
910
911	spdif_out_a13_pins: spdif-out-a13 {
912	mux {
913	groups = "spdif_out_a13";
914	function = "spdif_out";
915	drive-strength-microamp = <500>;
916	bias-disable;
917	};
918	};
919
920	tdm_a_din0_pins: tdm-a-din0 {
921	mux {
922	groups = "tdm_a_din0";
923	function = "tdm_a";
924	bias-disable;
925	};
926	};
927
928
929	tdm_a_din1_pins: tdm-a-din1 {
930	mux {
931	groups = "tdm_a_din1";
932	function = "tdm_a";
933	bias-disable;
934	};
935	};
936
937	tdm_a_dout0_pins: tdm-a-dout0 {
938	mux {
939	groups = "tdm_a_dout0";
940	function = "tdm_a";
941	bias-disable;
942	drive-strength-microamp = <3000>;
943	};
944	};
945
946	tdm_a_dout1_pins: tdm-a-dout1 {
947	mux {
948	groups = "tdm_a_dout1";
949	function = "tdm_a";
950	bias-disable;
951	drive-strength-microamp = <3000>;
952	};
953	};
954
955	tdm_a_fs_pins: tdm-a-fs {
956	mux {
957	groups = "tdm_a_fs";
958	function = "tdm_a";
959	bias-disable;
960	drive-strength-microamp = <3000>;
961	};
962	};
963
964	tdm_a_sclk_pins: tdm-a-sclk {
965	mux {
966	groups = "tdm_a_sclk";
967	function = "tdm_a";
968	bias-disable;
969	drive-strength-microamp = <3000>;
970	};
971	};
972
973	tdm_a_slv_fs_pins: tdm-a-slv-fs {
974	mux {
975	groups = "tdm_a_slv_fs";
976	function = "tdm_a";
977	bias-disable;
978	};
979	};
980
981
982	tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
983	mux {
984	groups = "tdm_a_slv_sclk";
985	function = "tdm_a";
986	bias-disable;
987	};
988	};
989
990	tdm_b_din0_pins: tdm-b-din0 {
991	mux {
992	groups = "tdm_b_din0";
993	function = "tdm_b";
994	bias-disable;
995	};
996	};
997
998	tdm_b_din1_pins: tdm-b-din1 {
999	mux {
1000	groups = "tdm_b_din1";
1001	function = "tdm_b";
1002	bias-disable;
1003	};
1004	};
1005
1006	tdm_b_din2_pins: tdm-b-din2 {
1007	mux {
1008	groups = "tdm_b_din2";
1009	function = "tdm_b";
1010	bias-disable;
1011	};
1012	};
1013
1014	tdm_b_din3_a_pins: tdm-b-din3-a {
1015	mux {
1016	groups = "tdm_b_din3_a";
1017	function = "tdm_b";
1018	bias-disable;
1019	};
1020	};
1021
1022	tdm_b_din3_h_pins: tdm-b-din3-h {
1023	mux {
1024	groups = "tdm_b_din3_h";
1025	function = "tdm_b";
1026	bias-disable;
1027	};
1028	};
1029
1030	tdm_b_dout0_pins: tdm-b-dout0 {
1031	mux {
1032	groups = "tdm_b_dout0";
1033	function = "tdm_b";
1034	bias-disable;
1035	drive-strength-microamp = <3000>;
1036	};
1037	};
1038
1039	tdm_b_dout1_pins: tdm-b-dout1 {
1040	mux {
1041	groups = "tdm_b_dout1";
1042	function = "tdm_b";
1043	bias-disable;
1044	drive-strength-microamp = <3000>;
1045	};
1046	};
1047
1048	tdm_b_dout2_pins: tdm-b-dout2 {
1049	mux {
1050	groups = "tdm_b_dout2";
1051	function = "tdm_b";
1052	bias-disable;
1053	drive-strength-microamp = <3000>;
1054	};
1055	};
1056
1057	tdm_b_dout3_a_pins: tdm-b-dout3-a {
1058	mux {
1059	groups = "tdm_b_dout3_a";
1060	function = "tdm_b";
1061	bias-disable;
1062	drive-strength-microamp = <3000>;
1063	};
1064	};
1065
1066	tdm_b_dout3_h_pins: tdm-b-dout3-h {
1067	mux {
1068	groups = "tdm_b_dout3_h";
1069	function = "tdm_b";
1070	bias-disable;
1071	drive-strength-microamp = <3000>;
1072	};
1073	};
1074
1075	tdm_b_fs_pins: tdm-b-fs {
1076	mux {
1077	groups = "tdm_b_fs";
1078	function = "tdm_b";
1079	bias-disable;
1080	drive-strength-microamp = <3000>;
1081	};
1082	};
1083
1084	tdm_b_sclk_pins: tdm-b-sclk {
1085	mux {
1086	groups = "tdm_b_sclk";
1087	function = "tdm_b";
1088	bias-disable;
1089	drive-strength-microamp = <3000>;
1090	};
1091	};
1092
1093	tdm_b_slv_fs_pins: tdm-b-slv-fs {
1094	mux {
1095	groups = "tdm_b_slv_fs";
1096	function = "tdm_b";
1097	bias-disable;
1098	};
1099	};
1100
1101	tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1102	mux {
1103	groups = "tdm_b_slv_sclk";
1104	function = "tdm_b";
1105	bias-disable;
1106	};
1107	};
1108
1109	tdm_c_din0_a_pins: tdm-c-din0-a {
1110	mux {
1111	groups = "tdm_c_din0_a";
1112	function = "tdm_c";
1113	bias-disable;
1114	};
1115	};
1116
1117	tdm_c_din0_z_pins: tdm-c-din0-z {
1118	mux {
1119	groups = "tdm_c_din0_z";
1120	function = "tdm_c";
1121	bias-disable;
1122	};
1123	};
1124
1125	tdm_c_din1_a_pins: tdm-c-din1-a {
1126	mux {
1127	groups = "tdm_c_din1_a";
1128	function = "tdm_c";
1129	bias-disable;
1130	};
1131	};
1132
1133	tdm_c_din1_z_pins: tdm-c-din1-z {
1134	mux {
1135	groups = "tdm_c_din1_z";
1136	function = "tdm_c";
1137	bias-disable;
1138	};
1139	};
1140
1141	tdm_c_din2_a_pins: tdm-c-din2-a {
1142	mux {
1143	groups = "tdm_c_din2_a";
1144	function = "tdm_c";
1145	bias-disable;
1146	};
1147	};
1148
1149	eth_leds_pins: eth-leds {
1150	mux {
1151	groups = "eth_link_led",
1152	"eth_act_led";
1153	function = "eth";
1154	bias-disable;
1155	};
1156	};
1157
1158	eth_pins: eth {
1159	mux {
1160	groups = "eth_mdio",
1161	"eth_mdc",
1162	"eth_rgmii_rx_clk",
1163	"eth_rx_dv",
1164	"eth_rxd0",
1165	"eth_rxd1",
1166	"eth_txen",
1167	"eth_txd0",
1168	"eth_txd1";
1169	function = "eth";
1170	drive-strength-microamp = <4000>;
1171	bias-disable;
1172	};
1173	};
1174
1175	eth_rgmii_pins: eth-rgmii {
1176	mux {
1177	groups = "eth_rxd2_rgmii",
1178	"eth_rxd3_rgmii",
1179	"eth_rgmii_tx_clk",
1180	"eth_txd2_rgmii",
1181	"eth_txd3_rgmii";
1182	function = "eth";
1183	drive-strength-microamp = <4000>;
1184	bias-disable;
1185	};
1186	};
1187
1188	tdm_c_din2_z_pins: tdm-c-din2-z {
1189	mux {
1190	groups = "tdm_c_din2_z";
1191	function = "tdm_c";
1192	bias-disable;
1193	};
1194	};
1195
1196	tdm_c_din3_a_pins: tdm-c-din3-a {
1197	mux {
1198	groups = "tdm_c_din3_a";
1199	function = "tdm_c";
1200	bias-disable;
1201	};
1202	};
1203
1204	tdm_c_din3_z_pins: tdm-c-din3-z {
1205	mux {
1206	groups = "tdm_c_din3_z";
1207	function = "tdm_c";
1208	bias-disable;
1209	};
1210	};
1211
1212	tdm_c_dout0_a_pins: tdm-c-dout0-a {
1213	mux {
1214	groups = "tdm_c_dout0_a";
1215	function = "tdm_c";
1216	bias-disable;
1217	drive-strength-microamp = <3000>;
1218	};
1219	};
1220
1221	tdm_c_dout0_z_pins: tdm-c-dout0-z {
1222	mux {
1223	groups = "tdm_c_dout0_z";
1224	function = "tdm_c";
1225	bias-disable;
1226	drive-strength-microamp = <3000>;
1227	};
1228	};
1229
1230	tdm_c_dout1_a_pins: tdm-c-dout1-a {
1231	mux {
1232	groups = "tdm_c_dout1_a";
1233	function = "tdm_c";
1234	bias-disable;
1235	drive-strength-microamp = <3000>;
1236	};
1237	};
1238
1239	tdm_c_dout1_z_pins: tdm-c-dout1-z {
1240	mux {
1241	groups = "tdm_c_dout1_z";
1242	function = "tdm_c";
1243	bias-disable;
1244	drive-strength-microamp = <3000>;
1245	};
1246	};
1247
1248	tdm_c_dout2_a_pins: tdm-c-dout2-a {
1249	mux {
1250	groups = "tdm_c_dout2_a";
1251	function = "tdm_c";
1252	bias-disable;
1253	drive-strength-microamp = <3000>;
1254	};
1255	};
1256
1257	tdm_c_dout2_z_pins: tdm-c-dout2-z {
1258	mux {
1259	groups = "tdm_c_dout2_z";
1260	function = "tdm_c";
1261	bias-disable;
1262	drive-strength-microamp = <3000>;
1263	};
1264	};
1265
1266	tdm_c_dout3_a_pins: tdm-c-dout3-a {
1267	mux {
1268	groups = "tdm_c_dout3_a";
1269	function = "tdm_c";
1270	bias-disable;
1271	drive-strength-microamp = <3000>;
1272	};
1273	};
1274
1275	tdm_c_dout3_z_pins: tdm-c-dout3-z {
1276	mux {
1277	groups = "tdm_c_dout3_z";
1278	function = "tdm_c";
1279	bias-disable;
1280	drive-strength-microamp = <3000>;
1281	};
1282	};
1283
1284	tdm_c_fs_a_pins: tdm-c-fs-a {
1285	mux {
1286	groups = "tdm_c_fs_a";
1287	function = "tdm_c";
1288	bias-disable;
1289	drive-strength-microamp = <3000>;
1290	};
1291	};
1292
1293	tdm_c_fs_z_pins: tdm-c-fs-z {
1294	mux {
1295	groups = "tdm_c_fs_z";
1296	function = "tdm_c";
1297	bias-disable;
1298	drive-strength-microamp = <3000>;
1299	};
1300	};
1301
1302	tdm_c_sclk_a_pins: tdm-c-sclk-a {
1303	mux {
1304	groups = "tdm_c_sclk_a";
1305	function = "tdm_c";
1306	bias-disable;
1307	drive-strength-microamp = <3000>;
1308	};
1309	};
1310
1311	tdm_c_sclk_z_pins: tdm-c-sclk-z {
1312	mux {
1313	groups = "tdm_c_sclk_z";
1314	function = "tdm_c";
1315	bias-disable;
1316	drive-strength-microamp = <3000>;
1317	};
1318	};
1319
1320	tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1321	mux {
1322	groups = "tdm_c_slv_fs_a";
1323	function = "tdm_c";
1324	bias-disable;
1325	};
1326	};
1327
1328	tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1329	mux {
1330	groups = "tdm_c_slv_fs_z";
1331	function = "tdm_c";
1332	bias-disable;
1333	};
1334	};
1335
1336	tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1337	mux {
1338	groups = "tdm_c_slv_sclk_a";
1339	function = "tdm_c";
1340	bias-disable;
1341	};
1342	};
1343
1344	tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1345	mux {
1346	groups = "tdm_c_slv_sclk_z";
1347	function = "tdm_c";
1348	bias-disable;
1349	};
1350	};
1351
1352	uart_a_pins: uart-a {
1353	mux {
1354	groups = "uart_a_tx",
1355	"uart_a_rx";
1356	function = "uart_a";
1357	bias-disable;
1358	};
1359	};
1360
1361	uart_a_cts_rts_pins: uart-a-cts-rts {
1362	mux {
1363	groups = "uart_a_cts",
1364	"uart_a_rts";
1365	function = "uart_a";
1366	bias-disable;
1367	};
1368	};
1369
1370	uart_b_pins: uart-b {
1371	mux {
1372	groups = "uart_b_tx",
1373	"uart_b_rx";
1374	function = "uart_b";
1375	bias-disable;
1376	};
1377	};
1378
1379	uart_c_pins: uart-c {
1380	mux {
1381	groups = "uart_c_tx",
1382	"uart_c_rx";
1383	function = "uart_c";
1384	bias-disable;
1385	};
1386	};
1387
1388	uart_c_cts_rts_pins: uart-c-cts-rts {
1389	mux {
1390	groups = "uart_c_cts",
1391	"uart_c_rts";
1392	function = "uart_c";
1393	bias-disable;
1394	};
1395	};
1396	};
1397	};
1398
1399	usb2_phy0: phy@36000 {
1400	compatible = "amlogic,g12a-usb2-phy";
1401	reg = <0x0 0x36000 0x0 0x2000>;
1402	clocks = <&xtal>;
1403	clock-names = "xtal";
1404	resets = <&reset RESET_USB_PHY20>;
1405	reset-names = "phy";
1406	#phy-cells = <0>;
1407	};
1408
1409	dmc: bus@38000 {
1410	compatible = "simple-bus";
1411	reg = <0x0 0x38000 0x0 0x400>;
1412	#address-cells = <2>;
1413	#size-cells = <2>;
1414	ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1415
1416	canvas: video-lut@48 {
1417	compatible = "amlogic,canvas";
1418	reg = <0x0 0x48 0x0 0x14>;
1419	};
1420	};
1421
1422	usb2_phy1: phy@3a000 {
1423	compatible = "amlogic,g12a-usb2-phy";
1424	reg = <0x0 0x3a000 0x0 0x2000>;
1425	clocks = <&xtal>;
1426	clock-names = "xtal";
1427	resets = <&reset RESET_USB_PHY21>;
1428	reset-names = "phy";
1429	#phy-cells = <0>;
1430	};
1431
1432	hiu: bus@3c000 {
1433	compatible = "simple-bus";
1434	reg = <0x0 0x3c000 0x0 0x1400>;
1435	#address-cells = <2>;
1436	#size-cells = <2>;
1437	ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1438
1439	hhi: system-controller@0 {
1440	compatible = "amlogic,meson-gx-hhi-sysctrl",
1441	"simple-mfd", "syscon";
1442	reg = <0 0 0 0x400>;
1443
1444	clkc: clock-controller {
1445	compatible = "amlogic,g12a-clkc";
1446	#clock-cells = <1>;
1447	clocks = <&xtal>;
1448	clock-names = "xtal";
1449	};
1450	};
1451	};
1452
1453	pdm: audio-controller@40000 {
1454	compatible = "amlogic,g12a-pdm",
1455	"amlogic,axg-pdm";
1456	reg = <0x0 0x40000 0x0 0x34>;
1457	#sound-dai-cells = <0>;
1458	sound-name-prefix = "PDM";
1459	clocks = <&clkc_audio AUD_CLKID_PDM>,
1460	<&clkc_audio AUD_CLKID_PDM_DCLK>,
1461	<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
1462	clock-names = "pclk", "dclk", "sysclk";
1463	status = "disabled";
1464	};
1465
1466	audio: bus@42000 {
1467	compatible = "simple-bus";
1468	reg = <0x0 0x42000 0x0 0x2000>;
1469	#address-cells = <2>;
1470	#size-cells = <2>;
1471	ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
1472
1473	clkc_audio: clock-controller@0 {
1474	status = "disabled";
1475	compatible = "amlogic,g12a-audio-clkc";
1476	reg = <0x0 0x0 0x0 0xb4>;
1477	#clock-cells = <1>;
1478
1479	clocks = <&clkc CLKID_AUDIO>,
1480	<&clkc CLKID_MPLL0>,
1481	<&clkc CLKID_MPLL1>,
1482	<&clkc CLKID_MPLL2>,
1483	<&clkc CLKID_MPLL3>,
1484	<&clkc CLKID_HIFI_PLL>,
1485	<&clkc CLKID_FCLK_DIV3>,
1486	<&clkc CLKID_FCLK_DIV4>,
1487	<&clkc CLKID_GP0_PLL>;
1488	clock-names = "pclk",
1489	"mst_in0",
1490	"mst_in1",
1491	"mst_in2",
1492	"mst_in3",
1493	"mst_in4",
1494	"mst_in5",
1495	"mst_in6",
1496	"mst_in7";
1497
1498	resets = <&reset RESET_AUDIO>;
1499	};
1500
1501	toddr_a: audio-controller@100 {
1502	compatible = "amlogic,g12a-toddr",
1503	"amlogic,axg-toddr";
1504	reg = <0x0 0x100 0x0 0x1c>;
1505	#sound-dai-cells = <0>;
1506	sound-name-prefix = "TODDR_A";
1507	interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
1508	clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1509	resets = <&arb AXG_ARB_TODDR_A>;
1510	status = "disabled";
1511	};
1512
1513	toddr_b: audio-controller@140 {
1514	compatible = "amlogic,g12a-toddr",
1515	"amlogic,axg-toddr";
1516	reg = <0x0 0x140 0x0 0x1c>;
1517	#sound-dai-cells = <0>;
1518	sound-name-prefix = "TODDR_B";
1519	interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
1520	clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1521	resets = <&arb AXG_ARB_TODDR_B>;
1522	status = "disabled";
1523	};
1524
1525	toddr_c: audio-controller@180 {
1526	compatible = "amlogic,g12a-toddr",
1527	"amlogic,axg-toddr";
1528	reg = <0x0 0x180 0x0 0x1c>;
1529	#sound-dai-cells = <0>;
1530	sound-name-prefix = "TODDR_C";
1531	interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1532	clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1533	resets = <&arb AXG_ARB_TODDR_C>;
1534	status = "disabled";
1535	};
1536
1537	frddr_a: audio-controller@1c0 {
1538	compatible = "amlogic,g12a-frddr",
1539	"amlogic,axg-frddr";
1540	reg = <0x0 0x1c0 0x0 0x1c>;
1541	#sound-dai-cells = <0>;
1542	sound-name-prefix = "FRDDR_A";
1543	interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
1544	clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1545	resets = <&arb AXG_ARB_FRDDR_A>;
1546	status = "disabled";
1547	};
1548
1549	frddr_b: audio-controller@200 {
1550	compatible = "amlogic,g12a-frddr",
1551	"amlogic,axg-frddr";
1552	reg = <0x0 0x200 0x0 0x1c>;
1553	#sound-dai-cells = <0>;
1554	sound-name-prefix = "FRDDR_B";
1555	interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
1556	clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1557	resets = <&arb AXG_ARB_FRDDR_B>;
1558	status = "disabled";
1559	};
1560
1561	frddr_c: audio-controller@240 {
1562	compatible = "amlogic,g12a-frddr",
1563	"amlogic,axg-frddr";
1564	reg = <0x0 0x240 0x0 0x1c>;
1565	#sound-dai-cells = <0>;
1566	sound-name-prefix = "FRDDR_C";
1567	interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
1568	clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1569	resets = <&arb AXG_ARB_FRDDR_C>;
1570	status = "disabled";
1571	};
1572
1573	arb: reset-controller@280 {
1574	status = "disabled";
1575	compatible = "amlogic,meson-axg-audio-arb";
1576	reg = <0x0 0x280 0x0 0x4>;
1577	#reset-cells = <1>;
1578	clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1579	};
1580
1581	tdmin_a: audio-controller@300 {
1582	compatible = "amlogic,g12a-tdmin",
1583	"amlogic,axg-tdmin";
1584	reg = <0x0 0x300 0x0 0x40>;
1585	sound-name-prefix = "TDMIN_A";
1586	clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1587	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1588	<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1589	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1590	<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1591	clock-names = "pclk", "sclk", "sclk_sel",
1592	"lrclk", "lrclk_sel";
1593	status = "disabled";
1594	};
1595
1596	tdmin_b: audio-controller@340 {
1597	compatible = "amlogic,g12a-tdmin",
1598	"amlogic,axg-tdmin";
1599	reg = <0x0 0x340 0x0 0x40>;
1600	sound-name-prefix = "TDMIN_B";
1601	clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1602	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1603	<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1604	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1605	<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1606	clock-names = "pclk", "sclk", "sclk_sel",
1607	"lrclk", "lrclk_sel";
1608	status = "disabled";
1609	};
1610
1611	tdmin_c: audio-controller@380 {
1612	compatible = "amlogic,g12a-tdmin",
1613	"amlogic,axg-tdmin";
1614	reg = <0x0 0x380 0x0 0x40>;
1615	sound-name-prefix = "TDMIN_C";
1616	clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1617	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1618	<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1619	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1620	<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1621	clock-names = "pclk", "sclk", "sclk_sel",
1622	"lrclk", "lrclk_sel";
1623	status = "disabled";
1624	};
1625
1626	tdmin_lb: audio-controller@3c0 {
1627	compatible = "amlogic,g12a-tdmin",
1628	"amlogic,axg-tdmin";
1629	reg = <0x0 0x3c0 0x0 0x40>;
1630	sound-name-prefix = "TDMIN_LB";
1631	clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1632	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1633	<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1634	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1635	<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1636	clock-names = "pclk", "sclk", "sclk_sel",
1637	"lrclk", "lrclk_sel";
1638	status = "disabled";
1639	};
1640
1641	spdifin: audio-controller@400 {
1642	compatible = "amlogic,g12a-spdifin",
1643	"amlogic,axg-spdifin";
1644	reg = <0x0 0x400 0x0 0x30>;
1645	#sound-dai-cells = <0>;
1646	sound-name-prefix = "SPDIFIN";
1647	interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
1648	clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1649	<&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1650	clock-names = "pclk", "refclk";
1651	status = "disabled";
1652	};
1653
1654	spdifout: audio-controller@480 {
1655	compatible = "amlogic,g12a-spdifout",
1656	"amlogic,axg-spdifout";
1657	reg = <0x0 0x480 0x0 0x50>;
1658	#sound-dai-cells = <0>;
1659	sound-name-prefix = "SPDIFOUT";
1660	clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1661	<&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1662	clock-names = "pclk", "mclk";
1663	status = "disabled";
1664	};
1665
1666	tdmout_a: audio-controller@500 {
1667	compatible = "amlogic,g12a-tdmout";
1668	reg = <0x0 0x500 0x0 0x40>;
1669	sound-name-prefix = "TDMOUT_A";
1670	clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1671	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1672	<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1673	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1674	<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1675	clock-names = "pclk", "sclk", "sclk_sel",
1676	"lrclk", "lrclk_sel";
1677	status = "disabled";
1678	};
1679
1680	tdmout_b: audio-controller@540 {
1681	compatible = "amlogic,g12a-tdmout";
1682	reg = <0x0 0x540 0x0 0x40>;
1683	sound-name-prefix = "TDMOUT_B";
1684	clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1685	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1686	<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1687	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1688	<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1689	clock-names = "pclk", "sclk", "sclk_sel",
1690	"lrclk", "lrclk_sel";
1691	status = "disabled";
1692	};
1693
1694	tdmout_c: audio-controller@580 {
1695	compatible = "amlogic,g12a-tdmout";
1696	reg = <0x0 0x580 0x0 0x40>;
1697	sound-name-prefix = "TDMOUT_C";
1698	clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1699	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1700	<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1701	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1702	<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1703	clock-names = "pclk", "sclk", "sclk_sel",
1704	"lrclk", "lrclk_sel";
1705	status = "disabled";
1706	};
1707
1708	spdifout_b: audio-controller@680 {
1709	compatible = "amlogic,g12a-spdifout",
1710	"amlogic,axg-spdifout";
1711	reg = <0x0 0x680 0x0 0x50>;
1712	#sound-dai-cells = <0>;
1713	sound-name-prefix = "SPDIFOUT_B";
1714	clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>,
1715	<&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>;
1716	clock-names = "pclk", "mclk";
1717	status = "disabled";
1718	};
1719
1720	tohdmitx: audio-controller@744 {
1721	compatible = "amlogic,g12a-tohdmitx";
1722	reg = <0x0 0x744 0x0 0x4>;
1723	#sound-dai-cells = <1>;
1724	sound-name-prefix = "TOHDMITX";
1725	status = "disabled";
1726	};
1727	};
1728
1729	usb3_pcie_phy: phy@46000 {
1730	compatible = "amlogic,g12a-usb3-pcie-phy";
1731	reg = <0x0 0x46000 0x0 0x2000>;
1732	clocks = <&clkc CLKID_PCIE_PLL>;
1733	clock-names = "ref_clk";
1734	resets = <&reset RESET_PCIE_PHY>;
1735	reset-names = "phy";
1736	assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1737	assigned-clock-rates = <100000000>;
1738	#phy-cells = <1>;
1739	};
1740
1741	eth_phy: mdio-multiplexer@4c000 {
1742	compatible = "amlogic,g12a-mdio-mux";
1743	reg = <0x0 0x4c000 0x0 0xa4>;
1744	clocks = <&clkc CLKID_ETH_PHY>,
1745	<&xtal>,
1746	<&clkc CLKID_MPLL_50M>;
1747	clock-names = "pclk", "clkin0", "clkin1";
1748	mdio-parent-bus = <&mdio0>;
1749	#address-cells = <1>;
1750	#size-cells = <0>;
1751
1752	ext_mdio: mdio@0 {
1753	reg = <0>;
1754	#address-cells = <1>;
1755	#size-cells = <0>;
1756	};
1757
1758	int_mdio: mdio@1 {
1759	reg = <1>;
1760	#address-cells = <1>;
1761	#size-cells = <0>;
1762
1763	internal_ephy: ethernet_phy@8 {
1764	compatible = "ethernet-phy-id0180.3301",
1765	"ethernet-phy-ieee802.3-c22";
1766	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1767	reg = <8>;
1768	max-speed = <100>;
1769	};
1770	};
1771	};
1772	};	74	};
1773		75
1774	aobus: bus@ff800000 {	76	opp-1000000000 {
1775	compatible = "simple-bus";	77	opp-hz = /bits/ 64 <1000000000>;
1776	reg = <0x0 0xff800000 0x0 0x100000>;	78	opp-microvolt = <731000>;
1777	#address-cells = <2>;
1778	#size-cells = <2>;
1779	ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1780
1781	rti: sys-ctrl@0 {
1782	compatible = "amlogic,meson-gx-ao-sysctrl",
1783	"simple-mfd", "syscon";
1784	reg = <0x0 0x0 0x0 0x100>;
1785	#address-cells = <2>;
1786	#size-cells = <2>;
1787	ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1788
1789	clkc_AO: clock-controller {
1790	compatible = "amlogic,meson-g12a-aoclkc";
1791	#clock-cells = <1>;
1792	#reset-cells = <1>;
1793	clocks = <&xtal>, <&clkc CLKID_CLK81>;
1794	clock-names = "xtal", "mpeg-clk";
1795	};
1796
1797	pwrc_vpu: power-controller-vpu {
1798	compatible = "amlogic,meson-g12a-pwrc-vpu";
1799	#power-domain-cells = <0>;
1800	amlogic,hhi-sysctrl = <&hhi>;
1801	resets = <&reset RESET_VIU>,
1802	<&reset RESET_VENC>,
1803	<&reset RESET_VCBUS>,
1804	<&reset RESET_BT656>,
1805	<&reset RESET_RDMA>,
1806	<&reset RESET_VENCI>,
1807	<&reset RESET_VENCP>,
1808	<&reset RESET_VDAC>,
1809	<&reset RESET_VDI6>,
1810	<&reset RESET_VENCL>,
1811	<&reset RESET_VID_LOCK>;
1812	clocks = <&clkc CLKID_VPU>,
1813	<&clkc CLKID_VAPB>;
1814	clock-names = "vpu", "vapb";
1815	/*
1816	* VPU clocking is provided by two identical clock paths
1817	* VPU_0 and VPU_1 muxed to a single clock by a glitch
1818	* free mux to safely change frequency while running.
1819	* Same for VAPB but with a final gate after the glitch free mux.
1820	*/
1821	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1822	<&clkc CLKID_VPU_0>,
1823	<&clkc CLKID_VPU>, /* Glitch free mux */
1824	<&clkc CLKID_VAPB_0_SEL>,
1825	<&clkc CLKID_VAPB_0>,
1826	<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1827	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1828	<0>, /* Do Nothing */
1829	<&clkc CLKID_VPU_0>,
1830	<&clkc CLKID_FCLK_DIV4>,
1831	<0>, /* Do Nothing */
1832	<&clkc CLKID_VAPB_0>;
1833	assigned-clock-rates = <0>, /* Do Nothing */
1834	<666666666>,
1835	<0>, /* Do Nothing */
1836	<0>, /* Do Nothing */
1837	<250000000>,
1838	<0>; /* Do Nothing */
1839	};
1840
1841	ao_pinctrl: pinctrl@14 {
1842	compatible = "amlogic,meson-g12a-aobus-pinctrl";
1843	#address-cells = <2>;
1844	#size-cells = <2>;
1845	ranges;
1846
1847	gpio_ao: bank@14 {
1848	reg = <0x0 0x14 0x0 0x8>,
1849	<0x0 0x1c 0x0 0x8>,
1850	<0x0 0x24 0x0 0x14>;
1851	reg-names = "mux",
1852	"ds",
1853	"gpio";
1854	gpio-controller;
1855	#gpio-cells = <2>;
1856	gpio-ranges = <&ao_pinctrl 0 0 15>;
1857	};
1858
1859	i2c_ao_sck_pins: i2c_ao_sck_pins {
1860	mux {
1861	groups = "i2c_ao_sck";
1862	function = "i2c_ao";
1863	bias-disable;
1864	drive-strength-microamp = <3000>;
1865	};
1866	};
1867
1868	i2c_ao_sda_pins: i2c_ao_sda {
1869	mux {
1870	groups = "i2c_ao_sda";
1871	function = "i2c_ao";
1872	bias-disable;
1873	drive-strength-microamp = <3000>;
1874	};
1875	};
1876
1877	i2c_ao_sck_e_pins: i2c_ao_sck_e {
1878	mux {
1879	groups = "i2c_ao_sck_e";
1880	function = "i2c_ao";
1881	bias-disable;
1882	drive-strength-microamp = <3000>;
1883	};
1884	};
1885
1886	i2c_ao_sda_e_pins: i2c_ao_sda_e {
1887	mux {
1888	groups = "i2c_ao_sda_e";
1889	function = "i2c_ao";
1890	bias-disable;
1891	drive-strength-microamp = <3000>;
1892	};
1893	};
1894
1895	mclk0_ao_pins: mclk0-ao {
1896	mux {
1897	groups = "mclk0_ao";
1898	function = "mclk0_ao";
1899	bias-disable;
1900	drive-strength-microamp = <3000>;
1901	};
1902	};
1903
1904	tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1905	mux {
1906	groups = "tdm_ao_b_din0";
1907	function = "tdm_ao_b";
1908	bias-disable;
1909	};
1910	};
1911
1912	spdif_ao_out_pins: spdif-ao-out {
1913	mux {
1914	groups = "spdif_ao_out";
1915	function = "spdif_ao_out";
1916	drive-strength-microamp = <500>;
1917	bias-disable;
1918	};
1919	};
1920
1921	tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1922	mux {
1923	groups = "tdm_ao_b_din1";
1924	function = "tdm_ao_b";
1925	bias-disable;
1926	};
1927	};
1928
1929	tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1930	mux {
1931	groups = "tdm_ao_b_din2";
1932	function = "tdm_ao_b";
1933	bias-disable;
1934	};
1935	};
1936
1937	tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1938	mux {
1939	groups = "tdm_ao_b_dout0";
1940	function = "tdm_ao_b";
1941	bias-disable;
1942	drive-strength-microamp = <3000>;
1943	};
1944	};
1945
1946	tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1947	mux {
1948	groups = "tdm_ao_b_dout1";
1949	function = "tdm_ao_b";
1950	bias-disable;
1951	drive-strength-microamp = <3000>;
1952	};
1953	};
1954
1955	tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1956	mux {
1957	groups = "tdm_ao_b_dout2";
1958	function = "tdm_ao_b";
1959	bias-disable;
1960	drive-strength-microamp = <3000>;
1961	};
1962	};
1963
1964	tdm_ao_b_fs_pins: tdm-ao-b-fs {
1965	mux {
1966	groups = "tdm_ao_b_fs";
1967	function = "tdm_ao_b";
1968	bias-disable;
1969	drive-strength-microamp = <3000>;
1970	};
1971	};
1972
1973	tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1974	mux {
1975	groups = "tdm_ao_b_sclk";
1976	function = "tdm_ao_b";
1977	bias-disable;
1978	drive-strength-microamp = <3000>;
1979	};
1980	};
1981
1982	tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1983	mux {
1984	groups = "tdm_ao_b_slv_fs";
1985	function = "tdm_ao_b";
1986	bias-disable;
1987	};
1988	};
1989
1990	tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1991	mux {
1992	groups = "tdm_ao_b_slv_sclk";
1993	function = "tdm_ao_b";
1994	bias-disable;
1995	};
1996	};
1997
1998	uart_ao_a_pins: uart-a-ao {
1999	mux {
2000	groups = "uart_ao_a_tx",
2001	"uart_ao_a_rx";
2002	function = "uart_ao_a";
2003	bias-disable;
2004	};
2005	};
2006
2007	uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
2008	mux {
2009	groups = "uart_ao_a_cts",
2010	"uart_ao_a_rts";
2011	function = "uart_ao_a";
2012	bias-disable;
2013	};
2014	};
2015
2016	pwm_ao_a_pins: pwm-ao-a {
2017	mux {
2018	groups = "pwm_ao_a";
2019	function = "pwm_ao_a";
2020	bias-disable;
2021	};
2022	};
2023
2024	pwm_ao_b_pins: pwm-ao-b {
2025	mux {
2026	groups = "pwm_ao_b";
2027	function = "pwm_ao_b";
2028	bias-disable;
2029	};
2030	};
2031
2032	pwm_ao_c_4_pins: pwm-ao-c-4 {
2033	mux {
2034	groups = "pwm_ao_c_4";
2035	function = "pwm_ao_c";
2036	bias-disable;
2037	};
2038	};
2039
2040	pwm_ao_c_6_pins: pwm-ao-c-6 {
2041	mux {
2042	groups = "pwm_ao_c_6";
2043	function = "pwm_ao_c";
2044	bias-disable;
2045	};
2046	};
2047
2048	pwm_ao_d_5_pins: pwm-ao-d-5 {
2049	mux {
2050	groups = "pwm_ao_d_5";
2051	function = "pwm_ao_d";
2052	bias-disable;
2053	};
2054	};
2055
2056	pwm_ao_d_10_pins: pwm-ao-d-10 {
2057	mux {
2058	groups = "pwm_ao_d_10";
2059	function = "pwm_ao_d";
2060	bias-disable;
2061	};
2062	};
2063
2064	pwm_ao_d_e_pins: pwm-ao-d-e {
2065	mux {
2066	groups = "pwm_ao_d_e";
2067	function = "pwm_ao_d";
2068	};
2069	};
2070
2071	remote_input_ao_pins: remote-input-ao {
2072	mux {
2073	groups = "remote_ao_input";
2074	function = "remote_ao_input";
2075	bias-disable;
2076	};
2077	};
2078	};
2079	};
2080
2081	cec_AO: cec@100 {
2082	compatible = "amlogic,meson-gx-ao-cec";
2083	reg = <0x0 0x00100 0x0 0x14>;
2084	interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2085	clocks = <&clkc_AO CLKID_AO_CEC>;
2086	clock-names = "core";
2087	status = "disabled";
2088	};
2089
2090	sec_AO: ao-secure@140 {
2091	compatible = "amlogic,meson-gx-ao-secure", "syscon";
2092	reg = <0x0 0x140 0x0 0x140>;
2093	amlogic,has-chip-id;
2094	};
2095
2096	cecb_AO: cec@280 {
2097	compatible = "amlogic,meson-g12a-ao-cec";
2098	reg = <0x0 0x00280 0x0 0x1c>;
2099	interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2100	clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2101	clock-names = "oscin";
2102	status = "disabled";
2103	};
2104
2105	pwm_AO_cd: pwm@2000 {
2106	compatible = "amlogic,meson-g12a-ao-pwm-cd";
2107	reg = <0x0 0x2000 0x0 0x20>;
2108	#pwm-cells = <3>;
2109	status = "disabled";
2110	};
2111
2112	uart_AO: serial@3000 {
2113	compatible = "amlogic,meson-gx-uart",
2114	"amlogic,meson-ao-uart";
2115	reg = <0x0 0x3000 0x0 0x18>;
2116	interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2117	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2118	clock-names = "xtal", "pclk", "baud";
2119	status = "disabled";
2120	};
2121
2122	uart_AO_B: serial@4000 {
2123	compatible = "amlogic,meson-gx-uart",
2124	"amlogic,meson-ao-uart";
2125	reg = <0x0 0x4000 0x0 0x18>;
2126	interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2127	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2128	clock-names = "xtal", "pclk", "baud";
2129	status = "disabled";
2130	};
2131
2132	i2c_AO: i2c@5000 {
2133	compatible = "amlogic,meson-axg-i2c";
2134	status = "disabled";
2135	reg = <0x0 0x05000 0x0 0x20>;
2136	interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2137	#address-cells = <1>;
2138	#size-cells = <0>;
2139	clocks = <&clkc CLKID_I2C>;
2140	};
2141
2142	pwm_AO_ab: pwm@7000 {
2143	compatible = "amlogic,meson-g12a-ao-pwm-ab";
2144	reg = <0x0 0x7000 0x0 0x20>;
2145	#pwm-cells = <3>;
2146	status = "disabled";
2147	};
2148
2149	ir: ir@8000 {
2150	compatible = "amlogic,meson-gxbb-ir";
2151	reg = <0x0 0x8000 0x0 0x20>;
2152	interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2153	status = "disabled";
2154	};
2155
2156	saradc: adc@9000 {
2157	compatible = "amlogic,meson-g12a-saradc",
2158	"amlogic,meson-saradc";
2159	reg = <0x0 0x9000 0x0 0x48>;
2160	#io-channel-cells = <1>;
2161	interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2162	clocks = <&xtal>,
2163	<&clkc_AO CLKID_AO_SAR_ADC>,
2164	<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2165	<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2166	clock-names = "clkin", "core", "adc_clk", "adc_sel";
2167	status = "disabled";
2168	};
2169	};	79	};
2170		80
2171	vpu: vpu@ff900000 {	81	opp-1200000000 {
2172	compatible = "amlogic,meson-g12a-vpu";	82	opp-hz = /bits/ 64 <1200000000>;
2173	reg = <0x0 0xff900000 0x0 0x100000>,	83	opp-microvolt = <731000>;
2174	<0x0 0xff63c000 0x0 0x1000>;
2175	reg-names = "vpu", "hhi";
2176	interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2177	#address-cells = <1>;
2178	#size-cells = <0>;
2179	amlogic,canvas = <&canvas>;
2180	power-domains = <&pwrc_vpu>;
2181
2182	/* CVBS VDAC output port */
2183	cvbs_vdac_port: port@0 {
2184	reg = <0>;
2185	};
2186
2187	/* HDMI-TX output port */
2188	hdmi_tx_port: port@1 {
2189	reg = <1>;
2190
2191	hdmi_tx_out: endpoint {
2192	remote-endpoint = <&hdmi_tx_in>;
2193	};
2194	};
2195	};	84	};
2196		85
2197	gic: interrupt-controller@ffc01000 {	86	opp-1398000000 {
2198	compatible = "arm,gic-400";	87	opp-hz = /bits/ 64 <1398000000>;
2199	reg = <0x0 0xffc01000 0 0x1000>,	88	opp-microvolt = <761000>;
2200	<0x0 0xffc02000 0 0x2000>,
2201	<0x0 0xffc04000 0 0x2000>,
2202	<0x0 0xffc06000 0 0x2000>;
2203	interrupt-controller;
2204	interrupts = <GIC_PPI 9
2205	(GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_HIGH)>;
2206	#interrupt-cells = <3>;
2207	#address-cells = <0>;
2208	};	89	};
2209		90
2210	cbus: bus@ffd00000 {	91	opp-1512000000 {
2211	compatible = "simple-bus";	92	opp-hz = /bits/ 64 <1512000000>;
2212	reg = <0x0 0xffd00000 0x0 0x100000>;	93	opp-microvolt = <791000>;
2213	#address-cells = <2>;
2214	#size-cells = <2>;
2215	ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2216
2217	reset: reset-controller@1004 {
2218	compatible = "amlogic,meson-g12a-reset",
2219	"amlogic,meson-axg-reset";
2220	reg = <0x0 0x1004 0x0 0x9c>;
2221	#reset-cells = <1>;
2222	};
2223
2224	gpio_intc: interrupt-controller@f080 {
2225	compatible = "amlogic,meson-g12a-gpio-intc",
2226	"amlogic,meson-gpio-intc";
2227	reg = <0x0 0xf080 0x0 0x10>;
2228	interrupt-controller;
2229	#interrupt-cells = <2>;
2230	amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2231	};
2232
2233	pwm_ef: pwm@19000 {
2234	compatible = "amlogic,meson-g12a-ee-pwm";
2235	reg = <0x0 0x19000 0x0 0x20>;
2236	#pwm-cells = <3>;
2237	status = "disabled";
2238	};
2239
2240	pwm_cd: pwm@1a000 {
2241	compatible = "amlogic,meson-g12a-ee-pwm";
2242	reg = <0x0 0x1a000 0x0 0x20>;
2243	#pwm-cells = <3>;
2244	status = "disabled";
2245	};
2246
2247	pwm_ab: pwm@1b000 {
2248	compatible = "amlogic,meson-g12a-ee-pwm";
2249	reg = <0x0 0x1b000 0x0 0x20>;
2250	#pwm-cells = <3>;
2251	status = "disabled";
2252	};
2253
2254	i2c3: i2c@1c000 {
2255	compatible = "amlogic,meson-axg-i2c";
2256	status = "disabled";
2257	reg = <0x0 0x1c000 0x0 0x20>;
2258	interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2259	#address-cells = <1>;
2260	#size-cells = <0>;
2261	clocks = <&clkc CLKID_I2C>;
2262	};
2263
2264	i2c2: i2c@1d000 {
2265	compatible = "amlogic,meson-axg-i2c";
2266	status = "disabled";
2267	reg = <0x0 0x1d000 0x0 0x20>;
2268	interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2269	#address-cells = <1>;
2270	#size-cells = <0>;
2271	clocks = <&clkc CLKID_I2C>;
2272	};
2273
2274	i2c1: i2c@1e000 {
2275	compatible = "amlogic,meson-axg-i2c";
2276	status = "disabled";
2277	reg = <0x0 0x1e000 0x0 0x20>;
2278	interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2279	#address-cells = <1>;
2280	#size-cells = <0>;
2281	clocks = <&clkc CLKID_I2C>;
2282	};
2283
2284	i2c0: i2c@1f000 {
2285	compatible = "amlogic,meson-axg-i2c";
2286	status = "disabled";
2287	reg = <0x0 0x1f000 0x0 0x20>;
2288	interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2289	#address-cells = <1>;
2290	#size-cells = <0>;
2291	clocks = <&clkc CLKID_I2C>;
2292	};
2293
2294	clk_msr: clock-measure@18000 {
2295	compatible = "amlogic,meson-g12a-clk-measure";
2296	reg = <0x0 0x18000 0x0 0x10>;
2297	};
2298
2299	uart_C: serial@22000 {
2300	compatible = "amlogic,meson-gx-uart";
2301	reg = <0x0 0x22000 0x0 0x18>;
2302	interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2303	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2304	clock-names = "xtal", "pclk", "baud";
2305	status = "disabled";
2306	};
2307
2308	uart_B: serial@23000 {
2309	compatible = "amlogic,meson-gx-uart";
2310	reg = <0x0 0x23000 0x0 0x18>;
2311	interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2312	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2313	clock-names = "xtal", "pclk", "baud";
2314	status = "disabled";
2315	};
2316
2317	uart_A: serial@24000 {
2318	compatible = "amlogic,meson-gx-uart";
2319	reg = <0x0 0x24000 0x0 0x18>;
2320	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2321	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2322	clock-names = "xtal", "pclk", "baud";
2323	status = "disabled";
2324	};
2325	};
2326
2327	sd_emmc_a: sd@ffe03000 {
2328	compatible = "amlogic,meson-axg-mmc";
2329	reg = <0x0 0xffe03000 0x0 0x800>;
2330	interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2331	status = "disabled";
2332	clocks = <&clkc CLKID_SD_EMMC_A>,
2333	<&clkc CLKID_SD_EMMC_A_CLK0>,
2334	<&clkc CLKID_FCLK_DIV2>;
2335	clock-names = "core", "clkin0", "clkin1";
2336	resets = <&reset RESET_SD_EMMC_A>;
2337	amlogic,dram-access-quirk;
2338	};
2339
2340	sd_emmc_b: sd@ffe05000 {
2341	compatible = "amlogic,meson-axg-mmc";
2342	reg = <0x0 0xffe05000 0x0 0x800>;
2343	interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2344	status = "disabled";
2345	clocks = <&clkc CLKID_SD_EMMC_B>,
2346	<&clkc CLKID_SD_EMMC_B_CLK0>,
2347	<&clkc CLKID_FCLK_DIV2>;
2348	clock-names = "core", "clkin0", "clkin1";
2349	resets = <&reset RESET_SD_EMMC_B>;
2350	};	94	};
2351		95
2352	sd_emmc_c: mmc@ffe07000 {	96	opp-1608000000 {
2353	compatible = "amlogic,meson-axg-mmc";	97	opp-hz = /bits/ 64 <1608000000>;
2354	reg = <0x0 0xffe07000 0x0 0x800>;	98	opp-microvolt = <831000>;
2355	interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2356	status = "disabled";
2357	clocks = <&clkc CLKID_SD_EMMC_C>,
2358	<&clkc CLKID_SD_EMMC_C_CLK0>,
2359	<&clkc CLKID_FCLK_DIV2>;
2360	clock-names = "core", "clkin0", "clkin1";
2361	resets = <&reset RESET_SD_EMMC_C>;
2362	};	99	};
2363		100
2364	usb: usb@ffe09000 {	101	opp-1704000000 {
2365	status = "disabled";	102	opp-hz = /bits/ 64 <1704000000>;
2366	compatible = "amlogic,meson-g12a-usb-ctrl";	103	opp-microvolt = <861000>;
2367	reg = <0x0 0xffe09000 0x0 0xa0>;
2368	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2369	#address-cells = <2>;
2370	#size-cells = <2>;
2371	ranges;
2372
2373	clocks = <&clkc CLKID_USB>;
2374	resets = <&reset RESET_USB>;
2375
2376	dr_mode = "otg";
2377
2378	phys = <&usb2_phy0>, <&usb2_phy1>,
2379	<&usb3_pcie_phy PHY_TYPE_USB3>;
2380	phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2381
2382	dwc2: usb@ff400000 {
2383	compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2384	reg = <0x0 0xff400000 0x0 0x40000>;
2385	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2386	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2387	clock-names = "ddr";
2388	phys = <&usb2_phy1>;
2389	dr_mode = "peripheral";
2390	g-rx-fifo-size = <192>;
2391	g-np-tx-fifo-size = <128>;
2392	g-tx-fifo-size = <128 128 16 16 16>;
2393	};
2394
2395	dwc3: usb@ff500000 {
2396	compatible = "snps,dwc3";
2397	reg = <0x0 0xff500000 0x0 0x100000>;
2398	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2399	dr_mode = "host";
2400	snps,dis_u2_susphy_quirk;
2401	snps,quirk-frame-length-adjustment;
2402	};
2403	};	104	};
2404		105
2405	mali: gpu@ffe40000 {	106	opp-1800000000 {
2406	compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";	107	opp-hz = /bits/ 64 <1800000000>;
2407	reg = <0x0 0xffe40000 0x0 0x40000>;	108	opp-microvolt = <981000>;
2408	interrupt-parent = <&gic>;
2409	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2410	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2411	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
2412	interrupt-names = "gpu", "mmu", "job";
2413	clocks = <&clkc CLKID_MALI>;
2414	resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2415
2416	/*
2417	* Mali clocking is provided by two identical clock paths
2418	* MALI_0 and MALI_1 muxed to a single clock by a glitch
2419	* free mux to safely change frequency while running.
2420	*/
2421	assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
2422	<&clkc CLKID_MALI_0>,
2423	<&clkc CLKID_MALI>; /* Glitch free mux */
2424	assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
2425	<0>, /* Do Nothing */
2426	<&clkc CLKID_MALI_0>;
2427	assigned-clock-rates = <0>, /* Do Nothing */
2428	<800000000>,
2429	<0>; /* Do Nothing */
2430	};	109	};
2431	};	110	};
		111	};
2432		112
2433	timer {	113	&sd_emmc_a {
2434	compatible = "arm,armv8-timer";	114	amlogic,dram-access-quirk;
2435	interrupts = <GIC_PPI 13
2436	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
2437	<GIC_PPI 14
2438	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
2439	<GIC_PPI 11
2440	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>,
2441	<GIC_PPI 10
2442	(GIC_CPU_MASK_RAW(0xff) \| IRQ_TYPE_LEVEL_LOW)>;
2443	};
2444
2445	xtal: xtal-clk {
2446	compatible = "fixed-clock";
2447	clock-frequency = <24000000>;
2448	clock-output-names = "xtal";
2449	#clock-cells = <0>;
2450	};
2451
2452	};	115	};

arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts+15−0

@@ -0,0 +1,15 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
	6	*/
	7
	8	/dts-v1/;
	9
	10	#include "meson-g12b-a311d.dtsi"
	11	#include "meson-g12b-khadas-vim3.dtsi"
	12
	13	/ {
	14	compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
	15	};

arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi+149−0

@@ -0,0 +1,149 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	*/
	6
	7	#include "meson-g12b.dtsi"
	8
	9	/ {
	10	cpu_opp_table_0: opp-table-0 {
	11	compatible = "operating-points-v2";
	12	opp-shared;
	13
	14	opp-100000000 {
	15	opp-hz = /bits/ 64 <100000000>;
	16	opp-microvolt = <731000>;
	17	};
	18
	19	opp-250000000 {
	20	opp-hz = /bits/ 64 <250000000>;
	21	opp-microvolt = <731000>;
	22	};
	23
	24	opp-500000000 {
	25	opp-hz = /bits/ 64 <500000000>;
	26	opp-microvolt = <731000>;
	27	};
	28
	29	opp-667000000 {
	30	opp-hz = /bits/ 64 <667000000>;
	31	opp-microvolt = <731000>;
	32	};
	33
	34	opp-1000000000 {
	35	opp-hz = /bits/ 64 <1000000000>;
	36	opp-microvolt = <761000>;
	37	};
	38
	39	opp-1200000000 {
	40	opp-hz = /bits/ 64 <1200000000>;
	41	opp-microvolt = <781000>;
	42	};
	43
	44	opp-1398000000 {
	45	opp-hz = /bits/ 64 <1398000000>;
	46	opp-microvolt = <811000>;
	47	};
	48
	49	opp-1512000000 {
	50	opp-hz = /bits/ 64 <1512000000>;
	51	opp-microvolt = <861000>;
	52	};
	53
	54	opp-1608000000 {
	55	opp-hz = /bits/ 64 <1608000000>;
	56	opp-microvolt = <901000>;
	57	};
	58
	59	opp-1704000000 {
	60	opp-hz = /bits/ 64 <1704000000>;
	61	opp-microvolt = <951000>;
	62	};
	63
	64	opp-1800000000 {
	65	opp-hz = /bits/ 64 <1800000000>;
	66	opp-microvolt = <1001000>;
	67	};
	68	};
	69
	70	cpub_opp_table_1: opp-table-1 {
	71	compatible = "operating-points-v2";
	72	opp-shared;
	73
	74	opp-100000000 {
	75	opp-hz = /bits/ 64 <100000000>;
	76	opp-microvolt = <731000>;
	77	};
	78
	79	opp-250000000 {
	80	opp-hz = /bits/ 64 <250000000>;
	81	opp-microvolt = <731000>;
	82	};
	83
	84	opp-500000000 {
	85	opp-hz = /bits/ 64 <500000000>;
	86	opp-microvolt = <731000>;
	87	};
	88
	89	opp-667000000 {
	90	opp-hz = /bits/ 64 <667000000>;
	91	opp-microvolt = <731000>;
	92	};
	93
	94	opp-1000000000 {
	95	opp-hz = /bits/ 64 <1000000000>;
	96	opp-microvolt = <731000>;
	97	};
	98
	99	opp-1200000000 {
	100	opp-hz = /bits/ 64 <1200000000>;
	101	opp-microvolt = <751000>;
	102	};
	103
	104	opp-1398000000 {
	105	opp-hz = /bits/ 64 <1398000000>;
	106	opp-microvolt = <771000>;
	107	};
	108
	109	opp-1512000000 {
	110	opp-hz = /bits/ 64 <1512000000>;
	111	opp-microvolt = <771000>;
	112	};
	113
	114	opp-1608000000 {
	115	opp-hz = /bits/ 64 <1608000000>;
	116	opp-microvolt = <781000>;
	117	};
	118
	119	opp-1704000000 {
	120	opp-hz = /bits/ 64 <1704000000>;
	121	opp-microvolt = <791000>;
	122	};
	123
	124	opp-1800000000 {
	125	opp-hz = /bits/ 64 <1800000000>;
	126	opp-microvolt = <831000>;
	127	};
	128
	129	opp-1908000000 {
	130	opp-hz = /bits/ 64 <1908000000>;
	131	opp-microvolt = <861000>;
	132	};
	133
	134	opp-2016000000 {
	135	opp-hz = /bits/ 64 <2016000000>;
	136	opp-microvolt = <911000>;
	137	};
	138
	139	opp-2108000000 {
	140	opp-hz = /bits/ 64 <2108000000>;
	141	opp-microvolt = <951000>;
	142	};
	143
	144	opp-2208000000 {
	145	opp-hz = /bits/ 64 <2208000000>;
	146	opp-microvolt = <1011000>;
	147	};
	148	};
	149	};

arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi+544−0

@@ -0,0 +1,544 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
	6	*/
	7
	8	#include <dt-bindings/input/input.h>
	9	#include <dt-bindings/gpio/meson-g12a-gpio.h>
	10	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
	11
	12	/ {
	13	model = "Khadas VIM3";
	14
	15	aliases {
	16	serial0 = &uart_AO;
	17	ethernet0 = &ethmac;
	18	};
	19
	20	chosen {
	21	stdout-path = "serial0:115200n8";
	22	};
	23
	24	memory@0 {
	25	device_type = "memory";
	26	reg = <0x0 0x0 0x0 0x80000000>;
	27	};
	28
	29	adc-keys {
	30	compatible = "adc-keys";
	31	io-channels = <&saradc 2>;
	32	io-channel-names = "buttons";
	33	keyup-threshold-microvolt = <1710000>;
	34
	35	button-function {
	36	label = "Function";
	37	linux,code = <KEY_FN>;
	38	press-threshold-microvolt = <10000>;
	39	};
	40	};
	41
	42	leds {
	43	compatible = "gpio-leds";
	44
	45	white {
	46	label = "vim3:white:sys";
	47	gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
	48	linux,default-trigger = "heartbeat";
	49	};
	50
	51	red {
	52	label = "vim3:red";
	53	gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
	54	};
	55	};
	56
	57	emmc_pwrseq: emmc-pwrseq {
	58	compatible = "mmc-pwrseq-emmc";
	59	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	60	};
	61
	62	gpio-keys-polled {
	63	compatible = "gpio-keys-polled";
	64	poll-interval = <100>;
	65
	66	power-button {
	67	label = "power";
	68	linux,code = <KEY_POWER>;
	69	gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
	70	};
	71	};
	72
	73	sdio_pwrseq: sdio-pwrseq {
	74	compatible = "mmc-pwrseq-simple";
	75	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	76	clocks = <&wifi32k>;
	77	clock-names = "ext_clock";
	78	};
	79
	80	dc_in: regulator-dc_in {
	81	compatible = "regulator-fixed";
	82	regulator-name = "DC_IN";
	83	regulator-min-microvolt = <5000000>;
	84	regulator-max-microvolt = <5000000>;
	85	regulator-always-on;
	86	};
	87
	88	vcc_5v: regulator-vcc_5v {
	89	compatible = "regulator-fixed";
	90	regulator-name = "VCC_5V";
	91	regulator-min-microvolt = <5000000>;
	92	regulator-max-microvolt = <5000000>;
	93	vin-supply = <&dc_in>;
	94
	95	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	96	enable-active-high;
	97	};
	98
	99	vcc_1v8: regulator-vcc_1v8 {
	100	compatible = "regulator-fixed";
	101	regulator-name = "VCC_1V8";
	102	regulator-min-microvolt = <1800000>;
	103	regulator-max-microvolt = <1800000>;
	104	vin-supply = <&vcc_3v3>;
	105	regulator-always-on;
	106	};
	107
	108	vcc_3v3: regulator-vcc_3v3 {
	109	compatible = "regulator-fixed";
	110	regulator-name = "VCC_3V3";
	111	regulator-min-microvolt = <3300000>;
	112	regulator-max-microvolt = <3300000>;
	113	vin-supply = <&vsys_3v3>;
	114	regulator-always-on;
	115	/* FIXME: actually controlled by VDDCPU_B_EN */
	116	};
	117
	118	vddcpu_a: regulator-vddcpu-a {
	119	/*
	120	* MP8756GD Regulator.
	121	*/
	122	compatible = "pwm-regulator";
	123
	124	regulator-name = "VDDCPU_A";
	125	regulator-min-microvolt = <690000>;
	126	regulator-max-microvolt = <1050000>;
	127
	128	vin-supply = <&dc_in>;
	129
	130	pwms = <&pwm_ab 0 1250 0>;
	131	pwm-dutycycle-range = <100 0>;
	132
	133	regulator-boot-on;
	134	regulator-always-on;
	135	};
	136
	137	vddcpu_b: regulator-vddcpu-b {
	138	/*
	139	* Silergy SY8030DEC Regulator.
	140	*/
	141	compatible = "pwm-regulator";
	142
	143	regulator-name = "VDDCPU_B";
	144	regulator-min-microvolt = <690000>;
	145	regulator-max-microvolt = <1050000>;
	146
	147	vin-supply = <&vsys_3v3>;
	148
	149	pwms = <&pwm_AO_cd 1 1250 0>;
	150	pwm-dutycycle-range = <100 0>;
	151
	152	regulator-boot-on;
	153	regulator-always-on;
	154	};
	155
	156	vddao_1v8: regulator-vddao_1v8 {
	157	compatible = "regulator-fixed";
	158	regulator-name = "VDDIO_AO1V8";
	159	regulator-min-microvolt = <1800000>;
	160	regulator-max-microvolt = <1800000>;
	161	vin-supply = <&vsys_3v3>;
	162	regulator-always-on;
	163	};
	164
	165	emmc_1v8: regulator-emmc_1v8 {
	166	compatible = "regulator-fixed";
	167	regulator-name = "EMMC_AO1V8";
	168	regulator-min-microvolt = <1800000>;
	169	regulator-max-microvolt = <1800000>;
	170	vin-supply = <&vcc_3v3>;
	171	regulator-always-on;
	172	};
	173
	174	vsys_3v3: regulator-vsys_3v3 {
	175	compatible = "regulator-fixed";
	176	regulator-name = "VSYS_3V3";
	177	regulator-min-microvolt = <3300000>;
	178	regulator-max-microvolt = <3300000>;
	179	vin-supply = <&dc_in>;
	180	regulator-always-on;
	181	};
	182
	183	usb_pwr: regulator-usb_pwr {
	184	compatible = "regulator-fixed";
	185	regulator-name = "USB_PWR";
	186	regulator-min-microvolt = <5000000>;
	187	regulator-max-microvolt = <5000000>;
	188	vin-supply = <&vcc_5v>;
	189
	190	gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
	191	enable-active-high;
	192	};
	193
	194	hdmi-connector {
	195	compatible = "hdmi-connector";
	196	type = "a";
	197
	198	port {
	199	hdmi_connector_in: endpoint {
	200	remote-endpoint = <&hdmi_tx_tmds_out>;
	201	};
	202	};
	203	};
	204
	205	wifi32k: wifi32k {
	206	compatible = "pwm-clock";
	207	#clock-cells = <0>;
	208	clock-frequency = <32768>;
	209	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	210	};
	211
	212	sound {
	213	compatible = "amlogic,axg-sound-card";
	214	model = "G12A-KHADAS-VIM3";
	215	audio-aux-devs = <&tdmout_b>;
	216	audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
	217	"TDMOUT_B IN 1", "FRDDR_B OUT 1",
	218	"TDMOUT_B IN 2", "FRDDR_C OUT 1",
	219	"TDM_B Playback", "TDMOUT_B OUT";
	220
	221	assigned-clocks = <&clkc CLKID_MPLL2>,
	222	<&clkc CLKID_MPLL0>,
	223	<&clkc CLKID_MPLL1>;
	224	assigned-clock-parents = <0>, <0>, <0>;
	225	assigned-clock-rates = <294912000>,
	226	<270950400>,
	227	<393216000>;
	228	status = "okay";
	229
	230	dai-link-0 {
	231	sound-dai = <&frddr_a>;
	232	};
	233
	234	dai-link-1 {
	235	sound-dai = <&frddr_b>;
	236	};
	237
	238	dai-link-2 {
	239	sound-dai = <&frddr_c>;
	240	};
	241
	242	/* 8ch hdmi interface */
	243	dai-link-3 {
	244	sound-dai = <&tdmif_b>;
	245	dai-format = "i2s";
	246	dai-tdm-slot-tx-mask-0 = <1 1>;
	247	dai-tdm-slot-tx-mask-1 = <1 1>;
	248	dai-tdm-slot-tx-mask-2 = <1 1>;
	249	dai-tdm-slot-tx-mask-3 = <1 1>;
	250	mclk-fs = <256>;
	251
	252	codec {
	253	sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
	254	};
	255	};
	256
	257	/* hdmi glue */
	258	dai-link-4 {
	259	sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
	260
	261	codec {
	262	sound-dai = <&hdmi_tx>;
	263	};
	264	};
	265	};
	266	};
	267
	268	&arb {
	269	status = "okay";
	270	};
	271
	272	&cec_AO {
	273	pinctrl-0 = <&cec_ao_a_h_pins>;
	274	pinctrl-names = "default";
	275	status = "disabled";
	276	hdmi-phandle = <&hdmi_tx>;
	277	};
	278
	279	&cecb_AO {
	280	pinctrl-0 = <&cec_ao_b_h_pins>;
	281	pinctrl-names = "default";
	282	status = "okay";
	283	hdmi-phandle = <&hdmi_tx>;
	284	};
	285
	286	&clkc_audio {
	287	status = "okay";
	288	};
	289
	290	&cpu0 {
	291	cpu-supply = <&vddcpu_b>;
	292	operating-points-v2 = <&cpu_opp_table_0>;
	293	clocks = <&clkc CLKID_CPU_CLK>;
	294	clock-latency = <50000>;
	295	};
	296
	297	&cpu1 {
	298	cpu-supply = <&vddcpu_b>;
	299	operating-points-v2 = <&cpu_opp_table_0>;
	300	clocks = <&clkc CLKID_CPU_CLK>;
	301	clock-latency = <50000>;
	302	};
	303
	304	&cpu100 {
	305	cpu-supply = <&vddcpu_a>;
	306	operating-points-v2 = <&cpub_opp_table_1>;
	307	clocks = <&clkc CLKID_CPUB_CLK>;
	308	clock-latency = <50000>;
	309	};
	310
	311	&cpu101 {
	312	cpu-supply = <&vddcpu_a>;
	313	operating-points-v2 = <&cpub_opp_table_1>;
	314	clocks = <&clkc CLKID_CPUB_CLK>;
	315	clock-latency = <50000>;
	316	};
	317
	318	&cpu102 {
	319	cpu-supply = <&vddcpu_a>;
	320	operating-points-v2 = <&cpub_opp_table_1>;
	321	clocks = <&clkc CLKID_CPUB_CLK>;
	322	clock-latency = <50000>;
	323	};
	324
	325	&cpu103 {
	326	cpu-supply = <&vddcpu_a>;
	327	operating-points-v2 = <&cpub_opp_table_1>;
	328	clocks = <&clkc CLKID_CPUB_CLK>;
	329	clock-latency = <50000>;
	330	};
	331
	332	&ext_mdio {
	333	external_phy: ethernet-phy@0 {
	334	/* Realtek RTL8211F (0x001cc916) */
	335	reg = <0>;
	336	max-speed = <1000>;
	337
	338	interrupt-parent = <&gpio_intc>;
	339	/* MAC_INTR on GPIOZ_14 */
	340	interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
	341	};
	342	};
	343
	344	&ethmac {
	345	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
	346	pinctrl-names = "default";
	347	status = "okay";
	348	phy-mode = "rgmii";
	349	phy-handle = <&external_phy>;
	350	amlogic,tx-delay-ns = <2>;
	351	};
	352
	353	&frddr_a {
	354	status = "okay";
	355	};
	356
	357	&frddr_b {
	358	status = "okay";
	359	};
	360
	361	&frddr_c {
	362	status = "okay";
	363	};
	364
	365	&hdmi_tx {
	366	status = "okay";
	367	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
	368	pinctrl-names = "default";
	369	hdmi-supply = <&vcc_5v>;
	370	};
	371
	372	&hdmi_tx_tmds_port {
	373	hdmi_tx_tmds_out: endpoint {
	374	remote-endpoint = <&hdmi_connector_in>;
	375	};
	376	};
	377
	378	&i2c_AO {
	379	status = "okay";
	380	pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
	381	pinctrl-names = "default";
	382
	383	gpio_expander: gpio-controller@20 {
	384	compatible = "ti,tca6408";
	385	reg = <0x20>;
	386	vcc-supply = <&vcc_3v3>;
	387	gpio-controller;
	388	#gpio-cells = <2>;
	389	};
	390
	391	rtc@51 {
	392	compatible = "haoyu,hym8563";
	393	reg = <0x51>;
	394	#clock-cells = <0>;
	395	};
	396	};
	397
	398	&ir {
	399	status = "okay";
	400	pinctrl-0 = <&remote_input_ao_pins>;
	401	pinctrl-names = "default";
	402	linux,rc-map-name = "rc-khadas";
	403	};
	404
	405	&pwm_ab {
	406	pinctrl-0 = <&pwm_a_e_pins>;
	407	pinctrl-names = "default";
	408	clocks = <&xtal>;
	409	clock-names = "clkin0";
	410	status = "okay";
	411	};
	412
	413	&pwm_AO_cd {
	414	pinctrl-0 = <&pwm_ao_d_e_pins>;
	415	pinctrl-names = "default";
	416	clocks = <&xtal>;
	417	clock-names = "clkin1";
	418	status = "okay";
	419	};
	420
	421	&pwm_ef {
	422	status = "okay";
	423	pinctrl-0 = <&pwm_e_pins>;
	424	pinctrl-names = "default";
	425	};
	426
	427	&saradc {
	428	status = "okay";
	429	vref-supply = <&vddao_1v8>;
	430	};
	431
	432	/* SDIO */
	433	&sd_emmc_a {
	434	status = "okay";
	435	pinctrl-0 = <&sdio_pins>;
	436	pinctrl-1 = <&sdio_clk_gate_pins>;
	437	pinctrl-names = "default", "clk-gate";
	438	#address-cells = <1>;
	439	#size-cells = <0>;
	440
	441	bus-width = <4>;
	442	cap-sd-highspeed;
	443	sd-uhs-sdr50;
	444	max-frequency = <100000000>;
	445
	446	non-removable;
	447	disable-wp;
	448
	449	mmc-pwrseq = <&sdio_pwrseq>;
	450
	451	vmmc-supply = <&vsys_3v3>;
	452	vqmmc-supply = <&vddao_1v8>;
	453
	454	brcmf: wifi@1 {
	455	reg = <1>;
	456	compatible = "brcm,bcm4329-fmac";
	457	};
	458	};
	459
	460	/* SD card */
	461	&sd_emmc_b {
	462	status = "okay";
	463	pinctrl-0 = <&sdcard_c_pins>;
	464	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	465	pinctrl-names = "default", "clk-gate";
	466
	467	bus-width = <4>;
	468	cap-sd-highspeed;
	469	max-frequency = <50000000>;
	470	disable-wp;
	471
	472	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	473	vmmc-supply = <&vsys_3v3>;
	474	vqmmc-supply = <&vsys_3v3>;
	475	};
	476
	477	/* eMMC */
	478	&sd_emmc_c {
	479	status = "okay";
	480	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	481	pinctrl-1 = <&emmc_clk_gate_pins>;
	482	pinctrl-names = "default", "clk-gate";
	483
	484	bus-width = <8>;
	485	cap-mmc-highspeed;
	486	mmc-ddr-1_8v;
	487	mmc-hs200-1_8v;
	488	max-frequency = <200000000>;
	489	disable-wp;
	490
	491	mmc-pwrseq = <&emmc_pwrseq>;
	492	vmmc-supply = <&vcc_3v3>;
	493	vqmmc-supply = <&emmc_1v8>;
	494	};
	495
	496	&tdmif_b {
	497	status = "okay";
	498	};
	499
	500	&tdmout_b {
	501	status = "okay";
	502	};
	503
	504	&tohdmitx {
	505	status = "okay";
	506	};
	507
	508	&uart_A {
	509	status = "okay";
	510	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	511	pinctrl-names = "default";
	512	uart-has-rtscts;
	513
	514	bluetooth {
	515	compatible = "brcm,bcm43438-bt";
	516	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	517	max-speed = <2000000>;
	518	clocks = <&wifi32k>;
	519	clock-names = "lpo";
	520	};
	521	};
	522
	523	&uart_AO {
	524	status = "okay";
	525	pinctrl-0 = <&uart_ao_a_pins>;
	526	pinctrl-names = "default";
	527	};
	528
	529	&usb2_phy0 {
	530	phy-supply = <&dc_in>;
	531	};
	532
	533	&usb2_phy1 {
	534	phy-supply = <&usb_pwr>;
	535	};
	536
	537	&usb3_pcie_phy {
	538	phy-supply = <&usb_pwr>;
	539	};
	540
	541	&usb {
	542	status = "okay";
	543	dr_mode = "peripheral";
	544	};

arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts+98−1

@@ -6,7 +6,7 @@ · 5 unmodified lines
6		6
7	/dts-v1/;	7	/dts-v1/;
8		8
9	#include "meson-g12b.dtsi"	9	#include "meson-g12b-s922x.dtsi"
10	#include <dt-bindings/input/input.h>	10	#include <dt-bindings/input/input.h>
11	#include <dt-bindings/gpio/meson-g12a-gpio.h>	11	#include <dt-bindings/gpio/meson-g12a-gpio.h>
12	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>	12	#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
@@ -53,6 +53,7 @@ · 40 unmodified lines
53		53
54	gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;	54	gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
55	enable-active-high;	55	enable-active-high;
		56	regulator-always-on;
56	};	57	};
57		58
58	tf_io: gpio-regulator-tf_io {	59	tf_io: gpio-regulator-tf_io {
@@ -114,6 +115,44 @@ · 55 unmodified lines
114	/* FIXME: actually controlled by VDDCPU_B_EN */	115	/* FIXME: actually controlled by VDDCPU_B_EN */
115	};	116	};
116		117
		118	vddcpu_a: regulator-vddcpu-a {
		119	/*
		120	* MP8756GD Regulator.
		121	*/
		122	compatible = "pwm-regulator";
		123
		124	regulator-name = "VDDCPU_A";
		125	regulator-min-microvolt = <721000>;
		126	regulator-max-microvolt = <1022000>;
		127
		128	vin-supply = <&main_12v>;
		129
		130	pwms = <&pwm_ab 0 1250 0>;
		131	pwm-dutycycle-range = <100 0>;
		132
		133	regulator-boot-on;
		134	regulator-always-on;
		135	};
		136
		137	vddcpu_b: regulator-vddcpu-b {
		138	/*
		139	* Silergy SY8120B1ABC Regulator.
		140	*/
		141	compatible = "pwm-regulator";
		142
		143	regulator-name = "VDDCPU_B";
		144	regulator-min-microvolt = <721000>;
		145	regulator-max-microvolt = <1022000>;
		146
		147	vin-supply = <&main_12v>;
		148
		149	pwms = <&pwm_AO_cd 1 1250 0>;
		150	pwm-dutycycle-range = <100 0>;
		151
		152	regulator-boot-on;
		153	regulator-always-on;
		154	};
		155
117	hub_5v: regulator-hub_5v {	156	hub_5v: regulator-hub_5v {
118	compatible = "regulator-fixed";	157	compatible = "regulator-fixed";
119	regulator-name = "HUB_5V";	158	regulator-name = "HUB_5V";
@@ -245,6 +284,48 @@ · 125 unmodified lines
245	status = "okay";	284	status = "okay";
246	};	285	};
247		286
		287	&cpu0 {
		288	cpu-supply = <&vddcpu_b>;
		289	operating-points-v2 = <&cpu_opp_table_0>;
		290	clocks = <&clkc CLKID_CPU_CLK>;
		291	clock-latency = <50000>;
		292	};
		293
		294	&cpu1 {
		295	cpu-supply = <&vddcpu_b>;
		296	operating-points-v2 = <&cpu_opp_table_0>;
		297	clocks = <&clkc CLKID_CPU_CLK>;
		298	clock-latency = <50000>;
		299	};
		300
		301	&cpu100 {
		302	cpu-supply = <&vddcpu_a>;
		303	operating-points-v2 = <&cpub_opp_table_1>;
		304	clocks = <&clkc CLKID_CPUB_CLK>;
		305	clock-latency = <50000>;
		306	};
		307
		308	&cpu101 {
		309	cpu-supply = <&vddcpu_a>;
		310	operating-points-v2 = <&cpub_opp_table_1>;
		311	clocks = <&clkc CLKID_CPUB_CLK>;
		312	clock-latency = <50000>;
		313	};
		314
		315	&cpu102 {
		316	cpu-supply = <&vddcpu_a>;
		317	operating-points-v2 = <&cpub_opp_table_1>;
		318	clocks = <&clkc CLKID_CPUB_CLK>;
		319	clock-latency = <50000>;
		320	};
		321
		322	&cpu103 {
		323	cpu-supply = <&vddcpu_a>;
		324	operating-points-v2 = <&cpub_opp_table_1>;
		325	clocks = <&clkc CLKID_CPUB_CLK>;
		326	clock-latency = <50000>;
		327	};
		328
248	&ext_mdio {	329	&ext_mdio {
249	external_phy: ethernet-phy@0 {	330	external_phy: ethernet-phy@0 {
250	/* Realtek RTL8211F (0x001cc916) */	331	/* Realtek RTL8211F (0x001cc916) */
@@ -316,6 +397,22 @@ · 65 unmodified lines
316	pinctrl-names = "default";	397	pinctrl-names = "default";
317	};	398	};
318		399
		400	&pwm_ab {
		401	pinctrl-0 = <&pwm_a_e_pins>;
		402	pinctrl-names = "default";
		403	clocks = <&xtal>;
		404	clock-names = "clkin0";
		405	status = "okay";
		406	};
		407
		408	&pwm_AO_cd {
		409	pinctrl-0 = <&pwm_ao_d_e_pins>;
		410	pinctrl-names = "default";
		411	clocks = <&xtal>;
		412	clock-names = "clkin1";
		413	status = "okay";
		414	};
		415
319	/* SD card */	416	/* SD card */
320	&sd_emmc_b {	417	&sd_emmc_b {
321	status = "okay";	418	status = "okay";

arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts+15−0

@@ -0,0 +1,15 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
	6	*/
	7
	8	/dts-v1/;
	9
	10	#include "meson-g12b-s922x.dtsi"
	11	#include "meson-g12b-khadas-vim3.dtsi"
	12
	13	/ {
	14	compatible = "khadas,vim3", "amlogic,s922x", "amlogic,g12b";
	15	};

arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi+124−0

@@ -0,0 +1,124 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	*/
	6
	7	#include "meson-g12b.dtsi"
	8
	9	/ {
	10	cpu_opp_table_0: opp-table-0 {
	11	compatible = "operating-points-v2";
	12	opp-shared;
	13
	14	opp-100000000 {
	15	opp-hz = /bits/ 64 <100000000>;
	16	opp-microvolt = <731000>;
	17	};
	18
	19	opp-250000000 {
	20	opp-hz = /bits/ 64 <250000000>;
	21	opp-microvolt = <731000>;
	22	};
	23
	24	opp-500000000 {
	25	opp-hz = /bits/ 64 <500000000>;
	26	opp-microvolt = <731000>;
	27	};
	28
	29	opp-667000000 {
	30	opp-hz = /bits/ 64 <667000000>;
	31	opp-microvolt = <731000>;
	32	};
	33
	34	opp-1000000000 {
	35	opp-hz = /bits/ 64 <1000000000>;
	36	opp-microvolt = <731000>;
	37	};
	38
	39	opp-1200000000 {
	40	opp-hz = /bits/ 64 <1200000000>;
	41	opp-microvolt = <731000>;
	42	};
	43
	44	opp-1398000000 {
	45	opp-hz = /bits/ 64 <1398000000>;
	46	opp-microvolt = <761000>;
	47	};
	48
	49	opp-1512000000 {
	50	opp-hz = /bits/ 64 <1512000000>;
	51	opp-microvolt = <791000>;
	52	};
	53
	54	opp-1608000000 {
	55	opp-hz = /bits/ 64 <1608000000>;
	56	opp-microvolt = <831000>;
	57	};
	58
	59	opp-1704000000 {
	60	opp-hz = /bits/ 64 <1704000000>;
	61	opp-microvolt = <861000>;
	62	};
	63
	64	opp-1896000000 {
	65	opp-hz = /bits/ 64 <1896000000>;
	66	opp-microvolt = <981000>;
	67	};
	68	};
	69
	70	cpub_opp_table_1: opp-table-1 {
	71	compatible = "operating-points-v2";
	72	opp-shared;
	73
	74	opp-100000000 {
	75	opp-hz = /bits/ 64 <100000000>;
	76	opp-microvolt = <751000>;
	77	};
	78
	79	opp-250000000 {
	80	opp-hz = /bits/ 64 <250000000>;
	81	opp-microvolt = <751000>;
	82	};
	83
	84	opp-500000000 {
	85	opp-hz = /bits/ 64 <500000000>;
	86	opp-microvolt = <751000>;
	87	};
	88
	89	opp-667000000 {
	90	opp-hz = /bits/ 64 <667000000>;
	91	opp-microvolt = <751000>;
	92	};
	93
	94	opp-1000000000 {
	95	opp-hz = /bits/ 64 <1000000000>;
	96	opp-microvolt = <771000>;
	97	};
	98
	99	opp-1200000000 {
	100	opp-hz = /bits/ 64 <1200000000>;
	101	opp-microvolt = <771000>;
	102	};
	103
	104	opp-1398000000 {
	105	opp-hz = /bits/ 64 <1398000000>;
	106	opp-microvolt = <791000>;
	107	};
	108
	109	opp-1512000000 {
	110	opp-hz = /bits/ 64 <1512000000>;
	111	opp-microvolt = <821000>;
	112	};
	113
	114	opp-1608000000 {
	115	opp-hz = /bits/ 64 <1608000000>;
	116	opp-microvolt = <861000>;
	117	};
	118
	119	opp-1704000000 {
	120	opp-hz = /bits/ 64 <1704000000>;
	121	opp-microvolt = <891000>;
	122	};
	123	};
	124	};

arch/arm64/boot/dts/amlogic/meson-g12b.dtsi+27−3

  * Author: Neil Armstrong <narmstrong@baylibre.com>
  */
-#include "meson-g12a.dtsi"
+#include "meson-g12-common.dtsi"
 / {
 	compatible = "amlogic,g12b";
 	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
 		cpu-map {
 			cluster0 {
 				core0 {
 			};
 		};
-		/delete-node/ cpu@2;
+		cpu0: cpu@0 {
-		/delete-node/ cpu@3;
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
 		cpu100: cpu@100 {
 			device_type = "cpu";
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 		};
+		l2: l2-cache0 {
+			compatible = "cache";
+		};
 	};
 };
 &clkc {
 	compatible = "amlogic,g12b-clkc";
 };
+&sd_emmc_a {
+	amlogic,dram-access-quirk;
+};

arch/arm64/boot/dts/amlogic/meson-gx.dtsi+16−0

@@ -437,6 +437,20 @@ · 436 unmodified lines
437	};	437	};
438	};	438	};
439		439
		440	vdec: video-codec@c8820000 {
		441	compatible = "amlogic,gx-vdec";
		442	reg = <0x0 0xc8820000 0x0 0x10000>,
		443	<0x0 0xc110a580 0x0 0xe4>;
		444	reg-names = "dos", "esparser";
		445
		446	interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
		447	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
		448	interrupt-names = "vdec", "esparser";
		449
		450	amlogic,ao-sysctrl = <&sysctrl_AO>;
		451	amlogic,canvas = <&canvas>;
		452	};
		453
440	periphs: periphs@c8834000 {	454	periphs: periphs@c8834000 {
441	compatible = "simple-bus";	455	compatible = "simple-bus";
442	reg = <0x0 0xc8834000 0x0 0x2000>;	456	reg = <0x0 0xc8834000 0x0 0x2000>;
@@ -493,6 +507,8 @@ · 50 unmodified lines
493	0x0 0xc8834540 0x0 0x4>;	507	0x0 0xc8834540 0x0 0x4>;
494	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;	508	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
495	interrupt-names = "macirq";	509	interrupt-names = "macirq";
		510	rx-fifo-depth = <4096>;
		511	tx-fifo-depth = <2048>;
496	status = "disabled";	512	status = "disabled";
497	};	513	};
498		514

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi+11−0

@@ -845,3 +845,14 @@ · 844 unmodified lines
845	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";	845	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
846	power-domains = <&pwrc_vpu>;	846	power-domains = <&pwrc_vpu>;
847	};	847	};
		848
		849	&vdec {
		850	compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
		851	clocks = <&clkc CLKID_DOS_PARSER>,
		852	<&clkc CLKID_DOS>,
		853	<&clkc CLKID_VDEC_1>,
		854	<&clkc CLKID_VDEC_HEVC>;
		855	clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
		856	resets = <&reset RESET_PARSER>;
		857	reset-names = "esparser";
		858	};

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi+11−0

@@ -848,3 +848,14 @@ · 847 unmodified lines
848	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";	848	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
849	power-domains = <&pwrc_vpu>;	849	power-domains = <&pwrc_vpu>;
850	};	850	};
		851
		852	&vdec {
		853	compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
		854	clocks = <&clkc CLKID_DOS_PARSER>,
		855	<&clkc CLKID_DOS>,
		856	<&clkc CLKID_VDEC_1>,
		857	<&clkc CLKID_VDEC_HEVC>;
		858	clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
		859	resets = <&reset RESET_PARSER>;
		860	reset-names = "esparser";
		861	};

arch/arm64/boot/dts/amlogic/meson-gxm.dtsi+4−0

@@ -144,3 +144,7 @@ · 143 unmodified lines
144	&dwc3 {	144	&dwc3 {
145	phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;	145	phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
146	};	146	};
		147
		148	&vdec {
		149	compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
		150	};

arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts+300−0

@@ -0,0 +1,300 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre SAS. All rights reserved.
	4	*/
	5
	6	/dts-v1/;
	7
	8	#include "meson-sm1.dtsi"
	9	#include <dt-bindings/gpio/gpio.h>
	10	#include <dt-bindings/input/input.h>
	11	#include <dt-bindings/gpio/meson-g12a-gpio.h>
	12
	13	/ {
	14	compatible = "seirobotics,sei610", "amlogic,sm1";
	15	model = "SEI Robotics SEI610";
	16
	17	aliases {
	18	serial0 = &uart_AO;
	19	ethernet0 = &ethmac;
	20	};
	21
	22	chosen {
	23	stdout-path = "serial0:115200n8";
	24	};
	25
	26	emmc_pwrseq: emmc-pwrseq {
	27	compatible = "mmc-pwrseq-emmc";
	28	reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
	29	};
	30
	31	gpio-keys {
	32	compatible = "gpio-keys-polled";
	33	poll-interval = <100>;
	34
	35	key1 {
	36	label = "A";
	37	linux,code = <BTN_0>;
	38	gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>;
	39	};
	40
	41	key2 {
	42	label = "B";
	43	linux,code = <BTN_1>;
	44	gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
	45	};
	46
	47	key3 {
	48	label = "C";
	49	linux,code = <BTN_2>;
	50	gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
	51	};
	52	};
	53
	54	leds {
	55	compatible = "gpio-leds";
	56
	57	bluetooth {
	58	label = "sei610:blue:bt";
	59	gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW \| GPIO_OPEN_DRAIN)>;
	60	default-state = "off";
	61	};
	62	};
	63
	64	pwmleds {
	65	compatible = "pwm-leds";
	66
	67	power {
	68	label = "sei610:red:power";
	69	pwms = <&pwm_AO_ab 0 30518 0>;
	70	max-brightness = <255>;
	71	linux,default-trigger = "default-on";
	72	active-low;
	73	};
	74	};
	75
	76	memory@0 {
	77	device_type = "memory";
	78	reg = <0x0 0x0 0x0 0x40000000>;
	79	};
	80
	81	ao_5v: regulator-ao_5v {
	82	compatible = "regulator-fixed";
	83	regulator-name = "AO_5V";
	84	regulator-min-microvolt = <5000000>;
	85	regulator-max-microvolt = <5000000>;
	86	vin-supply = <&dc_in>;
	87	regulator-always-on;
	88	};
	89
	90	dc_in: regulator-dc_in {
	91	compatible = "regulator-fixed";
	92	regulator-name = "DC_IN";
	93	regulator-min-microvolt = <5000000>;
	94	regulator-max-microvolt = <5000000>;
	95	regulator-always-on;
	96	};
	97
	98	emmc_1v8: regulator-emmc_1v8 {
	99	compatible = "regulator-fixed";
	100	regulator-name = "EMMC_1V8";
	101	regulator-min-microvolt = <1800000>;
	102	regulator-max-microvolt = <1800000>;
	103	vin-supply = <&vddao_3v3>;
	104	regulator-always-on;
	105	};
	106
	107	vddao_3v3: regulator-vddao_3v3 {
	108	compatible = "regulator-fixed";
	109	regulator-name = "VDDAO_3V3";
	110	regulator-min-microvolt = <3300000>;
	111	regulator-max-microvolt = <3300000>;
	112	vin-supply = <&dc_in>;
	113	regulator-always-on;
	114	};
	115
	116	/* Used by Tuner, RGB Led & IR Emitter LED array */
	117	vddao_3v3_t: regulator-vddao_3v3_t {
	118	compatible = "regulator-fixed";
	119	regulator-name = "VDDAO_3V3_T";
	120	regulator-min-microvolt = <3300000>;
	121	regulator-max-microvolt = <3300000>;
	122	vin-supply = <&vddao_3v3>;
	123	gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
	124	enable-active-low;
	125	regulator-always-on;
	126	};
	127
	128	vddio_ao1v8: regulator-vddio_ao1v8 {
	129	compatible = "regulator-fixed";
	130	regulator-name = "VDDIO_AO1V8";
	131	regulator-min-microvolt = <1800000>;
	132	regulator-max-microvolt = <1800000>;
	133	vin-supply = <&vddao_3v3>;
	134	regulator-always-on;
	135	};
	136
	137	reserved-memory {
	138	/* TEE Reserved Memory */
	139	bl32_reserved: bl32@5000000 {
	140	reg = <0x0 0x05300000 0x0 0x2000000>;
	141	no-map;
	142	};
	143	};
	144
	145	sdio_pwrseq: sdio-pwrseq {
	146	compatible = "mmc-pwrseq-simple";
	147	reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
	148	clocks = <&wifi32k>;
	149	clock-names = "ext_clock";
	150	};
	151
	152	wifi32k: wifi32k {
	153	compatible = "pwm-clock";
	154	#clock-cells = <0>;
	155	clock-frequency = <32768>;
	156	pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
	157	};
	158	};
	159
	160	&cec_AO {
	161	pinctrl-0 = <&cec_ao_a_h_pins>;
	162	pinctrl-names = "default";
	163	status = "disabled";
	164	hdmi-phandle = <&hdmi_tx>;
	165	};
	166
	167	&cecb_AO {
	168	pinctrl-0 = <&cec_ao_b_h_pins>;
	169	pinctrl-names = "default";
	170	status = "okay";
	171	hdmi-phandle = <&hdmi_tx>;
	172	};
	173
	174	&ethmac {
	175	status = "okay";
	176	phy-handle = <&internal_ephy>;
	177	phy-mode = "rmii";
	178	};
	179
	180	&i2c3 {
	181	status = "okay";
	182	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
	183	pinctrl-names = "default";
	184	};
	185
	186	&ir {
	187	status = "okay";
	188	pinctrl-0 = <&remote_input_ao_pins>;
	189	pinctrl-names = "default";
	190	};
	191
	192	&pwm_AO_ab {
	193	status = "okay";
	194	pinctrl-0 = <&pwm_ao_a_pins>;
	195	pinctrl-names = "default";
	196	clocks = <&xtal>;
	197	clock-names = "clkin0";
	198	};
	199
	200	&pwm_ef {
	201	status = "okay";
	202	pinctrl-0 = <&pwm_e_pins>;
	203	pinctrl-names = "default";
	204	clocks = <&xtal>;
	205	clock-names = "clkin0";
	206	};
	207
	208	&saradc {
	209	status = "okay";
	210	vref-supply = <&vddio_ao1v8>;
	211	};
	212
	213	/* SDIO */
	214	&sd_emmc_a {
	215	status = "okay";
	216	pinctrl-0 = <&sdio_pins>;
	217	pinctrl-1 = <&sdio_clk_gate_pins>;
	218	pinctrl-names = "default", "clk-gate";
	219	#address-cells = <1>;
	220	#size-cells = <0>;
	221
	222	bus-width = <4>;
	223	cap-sd-highspeed;
	224	sd-uhs-sdr50;
	225	max-frequency = <100000000>;
	226
	227	non-removable;
	228	disable-wp;
	229
	230	mmc-pwrseq = <&sdio_pwrseq>;
	231
	232	vmmc-supply = <&vddao_3v3>;
	233	vqmmc-supply = <&vddio_ao1v8>;
	234
	235	brcmf: wifi@1 {
	236	reg = <1>;
	237	compatible = "brcm,bcm4329-fmac";
	238	};
	239	};
	240
	241	/* SD card */
	242	&sd_emmc_b {
	243	status = "okay";
	244	pinctrl-0 = <&sdcard_c_pins>;
	245	pinctrl-1 = <&sdcard_clk_gate_c_pins>;
	246	pinctrl-names = "default", "clk-gate";
	247
	248	bus-width = <4>;
	249	cap-sd-highspeed;
	250	max-frequency = <50000000>;
	251	disable-wp;
	252
	253	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
	254	vmmc-supply = <&vddao_3v3>;
	255	vqmmc-supply = <&vddao_3v3>;
	256	};
	257
	258	/* eMMC */
	259	&sd_emmc_c {
	260	status = "okay";
	261	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	262	pinctrl-1 = <&emmc_clk_gate_pins>;
	263	pinctrl-names = "default", "clk-gate";
	264
	265	bus-width = <8>;
	266	cap-mmc-highspeed;
	267	mmc-ddr-1_8v;
	268	mmc-hs200-1_8v;
	269	max-frequency = <200000000>;
	270	non-removable;
	271	disable-wp;
	272
	273	mmc-pwrseq = <&emmc_pwrseq>;
	274	vmmc-supply = <&vddao_3v3>;
	275	vqmmc-supply = <&emmc_1v8>;
	276	};
	277
	278	&uart_A {
	279	status = "okay";
	280	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	281	pinctrl-names = "default";
	282	uart-has-rtscts;
	283
	284	bluetooth {
	285	compatible = "brcm,bcm43438-bt";
	286	shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
	287	max-speed = <2000000>;
	288	clocks = <&wifi32k>;
	289	clock-names = "lpo";
	290	vbat-supply = <&vddao_3v3>;
	291	vddio-supply = <&vddio_ao1v8>;
	292	};
	293	};
	294
	295	/* Exposed via the on-board USB to Serial FT232RL IC */
	296	&uart_AO {
	297	status = "okay";
	298	pinctrl-0 = <&uart_ao_a_pins>;
	299	pinctrl-names = "default";
	300	};

arch/arm64/boot/dts/amlogic/meson-sm1.dtsi+68−0

@@ -0,0 +1,68 @@
	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	*/
	6
	7	#include "meson-g12-common.dtsi"
	8
	9	/ {
	10	compatible = "amlogic,sm1";
	11
	12	cpus {
	13	#address-cells = <0x2>;
	14	#size-cells = <0x0>;
	15
	16	cpu0: cpu@0 {
	17	device_type = "cpu";
	18	compatible = "arm,cortex-a55";
	19	reg = <0x0 0x0>;
	20	enable-method = "psci";
	21	next-level-cache = <&l2>;
	22	};
	23
	24	cpu1: cpu@1 {
	25	device_type = "cpu";
	26	compatible = "arm,cortex-a55";
	27	reg = <0x0 0x1>;
	28	enable-method = "psci";
	29	next-level-cache = <&l2>;
	30	};
	31
	32	cpu2: cpu@2 {
	33	device_type = "cpu";
	34	compatible = "arm,cortex-a55";
	35	reg = <0x0 0x2>;
	36	enable-method = "psci";
	37	next-level-cache = <&l2>;
	38	};
	39
	40	cpu3: cpu@3 {
	41	device_type = "cpu";
	42	compatible = "arm,cortex-a55";
	43	reg = <0x0 0x3>;
	44	enable-method = "psci";
	45	next-level-cache = <&l2>;
	46	};
	47
	48	l2: l2-cache0 {
	49	compatible = "cache";
	50	};
	51	};
	52	};
	53
	54	&cecb_AO {
	55	compatible = "amlogic,meson-sm1-ao-cec";
	56	};
	57
	58	&clk_msr {
	59	compatible = "amlogic,meson-sm1-clk-measure";
	60	};
	61
	62	&pwrc_vpu {
	63	status = "disabled";
	64	};
	65
	66	&vpu {
	67	status = "disabled";
	68	};

drivers/clk/clk.c+6−0

 	return ret;
 }
+int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent)
+{
+	return clk_core_set_parent_nolock(hw->core, parent->core);
+}
+EXPORT_SYMBOL_GPL(clk_hw_set_parent);
 /**
  * clk_set_parent - switch the parent of a mux clk
  * @clk: the mux clk whose input we are switching

drivers/clk/meson/Kconfig+5−6

@@ -1,7 +1,4 @@
1	# SPDX-License-Identifier: GPL-2.0-only	1	# SPDX-License-Identifier: GPL-2.0-only
2	config COMMON_CLK_MESON_INPUT
3	tristate
4
5	config COMMON_CLK_MESON_REGMAP	2	config COMMON_CLK_MESON_REGMAP
6	tristate	3	tristate
7	select REGMAP	4	select REGMAP
@@ -33,13 +30,15 @@ config COMMON_CLK_MESON_VID_PLL_DIV · 25 unmodified lines
33	config COMMON_CLK_MESON_AO_CLKC	30	config COMMON_CLK_MESON_AO_CLKC
34	tristate	31	tristate
35	select COMMON_CLK_MESON_REGMAP	32	select COMMON_CLK_MESON_REGMAP
36	select COMMON_CLK_MESON_INPUT
37	select RESET_CONTROLLER	33	select RESET_CONTROLLER
38		34
39	config COMMON_CLK_MESON_EE_CLKC	35	config COMMON_CLK_MESON_EE_CLKC
40	tristate	36	tristate
41	select COMMON_CLK_MESON_REGMAP	37	select COMMON_CLK_MESON_REGMAP
42	select COMMON_CLK_MESON_INPUT	38
		39	config COMMON_CLK_MESON_CPU_DYNDIV
		40	tristate
		41	select COMMON_CLK_MESON_REGMAP
43		42
44	config COMMON_CLK_MESON8B	43	config COMMON_CLK_MESON8B
45	bool	44	bool
@@ -86,7 +85,6 @@ config COMMON_CLK_AXG · 40 unmodified lines
86	config COMMON_CLK_AXG_AUDIO	85	config COMMON_CLK_AXG_AUDIO
87	tristate "Meson AXG Audio Clock Controller Driver"	86	tristate "Meson AXG Audio Clock Controller Driver"
88	depends on ARCH_MESON	87	depends on ARCH_MESON
89	select COMMON_CLK_MESON_INPUT
90	select COMMON_CLK_MESON_REGMAP	88	select COMMON_CLK_MESON_REGMAP
91	select COMMON_CLK_MESON_PHASE	89	select COMMON_CLK_MESON_PHASE
92	select COMMON_CLK_MESON_SCLK_DIV	90	select COMMON_CLK_MESON_SCLK_DIV
@@ -104,6 +102,7 @@ config COMMON_CLK_G12A · 11 unmodified lines
104	select COMMON_CLK_MESON_PLL	102	select COMMON_CLK_MESON_PLL
105	select COMMON_CLK_MESON_AO_CLKC	103	select COMMON_CLK_MESON_AO_CLKC
106	select COMMON_CLK_MESON_EE_CLKC	104	select COMMON_CLK_MESON_EE_CLKC
		105	select COMMON_CLK_MESON_CPU_DYNDIV
107	select MFD_SYSCON	106	select MFD_SYSCON
108	help	107	help
109	Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2	108	Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2

drivers/clk/meson/Makefile+1−1

 # Amlogic clock drivers
 obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
+obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
 obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
 obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
-obj-$(CONFIG_COMMON_CLK_MESON_INPUT) += clk-input.o
 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
 obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
 obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o

drivers/clk/meson/axg-aoclk.c+37−26

 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
-#define IN_PREFIX "ao-in-"
 /*
  * AO Configuration Clock registers offsets
  * Register offsets from the data sheet must be multiplied by 4.
 	.hw.init = &(struct clk_init_data) {				\
 		.name =  "axg_ao_" #_name,				\
 		.ops = &clk_regmap_gate_ops,				\
-		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+		.parent_data = &(const struct clk_parent_data) {	\
+			.fw_name = "mpeg-clk",				\
+		},							\
 		.num_parents = 1,					\
 		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_oscin",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "xtal",
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_32k_pre",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "cts_oscin" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&axg_aoclk_cts_oscin.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_32k_div",
 		.ops = &meson_clk_dualdiv_ops,
-		.parent_names = (const char *[]){ "axg_ao_32k_pre" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&axg_aoclk_32k_pre.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_32k_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "axg_ao_32k_div",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "axg_ao_32k_pre" },
+			&axg_aoclk_32k_div.hw,
+			&axg_aoclk_32k_pre.hw,
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_32k",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "axg_ao_32k_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&axg_aoclk_32k_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_cts_rtc_oscin",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "axg_ao_32k",
+		.parent_data = (const struct clk_parent_data []) {
-						  IN_PREFIX "ext_32k-0" },
+			{ .hw = &axg_aoclk_32k.hw },
+			{ .fw_name = "ext_32k-0", },
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_clk81",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
+		.parent_data = (const struct clk_parent_data []) {
-						  "axg_ao_cts_rtc_oscin"},
+			{ .fw_name = "mpeg-clk", },
+			{ .hw = &axg_aoclk_cts_rtc_oscin.hw },
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_saradc_mux",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "xtal",
+		.parent_data = (const struct clk_parent_data []) {
-						  "axg_ao_clk81" },
+			{ .fw_name = "xtal", },
+			{ .hw = &axg_aoclk_clk81.hw },
+		},
 		.num_parents = 2,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_saradc_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "axg_ao_saradc_mux" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&axg_aoclk_saradc_mux.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "axg_ao_saradc_gate",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "axg_ao_saradc_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&axg_aoclk_saradc_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.num = NR_CLKS,
 };
-static const struct meson_aoclk_input axg_aoclk_inputs[] = {
-	{ .name = "xtal",	.required = true  },
-	{ .name = "mpeg-clk",	.required = true  },
-	{ .name = "ext-32k-0",	.required = false },
-};
 static const struct meson_aoclk_data axg_aoclkc_data = {
 	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
 	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
 	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
 	.clks		= axg_aoclk_regmap,
 	.hw_data	= &axg_aoclk_onecell_data,
-	.inputs		= axg_aoclk_inputs,
-	.num_inputs	= ARRAY_SIZE(axg_aoclk_inputs),
-	.input_prefix	= IN_PREFIX,
 };
 static const struct of_device_id axg_aoclkc_match_table[] = {

drivers/clk/meson/axg-audio.c+120−141

@@ -15,7 +15,6 @@ · 14 unmodified lines
15	#include <linux/slab.h>	15	#include <linux/slab.h>
16		16
17	#include "axg-audio.h"	17	#include "axg-audio.h"
18	#include "clk-input.h"
19	#include "clk-regmap.h"	18	#include "clk-regmap.h"
20	#include "clk-phase.h"	19	#include "clk-phase.h"
21	#include "sclk-div.h"	20	#include "sclk-div.h"
@@ -24,7 +23,7 @@ · 2 unmodified lines
24	#define AUD_SLV_SCLK_COUNT 10	23	#define AUD_SLV_SCLK_COUNT 10
25	#define AUD_SLV_LRCLK_COUNT 10	24	#define AUD_SLV_LRCLK_COUNT 10
26		25
27	#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \	26	#define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \
28	struct clk_regmap aud_##_name = { \	27	struct clk_regmap aud_##_name = { \
29	.data = &(struct clk_regmap_gate_data){ \	28	.data = &(struct clk_regmap_gate_data){ \
30	.offset = (_reg), \	29	.offset = (_reg), \
@@ -33,13 +32,13 @@ struct clk_regmap aud_##_name = { \ · 2 unmodified lines
33	.hw.init = &(struct clk_init_data) { \	32	.hw.init = &(struct clk_init_data) { \
34	.name = "aud_"#_name, \	33	.name = "aud_"#_name, \
35	.ops = &clk_regmap_gate_ops, \	34	.ops = &clk_regmap_gate_ops, \
36	.parent_names = (const char *[]){ _pname }, \	35	.parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
37	.num_parents = 1, \	36	.num_parents = 1, \
38	.flags = CLK_DUTY_CYCLE_PARENT \| (_iflags), \	37	.flags = CLK_DUTY_CYCLE_PARENT \| (_iflags), \
39	}, \	38	}, \
40	}	39	}
41		40
42	#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \	41	#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \
43	struct clk_regmap aud_##_name = { \	42	struct clk_regmap aud_##_name = { \
44	.data = &(struct clk_regmap_mux_data){ \	43	.data = &(struct clk_regmap_mux_data){ \
45	.offset = (_reg), \	44	.offset = (_reg), \
@@ -50,13 +49,13 @@ struct clk_regmap aud_##_name = { \ · 4 unmodified lines
50	.hw.init = &(struct clk_init_data){ \	49	.hw.init = &(struct clk_init_data){ \
51	.name = "aud_"#_name, \	50	.name = "aud_"#_name, \
52	.ops = &clk_regmap_mux_ops, \	51	.ops = &clk_regmap_mux_ops, \
53	.parent_names = (_pnames), \	52	.parent_data = _pdata, \
54	.num_parents = ARRAY_SIZE(_pnames), \	53	.num_parents = ARRAY_SIZE(_pdata), \
55	.flags = CLK_DUTY_CYCLE_PARENT \| (_iflags), \	54	.flags = CLK_DUTY_CYCLE_PARENT \| (_iflags), \
56	}, \	55	}, \
57	}	56	}
58		57
59	#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \	58	#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \
60	struct clk_regmap aud_##_name = { \	59	struct clk_regmap aud_##_name = { \
61	.data = &(struct clk_regmap_div_data){ \	60	.data = &(struct clk_regmap_div_data){ \
62	.offset = (_reg), \	61	.offset = (_reg), \
@@ -67,15 +66,27 @@ struct clk_regmap aud_##_name = { \ · 4 unmodified lines
67	.hw.init = &(struct clk_init_data){ \	66	.hw.init = &(struct clk_init_data){ \
68	.name = "aud_"#_name, \	67	.name = "aud_"#_name, \
69	.ops = &clk_regmap_divider_ops, \	68	.ops = &clk_regmap_divider_ops, \
70	.parent_names = (const char *[]) { _pname }, \	69	.parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
71	.num_parents = 1, \	70	.num_parents = 1, \
72	.flags = (_iflags), \	71	.flags = (_iflags), \
73	}, \	72	}, \
74	}	73	}
75		74
76	#define AUD_PCLK_GATE(_name, _bit) \	75	#define AUD_PCLK_GATE(_name, _bit) \
77	AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0)	76	struct clk_regmap aud_##_name = { \
78		77	.data = &(struct clk_regmap_gate_data){ \
		78	.offset = (AUDIO_CLK_GATE_EN), \
		79	.bit_idx = (_bit), \
		80	}, \
		81	.hw.init = &(struct clk_init_data) { \
		82	.name = "aud_"#_name, \
		83	.ops = &clk_regmap_gate_ops, \
		84	.parent_data = &(const struct clk_parent_data) { \
		85	.fw_name = "pclk", \
		86	}, \
		87	.num_parents = 1, \
		88	}, \
		89	}
79	/* Audio peripheral clocks */	90	/* Audio peripheral clocks */
80	static AUD_PCLK_GATE(ddr_arb, 0);	91	static AUD_PCLK_GATE(ddr_arb, 0);
81	static AUD_PCLK_GATE(pdm, 1);	92	static AUD_PCLK_GATE(pdm, 1);
@@ -100,14 +111,20 @@ static AUD_PCLK_GATE(power_detect, 19); · 18 unmodified lines
100	static AUD_PCLK_GATE(spdifout_b, 21);	111	static AUD_PCLK_GATE(spdifout_b, 21);
101		112
102	/* Audio Master Clocks */	113	/* Audio Master Clocks */
103	static const char * const mst_mux_parent_names[] = {	114	static const struct clk_parent_data mst_mux_parent_data[] = {
104	"aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3",	115	{ .fw_name = "mst_in0", },
105	"aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7",	116	{ .fw_name = "mst_in1", },
		117	{ .fw_name = "mst_in2", },
		118	{ .fw_name = "mst_in3", },
		119	{ .fw_name = "mst_in4", },
		120	{ .fw_name = "mst_in5", },
		121	{ .fw_name = "mst_in6", },
		122	{ .fw_name = "mst_in7", },
106	};	123	};
107		124
108	#define AUD_MST_MUX(_name, _reg, _flag) \	125	#define AUD_MST_MUX(_name, _reg, _flag) \
109	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \	126	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
110	mst_mux_parent_names, CLK_SET_RATE_PARENT)	127	mst_mux_parent_data, 0)
111		128
112	#define AUD_MST_MCLK_MUX(_name, _reg) \	129	#define AUD_MST_MCLK_MUX(_name, _reg) \
113	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)	130	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
@@ -129,7 +146,7 @@ static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); · 15 unmodified lines
129		146
130	#define AUD_MST_DIV(_name, _reg, _flag) \	147	#define AUD_MST_DIV(_name, _reg, _flag) \
131	AUD_DIV(_name##_div, _reg, 0, 16, _flag, \	148	AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
132	"aud_"#_name"_sel", CLK_SET_RATE_PARENT) \	149	aud_##_name##_sel, CLK_SET_RATE_PARENT) \
133		150
134	#define AUD_MST_MCLK_DIV(_name, _reg) \	151	#define AUD_MST_MCLK_DIV(_name, _reg) \
135	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)	152	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
@@ -150,7 +167,7 @@ static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); · 14 unmodified lines
150	static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);	167	static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
151		168
152	#define AUD_MST_MCLK_GATE(_name, _reg) \	169	#define AUD_MST_MCLK_GATE(_name, _reg) \
153	AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \	170	AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
154	CLK_SET_RATE_PARENT)	171	CLK_SET_RATE_PARENT)
155		172
156	static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);	173	static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
@@ -168,7 +185,7 @@ static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); · 11 unmodified lines
168	/* Sample Clocks */	185	/* Sample Clocks */
169	#define AUD_MST_SCLK_PRE_EN(_name, _reg) \	186	#define AUD_MST_SCLK_PRE_EN(_name, _reg) \
170	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \	187	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
171	"aud_mst_"#_name"_mclk", 0)	188	aud_mst_##_name##_mclk, 0)
172		189
173	static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);	190	static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
174	static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);	191	static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -178,7 +195,7 @@ static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); · 3 unmodified lines
178	static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);	195	static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
179		196
180	#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \	197	#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
181	_hi_shift, _hi_width, _pname, _iflags) \	198	_hi_shift, _hi_width, _phws, _iflags) \
182	struct clk_regmap aud_##_name = { \	199	struct clk_regmap aud_##_name = { \
183	.data = &(struct meson_sclk_div_data) { \	200	.data = &(struct meson_sclk_div_data) { \
184	.div = { \	201	.div = { \
@@ -195,7 +212,7 @@ struct clk_regmap aud_##_name = { \ · 10 unmodified lines
195	.hw.init = &(struct clk_init_data) { \	212	.hw.init = &(struct clk_init_data) { \
196	.name = "aud_"#_name, \	213	.name = "aud_"#_name, \
197	.ops = &meson_sclk_div_ops, \	214	.ops = &meson_sclk_div_ops, \
198	.parent_names = (const char *[]) { _pname }, \	215	.parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
199	.num_parents = 1, \	216	.num_parents = 1, \
200	.flags = (_iflags), \	217	.flags = (_iflags), \
201	}, \	218	}, \
@@ -203,7 +220,7 @@ struct clk_regmap aud_##_name = { \ · 1 unmodified line
203		220
204	#define AUD_MST_SCLK_DIV(_name, _reg) \	221	#define AUD_MST_SCLK_DIV(_name, _reg) \
205	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \	222	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
206	"aud_mst_"#_name"_sclk_pre_en", \	223	aud_mst_##_name##_sclk_pre_en, \
207	CLK_SET_RATE_PARENT)	224	CLK_SET_RATE_PARENT)
208		225
209	static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);	226	static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
@@ -214,8 +231,8 @@ static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); · 4 unmodified lines
214	static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);	231	static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
215		232
216	#define AUD_MST_SCLK_POST_EN(_name, _reg) \	233	#define AUD_MST_SCLK_POST_EN(_name, _reg) \
217	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \	234	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
218	"aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)	235	aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
219		236
220	static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);	237	static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
221	static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);	238	static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -224,8 +241,8 @@ static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0); · 2 unmodified lines
224	static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);	241	static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
225	static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);	242	static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
226		243
227	#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \	244	#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
228	_pname, _iflags) \	245	_phws, _iflags) \
229	struct clk_regmap aud_##_name = { \	246	struct clk_regmap aud_##_name = { \
230	.data = &(struct meson_clk_triphase_data) { \	247	.data = &(struct meson_clk_triphase_data) { \
231	.ph0 = { \	248	.ph0 = { \
@@ -247,7 +264,7 @@ struct clk_regmap aud_##_name = { \ · 15 unmodified lines
247	.hw.init = &(struct clk_init_data) { \	264	.hw.init = &(struct clk_init_data) { \
248	.name = "aud_"#_name, \	265	.name = "aud_"#_name, \
249	.ops = &meson_clk_triphase_ops, \	266	.ops = &meson_clk_triphase_ops, \
250	.parent_names = (const char *[]) { _pname }, \	267	.parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
251	.num_parents = 1, \	268	.num_parents = 1, \
252	.flags = CLK_DUTY_CYCLE_PARENT \| (_iflags), \	269	.flags = CLK_DUTY_CYCLE_PARENT \| (_iflags), \
253	}, \	270	}, \
@@ -255,7 +272,7 @@ struct clk_regmap aud_##_name = { \ · 1 unmodified line
255		272
256	#define AUD_MST_SCLK(_name, _reg) \	273	#define AUD_MST_SCLK(_name, _reg) \
257	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \	274	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
258	"aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)	275	aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
259		276
260	static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);	277	static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
261	static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);	278	static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -266,7 +283,7 @@ static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); · 4 unmodified lines
266		283
267	#define AUD_MST_LRCLK_DIV(_name, _reg) \	284	#define AUD_MST_LRCLK_DIV(_name, _reg) \
268	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \	285	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
269	"aud_mst_"#_name"_sclk_post_en", 0) \	286	aud_mst_##_name##_sclk_post_en, 0) \
270		287
271	static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);	288	static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
272	static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);	289	static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -277,7 +294,7 @@ static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); · 4 unmodified lines
277		294
278	#define AUD_MST_LRCLK(_name, _reg) \	295	#define AUD_MST_LRCLK(_name, _reg) \
279	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \	296	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
280	"aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)	297	aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
281		298
282	static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);	299	static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
283	static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);	300	static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -286,19 +303,29 @@ static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); · 2 unmodified lines
286	static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);	303	static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
287	static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);	304	static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
288		305
289	static const char * const tdm_sclk_parent_names[] = {	306	static const struct clk_parent_data tdm_sclk_parent_data[] = {
290	"aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",	307	{ .hw = &aud_mst_a_sclk.hw, },
291	"aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",	308	{ .hw = &aud_mst_b_sclk.hw, },
292	"aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2",	309	{ .hw = &aud_mst_c_sclk.hw, },
293	"aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5",	310	{ .hw = &aud_mst_d_sclk.hw, },
294	"aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8",	311	{ .hw = &aud_mst_e_sclk.hw, },
295	"aud_slv_sclk9"	312	{ .hw = &aud_mst_f_sclk.hw, },
		313	{ .fw_name = "slv_sclk0", },
		314	{ .fw_name = "slv_sclk1", },
		315	{ .fw_name = "slv_sclk2", },
		316	{ .fw_name = "slv_sclk3", },
		317	{ .fw_name = "slv_sclk4", },
		318	{ .fw_name = "slv_sclk5", },
		319	{ .fw_name = "slv_sclk6", },
		320	{ .fw_name = "slv_sclk7", },
		321	{ .fw_name = "slv_sclk8", },
		322	{ .fw_name = "slv_sclk9", },
296	};	323	};
297		324
298	#define AUD_TDM_SCLK_MUX(_name, _reg) \	325	#define AUD_TDM_SCLK_MUX(_name, _reg) \
299	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \	326	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
300	CLK_MUX_ROUND_CLOSEST, \	327	CLK_MUX_ROUND_CLOSEST, \
301	tdm_sclk_parent_names, 0)	328	tdm_sclk_parent_data, 0)
302		329
303	static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);	330	static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
304	static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);	331	static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -310,7 +337,7 @@ static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); · 5 unmodified lines
310		337
311	#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \	338	#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
312	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \	339	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
313	"aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)	340	aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
314		341
315	static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);	342	static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
316	static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);	343	static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -322,7 +349,7 @@ static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); · 5 unmodified lines
322		349
323	#define AUD_TDM_SCLK_POST_EN(_name, _reg) \	350	#define AUD_TDM_SCLK_POST_EN(_name, _reg) \
324	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \	351	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
325	"aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)	352	aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
326		353
327	static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);	354	static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
328	static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);	355	static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -344,8 +371,9 @@ static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); · 15 unmodified lines
344	.hw.init = &(struct clk_init_data) { \	371	.hw.init = &(struct clk_init_data) { \
345	.name = "aud_tdm"#_name"_sclk", \	372	.name = "aud_tdm"#_name"_sclk", \
346	.ops = &meson_clk_phase_ops, \	373	.ops = &meson_clk_phase_ops, \
347	.parent_names = (const char *[]) \	374	.parent_hws = (const struct clk_hw *[]) { \
348	{ "aud_tdm"#_name"_sclk_post_en" }, \	375	&aud_tdm##_name##_sclk_post_en.hw \
		376	}, \
349	.num_parents = 1, \	377	.num_parents = 1, \
350	.flags = CLK_DUTY_CYCLE_PARENT \| CLK_SET_RATE_PARENT, \	378	.flags = CLK_DUTY_CYCLE_PARENT \| CLK_SET_RATE_PARENT, \
351	}, \	379	}, \
@@ -359,19 +387,29 @@ static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); · 7 unmodified lines
359	static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);	387	static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
360	static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);	388	static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
361		389
362	static const char * const tdm_lrclk_parent_names[] = {	390	static const struct clk_parent_data tdm_lrclk_parent_data[] = {
363	"aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",	391	{ .hw = &aud_mst_a_lrclk.hw, },
364	"aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",	392	{ .hw = &aud_mst_b_lrclk.hw, },
365	"aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2",	393	{ .hw = &aud_mst_c_lrclk.hw, },
366	"aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5",	394	{ .hw = &aud_mst_d_lrclk.hw, },
367	"aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8",	395	{ .hw = &aud_mst_e_lrclk.hw, },
368	"aud_slv_lrclk9"	396	{ .hw = &aud_mst_f_lrclk.hw, },
		397	{ .fw_name = "slv_lrclk0", },
		398	{ .fw_name = "slv_lrclk1", },
		399	{ .fw_name = "slv_lrclk2", },
		400	{ .fw_name = "slv_lrclk3", },
		401	{ .fw_name = "slv_lrclk4", },
		402	{ .fw_name = "slv_lrclk5", },
		403	{ .fw_name = "slv_lrclk6", },
		404	{ .fw_name = "slv_lrclk7", },
		405	{ .fw_name = "slv_lrclk8", },
		406	{ .fw_name = "slv_lrclk9", },
369	};	407	};
370		408
371	#define AUD_TDM_LRLCK(_name, _reg) \	409	#define AUD_TDM_LRLCK(_name, _reg) \
372	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \	410	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
373	CLK_MUX_ROUND_CLOSEST, \	411	CLK_MUX_ROUND_CLOSEST, \
374	tdm_lrclk_parent_names, 0)	412	tdm_lrclk_parent_data, 0)
375		413
376	static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);	414	static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
377	static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);	415	static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -386,39 +424,51 @@ static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); · 8 unmodified lines
386	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \	424	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \
387	CLK_SET_RATE_NO_REPARENT)	425	CLK_SET_RATE_NO_REPARENT)
388		426
389	static const char * const mclk_pad_ctrl_parent_names[] = {	427	static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
390	"aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk",	428	{ .hw = &aud_mst_a_mclk.hw },
391	"aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk",	429	{ .hw = &aud_mst_b_mclk.hw },
		430	{ .hw = &aud_mst_c_mclk.hw },
		431	{ .hw = &aud_mst_d_mclk.hw },
		432	{ .hw = &aud_mst_e_mclk.hw },
		433	{ .hw = &aud_mst_f_mclk.hw },
392	};	434	};
393		435
394	static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,	436	static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
395	mclk_pad_ctrl_parent_names);	437	mclk_pad_ctrl_parent_data);
396	static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,	438	static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
397	mclk_pad_ctrl_parent_names);	439	mclk_pad_ctrl_parent_data);
398		440
399	static const char * const lrclk_pad_ctrl_parent_names[] = {	441	static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
400	"aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",	442	{ .hw = &aud_mst_a_lrclk.hw },
401	"aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",	443	{ .hw = &aud_mst_b_lrclk.hw },
		444	{ .hw = &aud_mst_c_lrclk.hw },
		445	{ .hw = &aud_mst_d_lrclk.hw },
		446	{ .hw = &aud_mst_e_lrclk.hw },
		447	{ .hw = &aud_mst_f_lrclk.hw },
402	};	448	};
403		449
404	static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,	450	static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
405	lrclk_pad_ctrl_parent_names);	451	lrclk_pad_ctrl_parent_data);
406	static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,	452	static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
407	lrclk_pad_ctrl_parent_names);	453	lrclk_pad_ctrl_parent_data);
408	static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,	454	static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
409	lrclk_pad_ctrl_parent_names);	455	lrclk_pad_ctrl_parent_data);
410		456
411	static const char * const sclk_pad_ctrl_parent_names[] = {	457	static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
412	"aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",	458	{ .hw = &aud_mst_a_sclk.hw },
413	"aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",	459	{ .hw = &aud_mst_b_sclk.hw },
		460	{ .hw = &aud_mst_c_sclk.hw },
		461	{ .hw = &aud_mst_d_sclk.hw },
		462	{ .hw = &aud_mst_e_sclk.hw },
		463	{ .hw = &aud_mst_f_sclk.hw },
414	};	464	};
415		465
416	static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,	466	static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
417	sclk_pad_ctrl_parent_names);	467	sclk_pad_ctrl_parent_data);
418	static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,	468	static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
419	sclk_pad_ctrl_parent_names);	469	sclk_pad_ctrl_parent_data);
420	static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,	470	static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
421	sclk_pad_ctrl_parent_names);	471	sclk_pad_ctrl_parent_data);
422		472
423	/*	473	/*
424	* Array of all clocks provided by this provider	474	* Array of all clocks provided by this provider
@@ -868,54 +918,6 @@ static int devm_clk_get_enable(struct device dev, char id) · 443 unmodified lines
868	return 0;	918	return 0;
869	}	919	}
870		920
871	static int axg_register_clk_hw_input(struct device *dev,
872	const char *name)
873	{
874	char *clk_name;
875	struct clk_hw *hw;
876	int err = 0;
877
878	clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
879	if (!clk_name)
880	return -ENOMEM;
881
882	hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
883	if (IS_ERR(hw)) {
884	/* It is ok if an input clock is missing */
885	if (PTR_ERR(hw) == -ENOENT) {
886	dev_dbg(dev, "%s not provided", name);
887	} else {
888	err = PTR_ERR(hw);
889	if (err != -EPROBE_DEFER)
890	dev_err(dev, "failed to get %s clock", name);
891	}
892	}
893
894	kfree(clk_name);
895	return err;
896	}
897
898	static int axg_register_clk_hw_inputs(struct device *dev,
899	const char *basename,
900	unsigned int count)
901	{
902	char *name;
903	int i, ret;
904
905	for (i = 0; i < count; i++) {
906	name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
907	if (!name)
908	return -ENOMEM;
909
910	ret = axg_register_clk_hw_input(dev, name);
911	kfree(name);
912	if (ret)
913	return ret;
914	}
915
916	return 0;
917	}
918
919	static const struct regmap_config axg_audio_regmap_cfg = {	921	static const struct regmap_config axg_audio_regmap_cfg = {
920	.reg_bits = 32,	922	.reg_bits = 32,
921	.val_bits = 32,	923	.val_bits = 32,
@@ -963,29 +965,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) · 41 unmodified lines
963	return ret;	965	return ret;
964	}	966	}
965		967
966	/* Register the peripheral input clock */
967	hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
968	if (IS_ERR(hw))
969	return PTR_ERR(hw);
970
971	/* Register optional input master clocks */
972	ret = axg_register_clk_hw_inputs(dev, "mst_in",
973	AUD_MST_IN_COUNT);
974	if (ret)
975	return ret;
976
977	/* Register optional input slave sclks */
978	ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
979	AUD_SLV_SCLK_COUNT);
980	if (ret)
981	return ret;
982
983	/* Register optional input slave lrclks */
984	ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
985	AUD_SLV_LRCLK_COUNT);
986	if (ret)
987	return ret;
988
989	/* Populate regmap for the regmap backed clocks */	968	/* Populate regmap for the regmap backed clocks */
990	for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)	969	for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
991	aud_clk_regmaps[i]->map = map;	970	aud_clk_regmaps[i]->map = map;

drivers/clk/meson/axg.c+147−60

@@ -14,7 +14,6 @@ · 13 unmodified lines
14	#include <linux/of_device.h>	14	#include <linux/of_device.h>
15	#include <linux/platform_device.h>	15	#include <linux/platform_device.h>
16		16
17	#include "clk-input.h"
18	#include "clk-regmap.h"	17	#include "clk-regmap.h"
19	#include "clk-pll.h"	18	#include "clk-pll.h"
20	#include "clk-mpll.h"	19	#include "clk-mpll.h"
@@ -59,7 +58,9 @@ static struct clk_regmap axg_fixed_pll_dco = { · 38 unmodified lines
59	.hw.init = &(struct clk_init_data){	58	.hw.init = &(struct clk_init_data){
60	.name = "fixed_pll_dco",	59	.name = "fixed_pll_dco",
61	.ops = &meson_clk_pll_ro_ops,	60	.ops = &meson_clk_pll_ro_ops,
62	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	61	.parent_data = &(const struct clk_parent_data) {
		62	.fw_name = "xtal",
		63	},
63	.num_parents = 1,	64	.num_parents = 1,
64	},	65	},
65	};	66	};
@@ -74,7 +75,9 @@ static struct clk_regmap axg_fixed_pll = { · 8 unmodified lines
74	.hw.init = &(struct clk_init_data){	75	.hw.init = &(struct clk_init_data){
75	.name = "fixed_pll",	76	.name = "fixed_pll",
76	.ops = &clk_regmap_divider_ro_ops,	77	.ops = &clk_regmap_divider_ro_ops,
77	.parent_names = (const char *[]){ "fixed_pll_dco" },	78	.parent_hws = (const struct clk_hw *[]) {
		79	&axg_fixed_pll_dco.hw
		80	},
78	.num_parents = 1,	81	.num_parents = 1,
79	/*	82	/*
80	* This clock won't ever change at runtime so	83	* This clock won't ever change at runtime so
@@ -114,7 +117,9 @@ static struct clk_regmap axg_sys_pll_dco = { · 33 unmodified lines
114	.hw.init = &(struct clk_init_data){	117	.hw.init = &(struct clk_init_data){
115	.name = "sys_pll_dco",	118	.name = "sys_pll_dco",
116	.ops = &meson_clk_pll_ro_ops,	119	.ops = &meson_clk_pll_ro_ops,
117	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	120	.parent_data = &(const struct clk_parent_data) {
		121	.fw_name = "xtal",
		122	},
118	.num_parents = 1,	123	.num_parents = 1,
119	},	124	},
120	};	125	};
@@ -129,7 +134,9 @@ static struct clk_regmap axg_sys_pll = { · 8 unmodified lines
129	.hw.init = &(struct clk_init_data){	134	.hw.init = &(struct clk_init_data){
130	.name = "sys_pll",	135	.name = "sys_pll",
131	.ops = &clk_regmap_divider_ro_ops,	136	.ops = &clk_regmap_divider_ro_ops,
132	.parent_names = (const char *[]){ "sys_pll_dco" },	137	.parent_hws = (const struct clk_hw *[]) {
		138	&axg_sys_pll_dco.hw
		139	},
133	.num_parents = 1,	140	.num_parents = 1,
134	.flags = CLK_SET_RATE_PARENT,	141	.flags = CLK_SET_RATE_PARENT,
135	},	142	},
@@ -215,7 +222,9 @@ static struct clk_regmap axg_gp0_pll_dco = { · 79 unmodified lines
215	.hw.init = &(struct clk_init_data){	222	.hw.init = &(struct clk_init_data){
216	.name = "gp0_pll_dco",	223	.name = "gp0_pll_dco",
217	.ops = &meson_clk_pll_ops,	224	.ops = &meson_clk_pll_ops,
218	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	225	.parent_data = &(const struct clk_parent_data) {
		226	.fw_name = "xtal",
		227	},
219	.num_parents = 1,	228	.num_parents = 1,
220	},	229	},
221	};	230	};
@@ -230,7 +239,9 @@ static struct clk_regmap axg_gp0_pll = { · 8 unmodified lines
230	.hw.init = &(struct clk_init_data){	239	.hw.init = &(struct clk_init_data){
231	.name = "gp0_pll",	240	.name = "gp0_pll",
232	.ops = &clk_regmap_divider_ops,	241	.ops = &clk_regmap_divider_ops,
233	.parent_names = (const char *[]){ "gp0_pll_dco" },	242	.parent_hws = (const struct clk_hw *[]) {
		243	&axg_gp0_pll_dco.hw
		244	},
234	.num_parents = 1,	245	.num_parents = 1,
235	.flags = CLK_SET_RATE_PARENT,	246	.flags = CLK_SET_RATE_PARENT,
236	},	247	},
@@ -284,7 +295,9 @@ static struct clk_regmap axg_hifi_pll_dco = { · 47 unmodified lines
284	.hw.init = &(struct clk_init_data){	295	.hw.init = &(struct clk_init_data){
285	.name = "hifi_pll_dco",	296	.name = "hifi_pll_dco",
286	.ops = &meson_clk_pll_ops,	297	.ops = &meson_clk_pll_ops,
287	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	298	.parent_data = &(const struct clk_parent_data) {
		299	.fw_name = "xtal",
		300	},
288	.num_parents = 1,	301	.num_parents = 1,
289	},	302	},
290	};	303	};
@@ -299,7 +312,9 @@ static struct clk_regmap axg_hifi_pll = { · 8 unmodified lines
299	.hw.init = &(struct clk_init_data){	312	.hw.init = &(struct clk_init_data){
300	.name = "hifi_pll",	313	.name = "hifi_pll",
301	.ops = &clk_regmap_divider_ops,	314	.ops = &clk_regmap_divider_ops,
302	.parent_names = (const char *[]){ "hifi_pll_dco" },	315	.parent_hws = (const struct clk_hw *[]) {
		316	&axg_hifi_pll_dco.hw
		317	},
303	.num_parents = 1,	318	.num_parents = 1,
304	.flags = CLK_SET_RATE_PARENT,	319	.flags = CLK_SET_RATE_PARENT,
305	},	320	},
@@ -311,7 +326,7 @@ static struct clk_fixed_factor axg_fclk_div2_div = { · 5 unmodified lines
311	.hw.init = &(struct clk_init_data){	326	.hw.init = &(struct clk_init_data){
312	.name = "fclk_div2_div",	327	.name = "fclk_div2_div",
313	.ops = &clk_fixed_factor_ops,	328	.ops = &clk_fixed_factor_ops,
314	.parent_names = (const char *[]){ "fixed_pll" },	329	.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
315	.num_parents = 1,	330	.num_parents = 1,
316	},	331	},
317	};	332	};
@@ -324,7 +339,9 @@ static struct clk_regmap axg_fclk_div2 = { · 6 unmodified lines
324	.hw.init = &(struct clk_init_data){	339	.hw.init = &(struct clk_init_data){
325	.name = "fclk_div2",	340	.name = "fclk_div2",
326	.ops = &clk_regmap_gate_ops,	341	.ops = &clk_regmap_gate_ops,
327	.parent_names = (const char *[]){ "fclk_div2_div" },	342	.parent_hws = (const struct clk_hw *[]) {
		343	&axg_fclk_div2_div.hw
		344	},
328	.num_parents = 1,	345	.num_parents = 1,
329	.flags = CLK_IS_CRITICAL,	346	.flags = CLK_IS_CRITICAL,
330	},	347	},
@@ -336,7 +353,7 @@ static struct clk_fixed_factor axg_fclk_div3_div = { · 5 unmodified lines
336	.hw.init = &(struct clk_init_data){	353	.hw.init = &(struct clk_init_data){
337	.name = "fclk_div3_div",	354	.name = "fclk_div3_div",
338	.ops = &clk_fixed_factor_ops,	355	.ops = &clk_fixed_factor_ops,
339	.parent_names = (const char *[]){ "fixed_pll" },	356	.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
340	.num_parents = 1,	357	.num_parents = 1,
341	},	358	},
342	};	359	};
@@ -349,7 +366,9 @@ static struct clk_regmap axg_fclk_div3 = { · 6 unmodified lines
349	.hw.init = &(struct clk_init_data){	366	.hw.init = &(struct clk_init_data){
350	.name = "fclk_div3",	367	.name = "fclk_div3",
351	.ops = &clk_regmap_gate_ops,	368	.ops = &clk_regmap_gate_ops,
352	.parent_names = (const char *[]){ "fclk_div3_div" },	369	.parent_hws = (const struct clk_hw *[]) {
		370	&axg_fclk_div3_div.hw
		371	},
353	.num_parents = 1,	372	.num_parents = 1,
354	/*	373	/*
355	* FIXME:	374	* FIXME:
@@ -372,7 +391,7 @@ static struct clk_fixed_factor axg_fclk_div4_div = { · 16 unmodified lines
372	.hw.init = &(struct clk_init_data){	391	.hw.init = &(struct clk_init_data){
373	.name = "fclk_div4_div",	392	.name = "fclk_div4_div",
374	.ops = &clk_fixed_factor_ops,	393	.ops = &clk_fixed_factor_ops,
375	.parent_names = (const char *[]){ "fixed_pll" },	394	.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
376	.num_parents = 1,	395	.num_parents = 1,
377	},	396	},
378	};	397	};
@@ -385,7 +404,9 @@ static struct clk_regmap axg_fclk_div4 = { · 6 unmodified lines
385	.hw.init = &(struct clk_init_data){	404	.hw.init = &(struct clk_init_data){
386	.name = "fclk_div4",	405	.name = "fclk_div4",
387	.ops = &clk_regmap_gate_ops,	406	.ops = &clk_regmap_gate_ops,
388	.parent_names = (const char *[]){ "fclk_div4_div" },	407	.parent_hws = (const struct clk_hw *[]) {
		408	&axg_fclk_div4_div.hw
		409	},
389	.num_parents = 1,	410	.num_parents = 1,
390	},	411	},
391	};	412	};
@@ -396,7 +417,7 @@ static struct clk_fixed_factor axg_fclk_div5_div = { · 4 unmodified lines
396	.hw.init = &(struct clk_init_data){	417	.hw.init = &(struct clk_init_data){
397	.name = "fclk_div5_div",	418	.name = "fclk_div5_div",
398	.ops = &clk_fixed_factor_ops,	419	.ops = &clk_fixed_factor_ops,
399	.parent_names = (const char *[]){ "fixed_pll" },	420	.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
400	.num_parents = 1,	421	.num_parents = 1,
401	},	422	},
402	};	423	};
@@ -409,7 +430,9 @@ static struct clk_regmap axg_fclk_div5 = { · 6 unmodified lines
409	.hw.init = &(struct clk_init_data){	430	.hw.init = &(struct clk_init_data){
410	.name = "fclk_div5",	431	.name = "fclk_div5",
411	.ops = &clk_regmap_gate_ops,	432	.ops = &clk_regmap_gate_ops,
412	.parent_names = (const char *[]){ "fclk_div5_div" },	433	.parent_hws = (const struct clk_hw *[]) {
		434	&axg_fclk_div5_div.hw
		435	},
413	.num_parents = 1,	436	.num_parents = 1,
414	},	437	},
415	};	438	};
@@ -420,7 +443,9 @@ static struct clk_fixed_factor axg_fclk_div7_div = { · 4 unmodified lines
420	.hw.init = &(struct clk_init_data){	443	.hw.init = &(struct clk_init_data){
421	.name = "fclk_div7_div",	444	.name = "fclk_div7_div",
422	.ops = &clk_fixed_factor_ops,	445	.ops = &clk_fixed_factor_ops,
423	.parent_names = (const char *[]){ "fixed_pll" },	446	.parent_hws = (const struct clk_hw *[]) {
		447	&axg_fixed_pll.hw
		448	},
424	.num_parents = 1,	449	.num_parents = 1,
425	},	450	},
426	};	451	};
@@ -433,7 +458,9 @@ static struct clk_regmap axg_fclk_div7 = { · 6 unmodified lines
433	.hw.init = &(struct clk_init_data){	458	.hw.init = &(struct clk_init_data){
434	.name = "fclk_div7",	459	.name = "fclk_div7",
435	.ops = &clk_regmap_gate_ops,	460	.ops = &clk_regmap_gate_ops,
436	.parent_names = (const char *[]){ "fclk_div7_div" },	461	.parent_hws = (const struct clk_hw *[]) {
		462	&axg_fclk_div7_div.hw
		463	},
437	.num_parents = 1,	464	.num_parents = 1,
438	},	465	},
439	};	466	};
@@ -447,7 +474,9 @@ static struct clk_regmap axg_mpll_prediv = { · 7 unmodified lines
447	.hw.init = &(struct clk_init_data){	474	.hw.init = &(struct clk_init_data){
448	.name = "mpll_prediv",	475	.name = "mpll_prediv",
449	.ops = &clk_regmap_divider_ro_ops,	476	.ops = &clk_regmap_divider_ro_ops,
450	.parent_names = (const char *[]){ "fixed_pll" },	477	.parent_hws = (const struct clk_hw *[]) {
		478	&axg_fixed_pll.hw
		479	},
451	.num_parents = 1,	480	.num_parents = 1,
452	},	481	},
453	};	482	};
@@ -480,7 +509,9 @@ static struct clk_regmap axg_mpll0_div = { · 26 unmodified lines
480	.hw.init = &(struct clk_init_data){	509	.hw.init = &(struct clk_init_data){
481	.name = "mpll0_div",	510	.name = "mpll0_div",
482	.ops = &meson_clk_mpll_ops,	511	.ops = &meson_clk_mpll_ops,
483	.parent_names = (const char *[]){ "mpll_prediv" },	512	.parent_hws = (const struct clk_hw *[]) {
		513	&axg_mpll_prediv.hw
		514	},
484	.num_parents = 1,	515	.num_parents = 1,
485	},	516	},
486	};	517	};
@@ -493,7 +524,9 @@ static struct clk_regmap axg_mpll0 = { · 6 unmodified lines
493	.hw.init = &(struct clk_init_data){	524	.hw.init = &(struct clk_init_data){
494	.name = "mpll0",	525	.name = "mpll0",
495	.ops = &clk_regmap_gate_ops,	526	.ops = &clk_regmap_gate_ops,
496	.parent_names = (const char *[]){ "mpll0_div" },	527	.parent_hws = (const struct clk_hw *[]) {
		528	&axg_mpll0_div.hw
		529	},
497	.num_parents = 1,	530	.num_parents = 1,
498	.flags = CLK_SET_RATE_PARENT,	531	.flags = CLK_SET_RATE_PARENT,
499	},	532	},
@@ -527,7 +560,9 @@ static struct clk_regmap axg_mpll1_div = { · 27 unmodified lines
527	.hw.init = &(struct clk_init_data){	560	.hw.init = &(struct clk_init_data){
528	.name = "mpll1_div",	561	.name = "mpll1_div",
529	.ops = &meson_clk_mpll_ops,	562	.ops = &meson_clk_mpll_ops,
530	.parent_names = (const char *[]){ "mpll_prediv" },	563	.parent_hws = (const struct clk_hw *[]) {
		564	&axg_mpll_prediv.hw
		565	},
531	.num_parents = 1,	566	.num_parents = 1,
532	},	567	},
533	};	568	};
@@ -540,7 +575,9 @@ static struct clk_regmap axg_mpll1 = { · 6 unmodified lines
540	.hw.init = &(struct clk_init_data){	575	.hw.init = &(struct clk_init_data){
541	.name = "mpll1",	576	.name = "mpll1",
542	.ops = &clk_regmap_gate_ops,	577	.ops = &clk_regmap_gate_ops,
543	.parent_names = (const char *[]){ "mpll1_div" },	578	.parent_hws = (const struct clk_hw *[]) {
		579	&axg_mpll1_div.hw
		580	},
544	.num_parents = 1,	581	.num_parents = 1,
545	.flags = CLK_SET_RATE_PARENT,	582	.flags = CLK_SET_RATE_PARENT,
546	},	583	},
@@ -579,7 +616,9 @@ static struct clk_regmap axg_mpll2_div = { · 32 unmodified lines
579	.hw.init = &(struct clk_init_data){	616	.hw.init = &(struct clk_init_data){
580	.name = "mpll2_div",	617	.name = "mpll2_div",
581	.ops = &meson_clk_mpll_ops,	618	.ops = &meson_clk_mpll_ops,
582	.parent_names = (const char *[]){ "mpll_prediv" },	619	.parent_hws = (const struct clk_hw *[]) {
		620	&axg_mpll_prediv.hw
		621	},
583	.num_parents = 1,	622	.num_parents = 1,
584	},	623	},
585	};	624	};
@@ -592,7 +631,9 @@ static struct clk_regmap axg_mpll2 = { · 6 unmodified lines
592	.hw.init = &(struct clk_init_data){	631	.hw.init = &(struct clk_init_data){
593	.name = "mpll2",	632	.name = "mpll2",
594	.ops = &clk_regmap_gate_ops,	633	.ops = &clk_regmap_gate_ops,
595	.parent_names = (const char *[]){ "mpll2_div" },	634	.parent_hws = (const struct clk_hw *[]) {
		635	&axg_mpll2_div.hw
		636	},
596	.num_parents = 1,	637	.num_parents = 1,
597	.flags = CLK_SET_RATE_PARENT,	638	.flags = CLK_SET_RATE_PARENT,
598	},	639	},
@@ -626,7 +667,9 @@ static struct clk_regmap axg_mpll3_div = { · 27 unmodified lines
626	.hw.init = &(struct clk_init_data){	667	.hw.init = &(struct clk_init_data){
627	.name = "mpll3_div",	668	.name = "mpll3_div",
628	.ops = &meson_clk_mpll_ops,	669	.ops = &meson_clk_mpll_ops,
629	.parent_names = (const char *[]){ "mpll_prediv" },	670	.parent_hws = (const struct clk_hw *[]) {
		671	&axg_mpll_prediv.hw
		672	},
630	.num_parents = 1,	673	.num_parents = 1,
631	},	674	},
632	};	675	};
@@ -639,7 +682,9 @@ static struct clk_regmap axg_mpll3 = { · 6 unmodified lines
639	.hw.init = &(struct clk_init_data){	682	.hw.init = &(struct clk_init_data){
640	.name = "mpll3",	683	.name = "mpll3",
641	.ops = &clk_regmap_gate_ops,	684	.ops = &clk_regmap_gate_ops,
642	.parent_names = (const char *[]){ "mpll3_div" },	685	.parent_hws = (const struct clk_hw *[]) {
		686	&axg_mpll3_div.hw
		687	},
643	.num_parents = 1,	688	.num_parents = 1,
644	.flags = CLK_SET_RATE_PARENT,	689	.flags = CLK_SET_RATE_PARENT,
645	},	690	},
@@ -702,7 +747,9 @@ static struct clk_regmap axg_pcie_pll_dco = { · 56 unmodified lines
702	.hw.init = &(struct clk_init_data){	747	.hw.init = &(struct clk_init_data){
703	.name = "pcie_pll_dco",	748	.name = "pcie_pll_dco",
704	.ops = &meson_clk_pll_ops,	749	.ops = &meson_clk_pll_ops,
705	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	750	.parent_data = &(const struct clk_parent_data) {
		751	.fw_name = "xtal",
		752	},
706	.num_parents = 1,	753	.num_parents = 1,
707	},	754	},
708	};	755	};
@@ -717,7 +764,9 @@ static struct clk_regmap axg_pcie_pll_od = { · 8 unmodified lines
717	.hw.init = &(struct clk_init_data){	764	.hw.init = &(struct clk_init_data){
718	.name = "pcie_pll_od",	765	.name = "pcie_pll_od",
719	.ops = &clk_regmap_divider_ops,	766	.ops = &clk_regmap_divider_ops,
720	.parent_names = (const char *[]){ "pcie_pll_dco" },	767	.parent_hws = (const struct clk_hw *[]) {
		768	&axg_pcie_pll_dco.hw
		769	},
721	.num_parents = 1,	770	.num_parents = 1,
722	.flags = CLK_SET_RATE_PARENT,	771	.flags = CLK_SET_RATE_PARENT,
723	},	772	},
@@ -733,7 +782,9 @@ static struct clk_regmap axg_pcie_pll = { · 9 unmodified lines
733	.hw.init = &(struct clk_init_data){	782	.hw.init = &(struct clk_init_data){
734	.name = "pcie_pll",	783	.name = "pcie_pll",
735	.ops = &clk_regmap_divider_ops,	784	.ops = &clk_regmap_divider_ops,
736	.parent_names = (const char *[]){ "pcie_pll_od" },	785	.parent_hws = (const struct clk_hw *[]) {
		786	&axg_pcie_pll_od.hw
		787	},
737	.num_parents = 1,	788	.num_parents = 1,
738	.flags = CLK_SET_RATE_PARENT,	789	.flags = CLK_SET_RATE_PARENT,
739	},	790	},
@@ -750,7 +801,7 @@ static struct clk_regmap axg_pcie_mux = { · 10 unmodified lines
750	.hw.init = &(struct clk_init_data){	801	.hw.init = &(struct clk_init_data){
751	.name = "pcie_mux",	802	.name = "pcie_mux",
752	.ops = &clk_regmap_mux_ops,	803	.ops = &clk_regmap_mux_ops,
753	.parent_names = (const char *[]){ "pcie_pll" },	804	.parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
754	.num_parents = 1,	805	.num_parents = 1,
755	.flags = CLK_SET_RATE_PARENT,	806	.flags = CLK_SET_RATE_PARENT,
756	},	807	},
@@ -767,7 +818,7 @@ static struct clk_regmap axg_pcie_ref = { · 10 unmodified lines
767	.hw.init = &(struct clk_init_data){	818	.hw.init = &(struct clk_init_data){
768	.name = "pcie_ref",	819	.name = "pcie_ref",
769	.ops = &clk_regmap_mux_ops,	820	.ops = &clk_regmap_mux_ops,
770	.parent_names = (const char *[]){ "pcie_mux" },	821	.parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
771	.num_parents = 1,	822	.num_parents = 1,
772	.flags = CLK_SET_RATE_PARENT,	823	.flags = CLK_SET_RATE_PARENT,
773	},	824	},
@@ -781,7 +832,7 @@ static struct clk_regmap axg_pcie_cml_en0 = { · 7 unmodified lines
781	.hw.init = &(struct clk_init_data) {	832	.hw.init = &(struct clk_init_data) {
782	.name = "pcie_cml_en0",	833	.name = "pcie_cml_en0",
783	.ops = &clk_regmap_gate_ops,	834	.ops = &clk_regmap_gate_ops,
784	.parent_names = (const char *[]){ "pcie_ref" },	835	.parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
785	.num_parents = 1,	836	.num_parents = 1,
786	.flags = CLK_SET_RATE_PARENT,	837	.flags = CLK_SET_RATE_PARENT,
787		838
@@ -796,16 +847,21 @@ static struct clk_regmap axg_pcie_cml_en1 = { · 8 unmodified lines
796	.hw.init = &(struct clk_init_data) {	847	.hw.init = &(struct clk_init_data) {
797	.name = "pcie_cml_en1",	848	.name = "pcie_cml_en1",
798	.ops = &clk_regmap_gate_ops,	849	.ops = &clk_regmap_gate_ops,
799	.parent_names = (const char *[]){ "pcie_ref" },	850	.parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
800	.num_parents = 1,	851	.num_parents = 1,
801	.flags = CLK_SET_RATE_PARENT,	852	.flags = CLK_SET_RATE_PARENT,
802	},	853	},
803	};	854	};
804		855
805	static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };	856	static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
806	static const char * const clk81_parent_names[] = {	857	static const struct clk_parent_data clk81_parent_data[] = {
807	IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",	858	{ .fw_name = "xtal", },
808	"fclk_div3", "fclk_div5"	859	{ .hw = &axg_fclk_div7.hw },
		860	{ .hw = &axg_mpll1.hw },
		861	{ .hw = &axg_mpll2.hw },
		862	{ .hw = &axg_fclk_div4.hw },
		863	{ .hw = &axg_fclk_div3.hw },
		864	{ .hw = &axg_fclk_div5.hw },
809	};	865	};
810		866
811	static struct clk_regmap axg_mpeg_clk_sel = {	867	static struct clk_regmap axg_mpeg_clk_sel = {
@@ -818,8 +874,8 @@ static struct clk_regmap axg_mpeg_clk_sel = { · 6 unmodified lines
818	.hw.init = &(struct clk_init_data){	874	.hw.init = &(struct clk_init_data){
819	.name = "mpeg_clk_sel",	875	.name = "mpeg_clk_sel",
820	.ops = &clk_regmap_mux_ro_ops,	876	.ops = &clk_regmap_mux_ro_ops,
821	.parent_names = clk81_parent_names,	877	.parent_data = clk81_parent_data,
822	.num_parents = ARRAY_SIZE(clk81_parent_names),	878	.num_parents = ARRAY_SIZE(clk81_parent_data),
823	},	879	},
824	};	880	};
825		881
@@ -832,7 +888,9 @@ static struct clk_regmap axg_mpeg_clk_div = { · 6 unmodified lines
832	.hw.init = &(struct clk_init_data){	888	.hw.init = &(struct clk_init_data){
833	.name = "mpeg_clk_div",	889	.name = "mpeg_clk_div",
834	.ops = &clk_regmap_divider_ops,	890	.ops = &clk_regmap_divider_ops,
835	.parent_names = (const char *[]){ "mpeg_clk_sel" },	891	.parent_hws = (const struct clk_hw *[]) {
		892	&axg_mpeg_clk_sel.hw
		893	},
836	.num_parents = 1,	894	.num_parents = 1,
837	.flags = CLK_SET_RATE_PARENT,	895	.flags = CLK_SET_RATE_PARENT,
838	},	896	},
@@ -846,15 +904,20 @@ static struct clk_regmap axg_clk81 = { · 7 unmodified lines
846	.hw.init = &(struct clk_init_data){	904	.hw.init = &(struct clk_init_data){
847	.name = "clk81",	905	.name = "clk81",
848	.ops = &clk_regmap_gate_ops,	906	.ops = &clk_regmap_gate_ops,
849	.parent_names = (const char *[]){ "mpeg_clk_div" },	907	.parent_hws = (const struct clk_hw *[]) {
		908	&axg_mpeg_clk_div.hw
		909	},
850	.num_parents = 1,	910	.num_parents = 1,
851	.flags = (CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL),	911	.flags = (CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL),
852	},	912	},
853	};	913	};
854		914
855	static const char * const axg_sd_emmc_clk0_parent_names[] = {	915	static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
856	IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",	916	{ .fw_name = "xtal", },
857		917	{ .hw = &axg_fclk_div2.hw },
		918	{ .hw = &axg_fclk_div3.hw },
		919	{ .hw = &axg_fclk_div5.hw },
		920	{ .hw = &axg_fclk_div7.hw },
858	/*	921	/*
859	* Following these parent clocks, we should also have had mpll2, mpll3	922	* Following these parent clocks, we should also have had mpll2, mpll3
860	* and gp0_pll but these clocks are too precious to be used here. All	923	* and gp0_pll but these clocks are too precious to be used here. All
@@ -873,8 +936,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel = { · 12 unmodified lines
873	.hw.init = &(struct clk_init_data) {	936	.hw.init = &(struct clk_init_data) {
874	.name = "sd_emmc_b_clk0_sel",	937	.name = "sd_emmc_b_clk0_sel",
875	.ops = &clk_regmap_mux_ops,	938	.ops = &clk_regmap_mux_ops,
876	.parent_names = axg_sd_emmc_clk0_parent_names,	939	.parent_data = axg_sd_emmc_clk0_parent_data,
877	.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),	940	.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
878	.flags = CLK_SET_RATE_PARENT,	941	.flags = CLK_SET_RATE_PARENT,
879	},	942	},
880	};	943	};
@@ -889,7 +952,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0_div = { · 8 unmodified lines
889	.hw.init = &(struct clk_init_data) {	952	.hw.init = &(struct clk_init_data) {
890	.name = "sd_emmc_b_clk0_div",	953	.name = "sd_emmc_b_clk0_div",
891	.ops = &clk_regmap_divider_ops,	954	.ops = &clk_regmap_divider_ops,
892	.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },	955	.parent_hws = (const struct clk_hw *[]) {
		956	&axg_sd_emmc_b_clk0_sel.hw
		957	},
893	.num_parents = 1,	958	.num_parents = 1,
894	.flags = CLK_SET_RATE_PARENT,	959	.flags = CLK_SET_RATE_PARENT,
895	},	960	},
@@ -903,7 +968,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0 = { · 7 unmodified lines
903	.hw.init = &(struct clk_init_data){	968	.hw.init = &(struct clk_init_data){
904	.name = "sd_emmc_b_clk0",	969	.name = "sd_emmc_b_clk0",
905	.ops = &clk_regmap_gate_ops,	970	.ops = &clk_regmap_gate_ops,
906	.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },	971	.parent_hws = (const struct clk_hw *[]) {
		972	&axg_sd_emmc_b_clk0_div.hw
		973	},
907	.num_parents = 1,	974	.num_parents = 1,
908	.flags = CLK_SET_RATE_PARENT,	975	.flags = CLK_SET_RATE_PARENT,
909	},	976	},
@@ -919,8 +986,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel = { · 9 unmodified lines
919	.hw.init = &(struct clk_init_data) {	986	.hw.init = &(struct clk_init_data) {
920	.name = "sd_emmc_c_clk0_sel",	987	.name = "sd_emmc_c_clk0_sel",
921	.ops = &clk_regmap_mux_ops,	988	.ops = &clk_regmap_mux_ops,
922	.parent_names = axg_sd_emmc_clk0_parent_names,	989	.parent_data = axg_sd_emmc_clk0_parent_data,
923	.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),	990	.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
924	.flags = CLK_SET_RATE_PARENT,	991	.flags = CLK_SET_RATE_PARENT,
925	},	992	},
926	};	993	};
@@ -935,7 +1002,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0_div = { · 8 unmodified lines
935	.hw.init = &(struct clk_init_data) {	1002	.hw.init = &(struct clk_init_data) {
936	.name = "sd_emmc_c_clk0_div",	1003	.name = "sd_emmc_c_clk0_div",
937	.ops = &clk_regmap_divider_ops,	1004	.ops = &clk_regmap_divider_ops,
938	.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },	1005	.parent_hws = (const struct clk_hw *[]) {
		1006	&axg_sd_emmc_c_clk0_sel.hw
		1007	},
939	.num_parents = 1,	1008	.num_parents = 1,
940	.flags = CLK_SET_RATE_PARENT,	1009	.flags = CLK_SET_RATE_PARENT,
941	},	1010	},
@@ -949,7 +1018,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = { · 7 unmodified lines
949	.hw.init = &(struct clk_init_data){	1018	.hw.init = &(struct clk_init_data){
950	.name = "sd_emmc_c_clk0",	1019	.name = "sd_emmc_c_clk0",
951	.ops = &clk_regmap_gate_ops,	1020	.ops = &clk_regmap_gate_ops,
952	.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },	1021	.parent_hws = (const struct clk_hw *[]) {
		1022	&axg_sd_emmc_c_clk0_div.hw
		1023	},
953	.num_parents = 1,	1024	.num_parents = 1,
954	.flags = CLK_SET_RATE_PARENT,	1025	.flags = CLK_SET_RATE_PARENT,
955	},	1026	},
@@ -957,9 +1028,18 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = { · 1 unmodified line
957		1028
958	static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,	1029	static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
959	9, 10, 11, 13, 14, };	1030	9, 10, 11, 13, 14, };
960	static const char * const gen_clk_parent_names[] = {	1031	static const struct clk_parent_data gen_clk_parent_data[] = {
961	IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",	1032	{ .fw_name = "xtal", },
962	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",	1033	{ .hw = &axg_hifi_pll.hw },
		1034	{ .hw = &axg_mpll0.hw },
		1035	{ .hw = &axg_mpll1.hw },
		1036	{ .hw = &axg_mpll2.hw },
		1037	{ .hw = &axg_mpll3.hw },
		1038	{ .hw = &axg_fclk_div4.hw },
		1039	{ .hw = &axg_fclk_div3.hw },
		1040	{ .hw = &axg_fclk_div5.hw },
		1041	{ .hw = &axg_fclk_div7.hw },
		1042	{ .hw = &axg_gp0_pll.hw },
963	};	1043	};
964		1044
965	static struct clk_regmap axg_gen_clk_sel = {	1045	static struct clk_regmap axg_gen_clk_sel = {
@@ -978,8 +1058,8 @@ static struct clk_regmap axg_gen_clk_sel = { · 12 unmodified lines
978	* hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,	1058	* hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
979	* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll	1059	* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
980	*/	1060	*/
981	.parent_names = gen_clk_parent_names,	1061	.parent_data = gen_clk_parent_data,
982	.num_parents = ARRAY_SIZE(gen_clk_parent_names),	1062	.num_parents = ARRAY_SIZE(gen_clk_parent_data),
983	},	1063	},
984	};	1064	};
985		1065
@@ -992,7 +1072,9 @@ static struct clk_regmap axg_gen_clk_div = { · 6 unmodified lines
992	.hw.init = &(struct clk_init_data){	1072	.hw.init = &(struct clk_init_data){
993	.name = "gen_clk_div",	1073	.name = "gen_clk_div",
994	.ops = &clk_regmap_divider_ops,	1074	.ops = &clk_regmap_divider_ops,
995	.parent_names = (const char *[]){ "gen_clk_sel" },	1075	.parent_hws = (const struct clk_hw *[]) {
		1076	&axg_gen_clk_sel.hw
		1077	},
996	.num_parents = 1,	1078	.num_parents = 1,
997	.flags = CLK_SET_RATE_PARENT,	1079	.flags = CLK_SET_RATE_PARENT,
998	},	1080	},
@@ -1006,12 +1088,17 @@ static struct clk_regmap axg_gen_clk = { · 7 unmodified lines
1006	.hw.init = &(struct clk_init_data){	1088	.hw.init = &(struct clk_init_data){
1007	.name = "gen_clk",	1089	.name = "gen_clk",
1008	.ops = &clk_regmap_gate_ops,	1090	.ops = &clk_regmap_gate_ops,
1009	.parent_names = (const char *[]){ "gen_clk_div" },	1091	.parent_hws = (const struct clk_hw *[]) {
		1092	&axg_gen_clk_div.hw
		1093	},
1010	.num_parents = 1,	1094	.num_parents = 1,
1011	.flags = CLK_SET_RATE_PARENT,	1095	.flags = CLK_SET_RATE_PARENT,
1012	},	1096	},
1013	};	1097	};
1014		1098
		1099	#define MESON_GATE(_name, _reg, _bit) \
		1100	MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
		1101
1015	/* Everything Else (EE) domain gates */	1102	/* Everything Else (EE) domain gates */
1016	static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);	1103	static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1017	static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);	1104	static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);

drivers/clk/meson/clk-cpu-dyndiv.c+73−0

@@ -0,0 +1,73 @@
	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS.
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	*/
	6
	7	#include <linux/clk-provider.h>
	8	#include <linux/module.h>
	9
	10	#include "clk-regmap.h"
	11	#include "clk-cpu-dyndiv.h"
	12
	13	static inline struct meson_clk_cpu_dyndiv_data *
	14	meson_clk_cpu_dyndiv_data(struct clk_regmap *clk)
	15	{
	16	return (struct meson_clk_cpu_dyndiv_data *)clk->data;
	17	}
	18
	19	static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
	20	unsigned long prate)
	21	{
	22	struct clk_regmap *clk = to_clk_regmap(hw);
	23	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
	24
	25	return divider_recalc_rate(hw, prate,
	26	meson_parm_read(clk->map, &data->div),
	27	NULL, 0, data->div.width);
	28	}
	29
	30	static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
	31	unsigned long rate,
	32	unsigned long *prate)
	33	{
	34	struct clk_regmap *clk = to_clk_regmap(hw);
	35	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
	36
	37	return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
	38	}
	39
	40	static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
	41	unsigned long parent_rate)
	42	{
	43	struct clk_regmap *clk = to_clk_regmap(hw);
	44	struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
	45	unsigned int val;
	46	int ret;
	47
	48	ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);
	49	if (ret < 0)
	50	return ret;
	51
	52	val = (unsigned int)ret << data->div.shift;
	53
	54	/* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */
	55	meson_parm_write(clk->map, &data->dyn, 1);
	56
	57	/* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */
	58	return regmap_update_bits(clk->map, data->div.reg_off,
	59	SETPMASK(data->div.width, data->div.shift) \|
	60	SETPMASK(data->dyn.width, data->dyn.shift),
	61	val);
	62	};
	63
	64	const struct clk_ops meson_clk_cpu_dyndiv_ops = {
	65	.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
	66	.round_rate = meson_clk_cpu_dyndiv_round_rate,
	67	.set_rate = meson_clk_cpu_dyndiv_set_rate,
	68	};
	69	EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
	70
	71	MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider");
	72	MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
	73	MODULE_LICENSE("GPL v2");

drivers/clk/meson/clk-cpu-dyndiv.h+20−0

@@ -0,0 +1,20 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2019 BayLibre, SAS.
	4	* Author: Neil Armstrong <narmstrong@baylibre.com>
	5	*/
	6
	7	#ifndef __MESON_CLK_CPU_DYNDIV_H
	8	#define __MESON_CLK_CPU_DYNDIV_H
	9
	10	#include <linux/clk-provider.h>
	11	#include "parm.h"
	12
	13	struct meson_clk_cpu_dyndiv_data {
	14	struct parm div;
	15	struct parm dyn;
	16	};
	17
	18	extern const struct clk_ops meson_clk_cpu_dyndiv_ops;
	19
	20	#endif /* __MESON_CLK_CPU_DYNDIV_H */

drivers/clk/meson/clk-input.c+0−49

@@ -1,49 +0,0 @@
1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2	/*
3	* Copyright (c) 2018 BayLibre, SAS.
4	* Author: Jerome Brunet <jbrunet@baylibre.com>
5	*/
6
7	#include <linux/clk.h>
8	#include <linux/clk-provider.h>
9	#include <linux/device.h>
10	#include <linux/module.h>
11	#include "clk-input.h"
12
13	static const struct clk_ops meson_clk_no_ops = {};
14
15	struct clk_hw meson_clk_hw_register_input(struct device dev,
16	const char *of_name,
17	const char *clk_name,
18	unsigned long flags)
19	{
20	struct clk *parent_clk = devm_clk_get(dev, of_name);
21	struct clk_init_data init;
22	const char *parent_name;
23	struct clk_hw *hw;
24	int ret;
25
26	if (IS_ERR(parent_clk))
27	return (struct clk_hw *)parent_clk;
28
29	hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
30	if (!hw)
31	return ERR_PTR(-ENOMEM);
32
33	parent_name = __clk_get_name(parent_clk);
34	init.name = clk_name;
35	init.ops = &meson_clk_no_ops;
36	init.flags = flags;
37	init.parent_names = &parent_name;
38	init.num_parents = 1;
39	hw->init = &init;
40
41	ret = devm_clk_hw_register(dev, hw);
42
43	return ret ? ERR_PTR(ret) : hw;
44	}
45	EXPORT_SYMBOL_GPL(meson_clk_hw_register_input);
46
47	MODULE_DESCRIPTION("Amlogic clock input helper");
48	MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
49	MODULE_LICENSE("GPL v2");

drivers/clk/meson/clk-input.h+0−19

@@ -1,19 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0 */
2	/*
3	* Copyright (c) 2019 BayLibre, SAS.
4	* Author: Jerome Brunet <jbrunet@baylibre.com>
5	*/
6
7	#ifndef __MESON_CLK_INPUT_H
8	#define __MESON_CLK_INPUT_H
9
10	#include <linux/clk-provider.h>
11
12	struct device;
13
14	struct clk_hw meson_clk_hw_register_input(struct device dev,
15	const char *of_name,
16	const char *clk_name,
17	unsigned long flags);
18
19	#endif /* __MESON_CLK_INPUT_H */

drivers/clk/meson/clk-regmap.h+6−6

@@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) · 110 unmodified lines
111	extern const struct clk_ops clk_regmap_mux_ops;	111	extern const struct clk_ops clk_regmap_mux_ops;
112	extern const struct clk_ops clk_regmap_mux_ro_ops;	112	extern const struct clk_ops clk_regmap_mux_ro_ops;
113		113
114	#define __MESON_GATE(_name, _reg, _bit, _ops) \	114	#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \
115	struct clk_regmap _name = { \	115	struct clk_regmap _name = { \
116	.data = &(struct clk_regmap_gate_data){ \	116	.data = &(struct clk_regmap_gate_data){ \
117	.offset = (_reg), \	117	.offset = (_reg), \
@@ -120,15 +120,15 @@ struct clk_regmap _name = { \ · 2 unmodified lines
120	.hw.init = &(struct clk_init_data) { \	120	.hw.init = &(struct clk_init_data) { \
121	.name = #_name, \	121	.name = #_name, \
122	.ops = _ops, \	122	.ops = _ops, \
123	.parent_names = (const char *[]){ "clk81" }, \	123	.parent_hws = (const struct clk_hw *[]) { _pname }, \
124	.num_parents = 1, \	124	.num_parents = 1, \
125	.flags = (CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED), \	125	.flags = (CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED), \
126	}, \	126	}, \
127	}	127	}
128		128
129	#define MESON_GATE(_name, _reg, _bit) \	129	#define MESON_PCLK(_name, _reg, _bit, _pname) \
130	__MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ops)	130	__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
131		131
132	#define MESON_GATE_RO(_name, _reg, _bit) \	132	#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \
133	__MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ro_ops)	133	__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
134	#endif /* __CLK_REGMAP_H */	134	#endif /* __CLK_REGMAP_H */

drivers/clk/meson/g12a-aoclk.c+50−31

 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
-#define IN_PREFIX "ao-in-"
 /*
  * AO Configuration Clock registers offsets
  * Register offsets from the data sheet must be multiplied by 4.
 	.hw.init = &(struct clk_init_data) {				\
 		.name =  "g12a_ao_" #_name,				\
 		.ops = &clk_regmap_gate_ops,				\
-		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+		.parent_data = &(const struct clk_parent_data) {	\
+			.fw_name = "mpeg-clk",				\
+		},							\
 		.num_parents = 1,					\
 		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_oscin",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "xtal",
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_32k_by_oscin_pre",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "cts_oscin" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_cts_oscin.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_32k_by_oscin_div",
 		.ops = &meson_clk_dualdiv_ops,
-		.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_pre" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_32k_by_oscin_pre.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_32k_by_oscin_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_div",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "g12a_ao_32k_by_oscin_pre" },
+			&g12a_aoclk_32k_by_oscin_div.hw,
+			&g12a_aoclk_32k_by_oscin_pre.hw,
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_32k_by_oscin",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_32k_by_oscin_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_cec_pre",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "cts_oscin" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_cts_oscin.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_cec_div",
 		.ops = &meson_clk_dualdiv_ops,
-		.parent_names = (const char *[]){ "g12a_ao_cec_pre" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_cec_pre.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_cec_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "g12a_ao_cec_div",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "g12a_ao_cec_pre" },
+			&g12a_aoclk_cec_div.hw,
+			&g12a_aoclk_cec_pre.hw,
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_cec",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "g12a_ao_cec_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_cec_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_cts_rtc_oscin",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "g12a_ao_32k_by_oscin",
+		.parent_data = (const struct clk_parent_data []) {
-						  IN_PREFIX "ext_32k-0" },
+			{ .hw = &g12a_aoclk_32k_by_oscin.hw },
+			{ .fw_name = "ext-32k-0", },
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_clk81",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
+		.parent_data = (const struct clk_parent_data []) {
-						  "g12a_ao_cts_rtc_oscin"},
+			{ .fw_name = "mpeg-clk", },
+			{ .hw = &g12a_aoclk_cts_rtc_oscin.hw },
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_saradc_mux",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "xtal",
+		.parent_data = (const struct clk_parent_data []) {
-						  "g12a_ao_clk81" },
+			{ .fw_name = "xtal", },
+			{ .hw = &g12a_aoclk_clk81.hw },
+		},
 		.num_parents = 2,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_saradc_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "g12a_ao_saradc_mux" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_saradc_mux.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "g12a_ao_saradc_gate",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "g12a_ao_saradc_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&g12a_aoclk_saradc_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.num = NR_CLKS,
 };
-static const struct meson_aoclk_input g12a_aoclk_inputs[] = {
-	{ .name = "xtal",	.required = true  },
-	{ .name = "mpeg-clk",	.required = true  },
-	{ .name = "ext-32k-0",	.required = false },
-};
 static const struct meson_aoclk_data g12a_aoclkc_data = {
 	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
 	.num_reset	= ARRAY_SIZE(g12a_aoclk_reset),
 	.num_clks	= ARRAY_SIZE(g12a_aoclk_regmap),
 	.clks		= g12a_aoclk_regmap,
 	.hw_data	= &g12a_aoclk_onecell_data,
-	.inputs		= g12a_aoclk_inputs,
-	.num_inputs	= ARRAY_SIZE(g12a_aoclk_inputs),
-	.input_prefix	= IN_PREFIX,
 };
 static const struct of_device_id g12a_aoclkc_match_table[] = {

drivers/clk/meson/g12a.c+1179−447

@@ -14,11 +14,12 @@ · 13 unmodified lines
14	#include <linux/init.h>	14	#include <linux/init.h>
15	#include <linux/of_device.h>	15	#include <linux/of_device.h>
16	#include <linux/platform_device.h>	16	#include <linux/platform_device.h>
		17	#include <linux/clk.h>
17		18
18	#include "clk-input.h"
19	#include "clk-mpll.h"	19	#include "clk-mpll.h"
20	#include "clk-pll.h"	20	#include "clk-pll.h"
21	#include "clk-regmap.h"	21	#include "clk-regmap.h"
		22	#include "clk-cpu-dyndiv.h"
22	#include "vid-pll-div.h"	23	#include "vid-pll-div.h"
23	#include "meson-eeclk.h"	24	#include "meson-eeclk.h"
24	#include "g12a.h"	25	#include "g12a.h"
@@ -61,7 +62,9 @@ static struct clk_regmap g12a_fixed_pll_dco = { · 36 unmodified lines
61	.hw.init = &(struct clk_init_data){	62	.hw.init = &(struct clk_init_data){
62	.name = "fixed_pll_dco",	63	.name = "fixed_pll_dco",
63	.ops = &meson_clk_pll_ro_ops,	64	.ops = &meson_clk_pll_ro_ops,
64	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	65	.parent_data = &(const struct clk_parent_data) {
		66	.fw_name = "xtal",
		67	},
65	.num_parents = 1,	68	.num_parents = 1,
66	},	69	},
67	};	70	};
@@ -76,7 +79,9 @@ static struct clk_regmap g12a_fixed_pll = { · 8 unmodified lines
76	.hw.init = &(struct clk_init_data){	79	.hw.init = &(struct clk_init_data){
77	.name = "fixed_pll",	80	.name = "fixed_pll",
78	.ops = &clk_regmap_divider_ro_ops,	81	.ops = &clk_regmap_divider_ro_ops,
79	.parent_names = (const char *[]){ "fixed_pll_dco" },	82	.parent_hws = (const struct clk_hw *[]) {
		83	&g12a_fixed_pll_dco.hw
		84	},
80	.num_parents = 1,	85	.num_parents = 1,
81	/*	86	/*
82	* This clock won't ever change at runtime so	87	* This clock won't ever change at runtime so
@@ -85,16 +90,9 @@ static struct clk_regmap g12a_fixed_pll = { · 2 unmodified lines
85	},	90	},
86	};	91	};
87		92
88	/*	93	static const struct pll_mult_range g12a_sys_pll_mult_range = {
89	* Internal sys pll emulation configuration parameters	94	.min = 128,
90	*/	95	.max = 250,
91	static const struct reg_sequence g12a_sys_init_regs[] = {
92	{ .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 },
93	{ .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 },
94	{ .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
95	{ .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
96	{ .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
97	{ .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 },
98	};	96	};
99		97
100	static struct clk_regmap g12a_sys_pll_dco = {	98	static struct clk_regmap g12a_sys_pll_dco = {
@@ -124,14 +122,17 @@ static struct clk_regmap g12a_sys_pll_dco = { · 23 unmodified lines
124	.shift = 29,	122	.shift = 29,
125	.width = 1,	123	.width = 1,
126	},	124	},
127	.init_regs = g12a_sys_init_regs,	125	.range = &g12a_sys_pll_mult_range,
128	.init_count = ARRAY_SIZE(g12a_sys_init_regs),
129	},	126	},
130	.hw.init = &(struct clk_init_data){	127	.hw.init = &(struct clk_init_data){
131	.name = "sys_pll_dco",	128	.name = "sys_pll_dco",
132	.ops = &meson_clk_pll_ro_ops,	129	.ops = &meson_clk_pll_ops,
133	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	130	.parent_data = &(const struct clk_parent_data) {
		131	.fw_name = "xtal",
		132	},
134	.num_parents = 1,	133	.num_parents = 1,
		134	/* This clock feeds the CPU, avoid disabling it */
		135	.flags = CLK_IS_CRITICAL,
135	},	136	},
136	};	137	};
137		138
@@ -144,9 +145,12 @@ static struct clk_regmap g12a_sys_pll = { · 6 unmodified lines
144	},	145	},
145	.hw.init = &(struct clk_init_data){	146	.hw.init = &(struct clk_init_data){
146	.name = "sys_pll",	147	.name = "sys_pll",
147	.ops = &clk_regmap_divider_ro_ops,	148	.ops = &clk_regmap_divider_ops,
148	.parent_names = (const char *[]){ "sys_pll_dco" },	149	.parent_hws = (const struct clk_hw *[]) {
		150	&g12a_sys_pll_dco.hw
		151	},
149	.num_parents = 1,	152	.num_parents = 1,
		153	.flags = CLK_SET_RATE_PARENT,
150	},	154	},
151	};	155	};
152		156
@@ -177,12 +181,17 @@ static struct clk_regmap g12b_sys1_pll_dco = { · 24 unmodified lines
177	.shift = 29,	181	.shift = 29,
178	.width = 1,	182	.width = 1,
179	},	183	},
		184	.range = &g12a_sys_pll_mult_range,
180	},	185	},
181	.hw.init = &(struct clk_init_data){	186	.hw.init = &(struct clk_init_data){
182	.name = "sys1_pll_dco",	187	.name = "sys1_pll_dco",
183	.ops = &meson_clk_pll_ro_ops,	188	.ops = &meson_clk_pll_ops,
184	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	189	.parent_data = &(const struct clk_parent_data) {
		190	.fw_name = "xtal",
		191	},
185	.num_parents = 1,	192	.num_parents = 1,
		193	/* This clock feeds the CPU, avoid disabling it */
		194	.flags = CLK_IS_CRITICAL,
186	},	195	},
187	};	196	};
188		197
@@ -195,9 +204,12 @@ static struct clk_regmap g12b_sys1_pll = { · 6 unmodified lines
195	},	204	},
196	.hw.init = &(struct clk_init_data){	205	.hw.init = &(struct clk_init_data){
197	.name = "sys1_pll",	206	.name = "sys1_pll",
198	.ops = &clk_regmap_divider_ro_ops,	207	.ops = &clk_regmap_divider_ops,
199	.parent_names = (const char *[]){ "sys1_pll_dco" },	208	.parent_hws = (const struct clk_hw *[]) {
		209	&g12b_sys1_pll_dco.hw
		210	},
200	.num_parents = 1,	211	.num_parents = 1,
		212	.flags = CLK_SET_RATE_PARENT,
201	},	213	},
202	};	214	};
203		215
@@ -209,7 +221,7 @@ static struct clk_regmap g12a_sys_pll_div16_en = { · 5 unmodified lines
209	.hw.init = &(struct clk_init_data) {	221	.hw.init = &(struct clk_init_data) {
210	.name = "sys_pll_div16_en",	222	.name = "sys_pll_div16_en",
211	.ops = &clk_regmap_gate_ro_ops,	223	.ops = &clk_regmap_gate_ro_ops,
212	.parent_names = (const char *[]){ "sys_pll" },	224	.parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
213	.num_parents = 1,	225	.num_parents = 1,
214	/*	226	/*
215	* This clock is used to debug the sys_pll range	227	* This clock is used to debug the sys_pll range
@@ -226,7 +238,9 @@ static struct clk_regmap g12b_sys1_pll_div16_en = { · 10 unmodified lines
226	.hw.init = &(struct clk_init_data) {	238	.hw.init = &(struct clk_init_data) {
227	.name = "sys1_pll_div16_en",	239	.name = "sys1_pll_div16_en",
228	.ops = &clk_regmap_gate_ro_ops,	240	.ops = &clk_regmap_gate_ro_ops,
229	.parent_names = (const char *[]){ "sys1_pll" },	241	.parent_hws = (const struct clk_hw *[]) {
		242	&g12b_sys1_pll.hw
		243	},
230	.num_parents = 1,	244	.num_parents = 1,
231	/*	245	/*
232	* This clock is used to debug the sys_pll range	246	* This clock is used to debug the sys_pll range
@@ -241,7 +255,9 @@ static struct clk_fixed_factor g12a_sys_pll_div16 = { · 8 unmodified lines
241	.hw.init = &(struct clk_init_data){	255	.hw.init = &(struct clk_init_data){
242	.name = "sys_pll_div16",	256	.name = "sys_pll_div16",
243	.ops = &clk_fixed_factor_ops,	257	.ops = &clk_fixed_factor_ops,
244	.parent_names = (const char *[]){ "sys_pll_div16_en" },	258	.parent_hws = (const struct clk_hw *[]) {
		259	&g12a_sys_pll_div16_en.hw
		260	},
245	.num_parents = 1,	261	.num_parents = 1,
246	},	262	},
247	};	263	};
@@ -252,11 +268,75 @@ static struct clk_fixed_factor g12b_sys1_pll_div16 = { · 4 unmodified lines
252	.hw.init = &(struct clk_init_data){	268	.hw.init = &(struct clk_init_data){
253	.name = "sys1_pll_div16",	269	.name = "sys1_pll_div16",
254	.ops = &clk_fixed_factor_ops,	270	.ops = &clk_fixed_factor_ops,
255	.parent_names = (const char *[]){ "sys1_pll_div16_en" },	271	.parent_hws = (const struct clk_hw *[]) {
		272	&g12b_sys1_pll_div16_en.hw
		273	},
		274	.num_parents = 1,
		275	},
		276	};
		277
		278	static struct clk_fixed_factor g12a_fclk_div2_div = {
		279	.mult = 1,
		280	.div = 2,
		281	.hw.init = &(struct clk_init_data){
		282	.name = "fclk_div2_div",
		283	.ops = &clk_fixed_factor_ops,
		284	.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
		285	.num_parents = 1,
		286	},
		287	};
		288
		289	static struct clk_regmap g12a_fclk_div2 = {
		290	.data = &(struct clk_regmap_gate_data){
		291	.offset = HHI_FIX_PLL_CNTL1,
		292	.bit_idx = 24,
		293	},
		294	.hw.init = &(struct clk_init_data){
		295	.name = "fclk_div2",
		296	.ops = &clk_regmap_gate_ops,
		297	.parent_hws = (const struct clk_hw *[]) {
		298	&g12a_fclk_div2_div.hw
		299	},
256	.num_parents = 1,	300	.num_parents = 1,
257	},	301	},
258	};	302	};
259		303
		304	static struct clk_fixed_factor g12a_fclk_div3_div = {
		305	.mult = 1,
		306	.div = 3,
		307	.hw.init = &(struct clk_init_data){
		308	.name = "fclk_div3_div",
		309	.ops = &clk_fixed_factor_ops,
		310	.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
		311	.num_parents = 1,
		312	},
		313	};
		314
		315	static struct clk_regmap g12a_fclk_div3 = {
		316	.data = &(struct clk_regmap_gate_data){
		317	.offset = HHI_FIX_PLL_CNTL1,
		318	.bit_idx = 20,
		319	},
		320	.hw.init = &(struct clk_init_data){
		321	.name = "fclk_div3",
		322	.ops = &clk_regmap_gate_ops,
		323	.parent_hws = (const struct clk_hw *[]) {
		324	&g12a_fclk_div3_div.hw
		325	},
		326	.num_parents = 1,
		327	/*
		328	* This clock is used by the resident firmware and is required
		329	* by the platform to operate correctly.
		330	* Until the following condition are met, we need this clock to
		331	* be marked as critical:
		332	* a) Mark the clock used by a firmware resource, if possible
		333	* b) CCF has a clock hand-off mechanism to make the sure the
		334	* clock stays on until the proper driver comes along
		335	*/
		336	.flags = CLK_IS_CRITICAL,
		337	},
		338	};
		339
260	/* Datasheet names this field as "premux0" */	340	/* Datasheet names this field as "premux0" */
261	static struct clk_regmap g12a_cpu_clk_premux0 = {	341	static struct clk_regmap g12a_cpu_clk_premux0 = {
262	.data = &(struct clk_regmap_mux_data){	342	.data = &(struct clk_regmap_mux_data){
@@ -266,26 +346,61 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { · 3 unmodified lines
266	},	346	},
267	.hw.init = &(struct clk_init_data){	347	.hw.init = &(struct clk_init_data){
268	.name = "cpu_clk_dyn0_sel",	348	.name = "cpu_clk_dyn0_sel",
269	.ops = &clk_regmap_mux_ro_ops,	349	.ops = &clk_regmap_mux_ops,
270	.parent_names = (const char *[]){ IN_PREFIX "xtal",	350	.parent_data = (const struct clk_parent_data []) {
271	"fclk_div2",	351	{ .fw_name = "xtal", },
272	"fclk_div3" },	352	{ .hw = &g12a_fclk_div2.hw },
		353	{ .hw = &g12a_fclk_div3.hw },
		354	},
273	.num_parents = 3,	355	.num_parents = 3,
		356	/* This sub-tree is used a parking clock */
		357	.flags = CLK_SET_RATE_NO_REPARENT,
		358	},
		359	};
		360
		361	/* Datasheet names this field as "premux1" */
		362	static struct clk_regmap g12a_cpu_clk_premux1 = {
		363	.data = &(struct clk_regmap_mux_data){
		364	.offset = HHI_SYS_CPU_CLK_CNTL0,
		365	.mask = 0x3,
		366	.shift = 16,
		367	},
		368	.hw.init = &(struct clk_init_data){
		369	.name = "cpu_clk_dyn1_sel",
		370	.ops = &clk_regmap_mux_ops,
		371	.parent_data = (const struct clk_parent_data []) {
		372	{ .fw_name = "xtal", },
		373	{ .hw = &g12a_fclk_div2.hw },
		374	{ .hw = &g12a_fclk_div3.hw },
		375	},
		376	.num_parents = 3,
		377	/* This sub-tree is used a parking clock */
		378	.flags = CLK_SET_RATE_NO_REPARENT
274	},	379	},
275	};	380	};
276		381
277	/* Datasheet names this field as "mux0_divn_tcnt" */	382	/* Datasheet names this field as "mux0_divn_tcnt" */
278	static struct clk_regmap g12a_cpu_clk_mux0_div = {	383	static struct clk_regmap g12a_cpu_clk_mux0_div = {
279	.data = &(struct clk_regmap_div_data){	384	.data = &(struct meson_clk_cpu_dyndiv_data){
280	.offset = HHI_SYS_CPU_CLK_CNTL0,	385	.div = {
281	.shift = 4,	386	.reg_off = HHI_SYS_CPU_CLK_CNTL0,
282	.width = 6,	387	.shift = 4,
		388	.width = 6,
		389	},
		390	.dyn = {
		391	.reg_off = HHI_SYS_CPU_CLK_CNTL0,
		392	.shift = 26,
		393	.width = 1,
		394	},
283	},	395	},
284	.hw.init = &(struct clk_init_data){	396	.hw.init = &(struct clk_init_data){
285	.name = "cpu_clk_dyn0_div",	397	.name = "cpu_clk_dyn0_div",
286	.ops = &clk_regmap_divider_ro_ops,	398	.ops = &meson_clk_cpu_dyndiv_ops,
287	.parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },	399	.parent_hws = (const struct clk_hw *[]) {
		400	&g12a_cpu_clk_premux0.hw
		401	},
288	.num_parents = 1,	402	.num_parents = 1,
		403	.flags = CLK_SET_RATE_PARENT,
289	},	404	},
290	};	405	};
291		406
@@ -298,27 +413,13 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { · 6 unmodified lines
298	},	413	},
299	.hw.init = &(struct clk_init_data){	414	.hw.init = &(struct clk_init_data){
300	.name = "cpu_clk_dyn0",	415	.name = "cpu_clk_dyn0",
301	.ops = &clk_regmap_mux_ro_ops,	416	.ops = &clk_regmap_mux_ops,
302	.parent_names = (const char *[]){ "cpu_clk_dyn0_sel",	417	.parent_hws = (const struct clk_hw *[]) {
303	"cpu_clk_dyn0_div" },	418	&g12a_cpu_clk_premux0.hw,
		419	&g12a_cpu_clk_mux0_div.hw,
		420	},
304	.num_parents = 2,	421	.num_parents = 2,
305	},	422	.flags = CLK_SET_RATE_PARENT,
306	};
307
308	/* Datasheet names this field as "premux1" */
309	static struct clk_regmap g12a_cpu_clk_premux1 = {
310	.data = &(struct clk_regmap_mux_data){
311	.offset = HHI_SYS_CPU_CLK_CNTL0,
312	.mask = 0x3,
313	.shift = 16,
314	},
315	.hw.init = &(struct clk_init_data){
316	.name = "cpu_clk_dyn1_sel",
317	.ops = &clk_regmap_mux_ro_ops,
318	.parent_names = (const char *[]){ IN_PREFIX "xtal",
319	"fclk_div2",
320	"fclk_div3" },
321	.num_parents = 3,
322	},	423	},
323	};	424	};
324		425
@@ -332,7 +433,9 @@ static struct clk_regmap g12a_cpu_clk_mux1_div = { · 7 unmodified lines
332	.hw.init = &(struct clk_init_data){	433	.hw.init = &(struct clk_init_data){
333	.name = "cpu_clk_dyn1_div",	434	.name = "cpu_clk_dyn1_div",
334	.ops = &clk_regmap_divider_ro_ops,	435	.ops = &clk_regmap_divider_ro_ops,
335	.parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },	436	.parent_hws = (const struct clk_hw *[]) {
		437	&g12a_cpu_clk_premux1.hw
		438	},
336	.num_parents = 1,	439	.num_parents = 1,
337	},	440	},
338	};	441	};
@@ -346,10 +449,14 @@ static struct clk_regmap g12a_cpu_clk_postmux1 = { · 7 unmodified lines
346	},	449	},
347	.hw.init = &(struct clk_init_data){	450	.hw.init = &(struct clk_init_data){
348	.name = "cpu_clk_dyn1",	451	.name = "cpu_clk_dyn1",
349	.ops = &clk_regmap_mux_ro_ops,	452	.ops = &clk_regmap_mux_ops,
350	.parent_names = (const char *[]){ "cpu_clk_dyn1_sel",	453	.parent_hws = (const struct clk_hw *[]) {
351	"cpu_clk_dyn1_div" },	454	&g12a_cpu_clk_premux1.hw,
		455	&g12a_cpu_clk_mux1_div.hw,
		456	},
352	.num_parents = 2,	457	.num_parents = 2,
		458	/* This sub-tree is used a parking clock */
		459	.flags = CLK_SET_RATE_NO_REPARENT,
353	},	460	},
354	};	461	};
355		462
@@ -362,10 +469,13 @@ static struct clk_regmap g12a_cpu_clk_dyn = { · 6 unmodified lines
362	},	469	},
363	.hw.init = &(struct clk_init_data){	470	.hw.init = &(struct clk_init_data){
364	.name = "cpu_clk_dyn",	471	.name = "cpu_clk_dyn",
365	.ops = &clk_regmap_mux_ro_ops,	472	.ops = &clk_regmap_mux_ops,
366	.parent_names = (const char *[]){ "cpu_clk_dyn0",	473	.parent_hws = (const struct clk_hw *[]) {
367	"cpu_clk_dyn1" },	474	&g12a_cpu_clk_postmux0.hw,
		475	&g12a_cpu_clk_postmux1.hw,
		476	},
368	.num_parents = 2,	477	.num_parents = 2,
		478	.flags = CLK_SET_RATE_PARENT,
369	},	479	},
370	};	480	};
371		481
@@ -378,10 +488,13 @@ static struct clk_regmap g12a_cpu_clk = { · 6 unmodified lines
378	},	488	},
379	.hw.init = &(struct clk_init_data){	489	.hw.init = &(struct clk_init_data){
380	.name = "cpu_clk",	490	.name = "cpu_clk",
381	.ops = &clk_regmap_mux_ro_ops,	491	.ops = &clk_regmap_mux_ops,
382	.parent_names = (const char *[]){ "cpu_clk_dyn",	492	.parent_hws = (const struct clk_hw *[]) {
383	"sys_pll" },	493	&g12a_cpu_clk_dyn.hw,
		494	&g12a_sys_pll.hw,
		495	},
384	.num_parents = 2,	496	.num_parents = 2,
		497	.flags = CLK_SET_RATE_PARENT,
385	},	498	},
386	};	499	};
387		500
@@ -394,10 +507,13 @@ static struct clk_regmap g12b_cpu_clk = { · 6 unmodified lines
394	},	507	},
395	.hw.init = &(struct clk_init_data){	508	.hw.init = &(struct clk_init_data){
396	.name = "cpu_clk",	509	.name = "cpu_clk",
397	.ops = &clk_regmap_mux_ro_ops,	510	.ops = &clk_regmap_mux_ops,
398	.parent_names = (const char *[]){ "cpu_clk_dyn",	511	.parent_hws = (const struct clk_hw *[]) {
399	"sys1_pll" },	512	&g12a_cpu_clk_dyn.hw,
		513	&g12b_sys1_pll.hw
		514	},
400	.num_parents = 2,	515	.num_parents = 2,
		516	.flags = CLK_SET_RATE_PARENT,
401	},	517	},
402	};	518	};
403		519
@@ -410,26 +526,38 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { · 6 unmodified lines
410	},	526	},
411	.hw.init = &(struct clk_init_data){	527	.hw.init = &(struct clk_init_data){
412	.name = "cpub_clk_dyn0_sel",	528	.name = "cpub_clk_dyn0_sel",
413	.ops = &clk_regmap_mux_ro_ops,	529	.ops = &clk_regmap_mux_ops,
414	.parent_names = (const char *[]){ IN_PREFIX "xtal",	530	.parent_data = (const struct clk_parent_data []) {
415	"fclk_div2",	531	{ .fw_name = "xtal", },
416	"fclk_div3" },	532	{ .hw = &g12a_fclk_div2.hw },
		533	{ .hw = &g12a_fclk_div3.hw },
		534	},
417	.num_parents = 3,	535	.num_parents = 3,
418	},	536	},
419	};	537	};
420		538
421	/* Datasheet names this field as "mux0_divn_tcnt" */	539	/* Datasheet names this field as "mux0_divn_tcnt" */
422	static struct clk_regmap g12b_cpub_clk_mux0_div = {	540	static struct clk_regmap g12b_cpub_clk_mux0_div = {
423	.data = &(struct clk_regmap_div_data){	541	.data = &(struct meson_clk_cpu_dyndiv_data){
424	.offset = HHI_SYS_CPUB_CLK_CNTL,	542	.div = {
425	.shift = 4,	543	.reg_off = HHI_SYS_CPUB_CLK_CNTL,
426	.width = 6,	544	.shift = 4,
		545	.width = 6,
		546	},
		547	.dyn = {
		548	.reg_off = HHI_SYS_CPUB_CLK_CNTL,
		549	.shift = 26,
		550	.width = 1,
		551	},
427	},	552	},
428	.hw.init = &(struct clk_init_data){	553	.hw.init = &(struct clk_init_data){
429	.name = "cpub_clk_dyn0_div",	554	.name = "cpub_clk_dyn0_div",
430	.ops = &clk_regmap_divider_ro_ops,	555	.ops = &meson_clk_cpu_dyndiv_ops,
431	.parent_names = (const char *[]){ "cpub_clk_dyn0_sel" },	556	.parent_hws = (const struct clk_hw *[]) {
		557	&g12b_cpub_clk_premux0.hw
		558	},
432	.num_parents = 1,	559	.num_parents = 1,
		560	.flags = CLK_SET_RATE_PARENT,
433	},	561	},
434	};	562	};
435		563
@@ -442,10 +570,13 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = { · 6 unmodified lines
442	},	570	},
443	.hw.init = &(struct clk_init_data){	571	.hw.init = &(struct clk_init_data){
444	.name = "cpub_clk_dyn0",	572	.name = "cpub_clk_dyn0",
445	.ops = &clk_regmap_mux_ro_ops,	573	.ops = &clk_regmap_mux_ops,
446	.parent_names = (const char *[]){ "cpub_clk_dyn0_sel",	574	.parent_hws = (const struct clk_hw *[]) {
447	"cpub_clk_dyn0_div" },	575	&g12b_cpub_clk_premux0.hw,
		576	&g12b_cpub_clk_mux0_div.hw
		577	},
448	.num_parents = 2,	578	.num_parents = 2,
		579	.flags = CLK_SET_RATE_PARENT,
449	},	580	},
450	};	581	};
451		582
@@ -458,11 +589,15 @@ static struct clk_regmap g12b_cpub_clk_premux1 = { · 6 unmodified lines
458	},	589	},
459	.hw.init = &(struct clk_init_data){	590	.hw.init = &(struct clk_init_data){
460	.name = "cpub_clk_dyn1_sel",	591	.name = "cpub_clk_dyn1_sel",
461	.ops = &clk_regmap_mux_ro_ops,	592	.ops = &clk_regmap_mux_ops,
462	.parent_names = (const char *[]){ IN_PREFIX "xtal",	593	.parent_data = (const struct clk_parent_data []) {
463	"fclk_div2",	594	{ .fw_name = "xtal", },
464	"fclk_div3" },	595	{ .hw = &g12a_fclk_div2.hw },
		596	{ .hw = &g12a_fclk_div3.hw },
		597	},
465	.num_parents = 3,	598	.num_parents = 3,
		599	/* This sub-tree is used a parking clock */
		600	.flags = CLK_SET_RATE_NO_REPARENT,
466	},	601	},
467	};	602	};
468		603
@@ -476,7 +611,9 @@ static struct clk_regmap g12b_cpub_clk_mux1_div = { · 7 unmodified lines
476	.hw.init = &(struct clk_init_data){	611	.hw.init = &(struct clk_init_data){
477	.name = "cpub_clk_dyn1_div",	612	.name = "cpub_clk_dyn1_div",
478	.ops = &clk_regmap_divider_ro_ops,	613	.ops = &clk_regmap_divider_ro_ops,
479	.parent_names = (const char *[]){ "cpub_clk_dyn1_sel" },	614	.parent_hws = (const struct clk_hw *[]) {
		615	&g12b_cpub_clk_premux1.hw
		616	},
480	.num_parents = 1,	617	.num_parents = 1,
481	},	618	},
482	};	619	};
@@ -490,10 +627,14 @@ static struct clk_regmap g12b_cpub_clk_postmux1 = { · 7 unmodified lines
490	},	627	},
491	.hw.init = &(struct clk_init_data){	628	.hw.init = &(struct clk_init_data){
492	.name = "cpub_clk_dyn1",	629	.name = "cpub_clk_dyn1",
493	.ops = &clk_regmap_mux_ro_ops,	630	.ops = &clk_regmap_mux_ops,
494	.parent_names = (const char *[]){ "cpub_clk_dyn1_sel",	631	.parent_hws = (const struct clk_hw *[]) {
495	"cpub_clk_dyn1_div" },	632	&g12b_cpub_clk_premux1.hw,
		633	&g12b_cpub_clk_mux1_div.hw
		634	},
496	.num_parents = 2,	635	.num_parents = 2,
		636	/* This sub-tree is used a parking clock */
		637	.flags = CLK_SET_RATE_NO_REPARENT,
497	},	638	},
498	};	639	};
499		640
@@ -506,10 +647,13 @@ static struct clk_regmap g12b_cpub_clk_dyn = { · 6 unmodified lines
506	},	647	},
507	.hw.init = &(struct clk_init_data){	648	.hw.init = &(struct clk_init_data){
508	.name = "cpub_clk_dyn",	649	.name = "cpub_clk_dyn",
509	.ops = &clk_regmap_mux_ro_ops,	650	.ops = &clk_regmap_mux_ops,
510	.parent_names = (const char *[]){ "cpub_clk_dyn0",	651	.parent_hws = (const struct clk_hw *[]) {
511	"cpub_clk_dyn1" },	652	&g12b_cpub_clk_postmux0.hw,
		653	&g12b_cpub_clk_postmux1.hw
		654	},
512	.num_parents = 2,	655	.num_parents = 2,
		656	.flags = CLK_SET_RATE_PARENT,
513	},	657	},
514	};	658	};
515		659
@@ -522,13 +666,227 @@ static struct clk_regmap g12b_cpub_clk = { · 6 unmodified lines
522	},	666	},
523	.hw.init = &(struct clk_init_data){	667	.hw.init = &(struct clk_init_data){
524	.name = "cpub_clk",	668	.name = "cpub_clk",
525	.ops = &clk_regmap_mux_ro_ops,	669	.ops = &clk_regmap_mux_ops,
526	.parent_names = (const char *[]){ "cpub_clk_dyn",	670	.parent_hws = (const struct clk_hw *[]) {
527	"sys_pll" },	671	&g12b_cpub_clk_dyn.hw,
		672	&g12a_sys_pll.hw
		673	},
528	.num_parents = 2,	674	.num_parents = 2,
		675	.flags = CLK_SET_RATE_PARENT,
529	},	676	},
530	};	677	};
531		678
		679	static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
		680	unsigned long event, void *data)
		681	{
		682	if (event == POST_RATE_CHANGE \|\| event == PRE_RATE_CHANGE) {
		683	/* Wait for clock propagation before/after changing the mux */
		684	udelay(100);
		685	return NOTIFY_OK;
		686	}
		687
		688	return NOTIFY_DONE;
		689	}
		690
		691	static struct notifier_block g12a_cpu_clk_mux_nb = {
		692	.notifier_call = g12a_cpu_clk_mux_notifier_cb,
		693	};
		694
		695	struct g12a_cpu_clk_postmux_nb_data {
		696	struct notifier_block nb;
		697	struct clk_hw *xtal;
		698	struct clk_hw *cpu_clk_dyn;
		699	struct clk_hw *cpu_clk_postmux0;
		700	struct clk_hw *cpu_clk_postmux1;
		701	struct clk_hw *cpu_clk_premux1;
		702	};
		703
		704	static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
		705	unsigned long event, void *data)
		706	{
		707	struct g12a_cpu_clk_postmux_nb_data *nb_data =
		708	container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
		709
		710	switch (event) {
		711	case PRE_RATE_CHANGE:
		712	/*
		713	* This notifier means cpu_clk_postmux0 clock will be changed
		714	* to feed cpu_clk, this is the current path :
		715	* cpu_clk
		716	* \- cpu_clk_dyn
		717	* \- cpu_clk_postmux0
		718	* \- cpu_clk_muxX_div
		719	* \- cpu_clk_premux0
		720	* \- fclk_div3 or fclk_div2
		721	* OR
		722	* \- cpu_clk_premux0
		723	* \- fclk_div3 or fclk_div2
		724	*/
		725
		726	/* Setup cpu_clk_premux1 to xtal */
		727	clk_hw_set_parent(nb_data->cpu_clk_premux1,
		728	nb_data->xtal);
		729
		730	/* Setup cpu_clk_postmux1 to bypass divider */
		731	clk_hw_set_parent(nb_data->cpu_clk_postmux1,
		732	nb_data->cpu_clk_premux1);
		733
		734	/* Switch to parking clk on cpu_clk_postmux1 */
		735	clk_hw_set_parent(nb_data->cpu_clk_dyn,
		736	nb_data->cpu_clk_postmux1);
		737
		738	/*
		739	* Now, cpu_clk is 24MHz in the current path :
		740	* cpu_clk
		741	* \- cpu_clk_dyn
		742	* \- cpu_clk_postmux1
		743	* \- cpu_clk_premux1
		744	* \- xtal
		745	*/
		746
		747	udelay(100);
		748
		749	return NOTIFY_OK;
		750
		751	case POST_RATE_CHANGE:
		752	/*
		753	* The cpu_clk_postmux0 has ben updated, now switch back
		754	* cpu_clk_dyn to cpu_clk_postmux0 and take the changes
		755	* in account.
		756	*/
		757
		758	/* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
		759	clk_hw_set_parent(nb_data->cpu_clk_dyn,
		760	nb_data->cpu_clk_postmux0);
		761
		762	/*
		763	* new path :
		764	* cpu_clk
		765	* \- cpu_clk_dyn
		766	* \- cpu_clk_postmux0
		767	* \- cpu_clk_muxX_div
		768	* \- cpu_clk_premux0
		769	* \- fclk_div3 or fclk_div2
		770	* OR
		771	* \- cpu_clk_premux0
		772	* \- fclk_div3 or fclk_div2
		773	*/
		774
		775	udelay(100);
		776
		777	return NOTIFY_OK;
		778
		779	default:
		780	return NOTIFY_DONE;
		781	}
		782	}
		783
		784	static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
		785	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
		786	.cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
		787	.cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
		788	.cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
		789	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
		790	};
		791
		792	static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
		793	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
		794	.cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
		795	.cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
		796	.cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
		797	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
		798	};
		799
		800	struct g12a_sys_pll_nb_data {
		801	struct notifier_block nb;
		802	struct clk_hw *sys_pll;
		803	struct clk_hw *cpu_clk;
		804	struct clk_hw *cpu_clk_dyn;
		805	};
		806
		807	static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
		808	unsigned long event, void *data)
		809	{
		810	struct g12a_sys_pll_nb_data *nb_data =
		811	container_of(nb, struct g12a_sys_pll_nb_data, nb);
		812
		813	switch (event) {
		814	case PRE_RATE_CHANGE:
		815	/*
		816	* This notifier means sys_pll clock will be changed
		817	* to feed cpu_clk, this the current path :
		818	* cpu_clk
		819	* \- sys_pll
		820	* \- sys_pll_dco
		821	*/
		822
		823	/* Configure cpu_clk to use cpu_clk_dyn */
		824	clk_hw_set_parent(nb_data->cpu_clk,
		825	nb_data->cpu_clk_dyn);
		826
		827	/*
		828	* Now, cpu_clk uses the dyn path
		829	* cpu_clk
		830	* \- cpu_clk_dyn
		831	* \- cpu_clk_dynX
		832	* \- cpu_clk_dynX_sel
		833	* \- cpu_clk_dynX_div
		834	* \- xtal/fclk_div2/fclk_div3
		835	* \- xtal/fclk_div2/fclk_div3
		836	*/
		837
		838	udelay(100);
		839
		840	return NOTIFY_OK;
		841
		842	case POST_RATE_CHANGE:
		843	/*
		844	* The sys_pll has ben updated, now switch back cpu_clk to
		845	* sys_pll
		846	*/
		847
		848	/* Configure cpu_clk to use sys_pll */
		849	clk_hw_set_parent(nb_data->cpu_clk,
		850	nb_data->sys_pll);
		851
		852	udelay(100);
		853
		854	/* new path :
		855	* cpu_clk
		856	* \- sys_pll
		857	* \- sys_pll_dco
		858	*/
		859
		860	return NOTIFY_OK;
		861
		862	default:
		863	return NOTIFY_DONE;
		864	}
		865	}
		866
		867	static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
		868	.sys_pll = &g12a_sys_pll.hw,
		869	.cpu_clk = &g12a_cpu_clk.hw,
		870	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
		871	.nb.notifier_call = g12a_sys_pll_notifier_cb,
		872	};
		873
		874	/* G12B first CPU cluster uses sys1_pll */
		875	static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
		876	.sys_pll = &g12b_sys1_pll.hw,
		877	.cpu_clk = &g12b_cpu_clk.hw,
		878	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
		879	.nb.notifier_call = g12a_sys_pll_notifier_cb,
		880	};
		881
		882	/* G12B second CPU cluster uses sys_pll */
		883	static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
		884	.sys_pll = &g12a_sys_pll.hw,
		885	.cpu_clk = &g12b_cpub_clk.hw,
		886	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
		887	.nb.notifier_call = g12a_sys_pll_notifier_cb,
		888	};
		889
532	static struct clk_regmap g12a_cpu_clk_div16_en = {	890	static struct clk_regmap g12a_cpu_clk_div16_en = {
533	.data = &(struct clk_regmap_gate_data){	891	.data = &(struct clk_regmap_gate_data){
534	.offset = HHI_SYS_CPU_CLK_CNTL1,	892	.offset = HHI_SYS_CPU_CLK_CNTL1,
@@ -537,7 +895,9 @@ static struct clk_regmap g12a_cpu_clk_div16_en = { · 2 unmodified lines
537	.hw.init = &(struct clk_init_data) {	895	.hw.init = &(struct clk_init_data) {
538	.name = "cpu_clk_div16_en",	896	.name = "cpu_clk_div16_en",
539	.ops = &clk_regmap_gate_ro_ops,	897	.ops = &clk_regmap_gate_ro_ops,
540	.parent_names = (const char *[]){ "cpu_clk" },	898	.parent_hws = (const struct clk_hw *[]) {
		899	&g12a_cpu_clk.hw
		900	},
541	.num_parents = 1,	901	.num_parents = 1,
542	/*	902	/*
543	* This clock is used to debug the cpu_clk range	903	* This clock is used to debug the cpu_clk range
@@ -554,7 +914,9 @@ static struct clk_regmap g12b_cpub_clk_div16_en = { · 10 unmodified lines
554	.hw.init = &(struct clk_init_data) {	914	.hw.init = &(struct clk_init_data) {
555	.name = "cpub_clk_div16_en",	915	.name = "cpub_clk_div16_en",
556	.ops = &clk_regmap_gate_ro_ops,	916	.ops = &clk_regmap_gate_ro_ops,
557	.parent_names = (const char *[]){ "cpub_clk" },	917	.parent_hws = (const struct clk_hw *[]) {
		918	&g12b_cpub_clk.hw
		919	},
558	.num_parents = 1,	920	.num_parents = 1,
559	/*	921	/*
560	* This clock is used to debug the cpu_clk range	922	* This clock is used to debug the cpu_clk range
@@ -569,7 +931,9 @@ static struct clk_fixed_factor g12a_cpu_clk_div16 = { · 8 unmodified lines
569	.hw.init = &(struct clk_init_data){	931	.hw.init = &(struct clk_init_data){
570	.name = "cpu_clk_div16",	932	.name = "cpu_clk_div16",
571	.ops = &clk_fixed_factor_ops,	933	.ops = &clk_fixed_factor_ops,
572	.parent_names = (const char *[]){ "cpu_clk_div16_en" },	934	.parent_hws = (const struct clk_hw *[]) {
		935	&g12a_cpu_clk_div16_en.hw
		936	},
573	.num_parents = 1,	937	.num_parents = 1,
574	},	938	},
575	};	939	};
@@ -580,7 +944,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div16 = { · 4 unmodified lines
580	.hw.init = &(struct clk_init_data){	944	.hw.init = &(struct clk_init_data){
581	.name = "cpub_clk_div16",	945	.name = "cpub_clk_div16",
582	.ops = &clk_fixed_factor_ops,	946	.ops = &clk_fixed_factor_ops,
583	.parent_names = (const char *[]){ "cpub_clk_div16_en" },	947	.parent_hws = (const struct clk_hw *[]) {
		948	&g12b_cpub_clk_div16_en.hw
		949	},
584	.num_parents = 1,	950	.num_parents = 1,
585	},	951	},
586	};	952	};
@@ -595,7 +961,7 @@ static struct clk_regmap g12a_cpu_clk_apb_div = { · 8 unmodified lines
595	.hw.init = &(struct clk_init_data){	961	.hw.init = &(struct clk_init_data){
596	.name = "cpu_clk_apb_div",	962	.name = "cpu_clk_apb_div",
597	.ops = &clk_regmap_divider_ro_ops,	963	.ops = &clk_regmap_divider_ro_ops,
598	.parent_names = (const char *[]){ "cpu_clk" },	964	.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
599	.num_parents = 1,	965	.num_parents = 1,
600	},	966	},
601	};	967	};
@@ -608,7 +974,9 @@ static struct clk_regmap g12a_cpu_clk_apb = { · 6 unmodified lines
608	.hw.init = &(struct clk_init_data) {	974	.hw.init = &(struct clk_init_data) {
609	.name = "cpu_clk_apb",	975	.name = "cpu_clk_apb",
610	.ops = &clk_regmap_gate_ro_ops,	976	.ops = &clk_regmap_gate_ro_ops,
611	.parent_names = (const char *[]){ "cpu_clk_apb_div" },	977	.parent_hws = (const struct clk_hw *[]) {
		978	&g12a_cpu_clk_apb_div.hw
		979	},
612	.num_parents = 1,	980	.num_parents = 1,
613	/*	981	/*
614	* This clock is set by the ROM monitor code,	982	* This clock is set by the ROM monitor code,
@@ -627,7 +995,7 @@ static struct clk_regmap g12a_cpu_clk_atb_div = { · 12 unmodified lines
627	.hw.init = &(struct clk_init_data){	995	.hw.init = &(struct clk_init_data){
628	.name = "cpu_clk_atb_div",	996	.name = "cpu_clk_atb_div",
629	.ops = &clk_regmap_divider_ro_ops,	997	.ops = &clk_regmap_divider_ro_ops,
630	.parent_names = (const char *[]){ "cpu_clk" },	998	.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
631	.num_parents = 1,	999	.num_parents = 1,
632	},	1000	},
633	};	1001	};
@@ -640,7 +1008,9 @@ static struct clk_regmap g12a_cpu_clk_atb = { · 6 unmodified lines
640	.hw.init = &(struct clk_init_data) {	1008	.hw.init = &(struct clk_init_data) {
641	.name = "cpu_clk_atb",	1009	.name = "cpu_clk_atb",
642	.ops = &clk_regmap_gate_ro_ops,	1010	.ops = &clk_regmap_gate_ro_ops,
643	.parent_names = (const char *[]){ "cpu_clk_atb_div" },	1011	.parent_hws = (const struct clk_hw *[]) {
		1012	&g12a_cpu_clk_atb_div.hw
		1013	},
644	.num_parents = 1,	1014	.num_parents = 1,
645	/*	1015	/*
646	* This clock is set by the ROM monitor code,	1016	* This clock is set by the ROM monitor code,
@@ -659,7 +1029,7 @@ static struct clk_regmap g12a_cpu_clk_axi_div = { · 12 unmodified lines
659	.hw.init = &(struct clk_init_data){	1029	.hw.init = &(struct clk_init_data){
660	.name = "cpu_clk_axi_div",	1030	.name = "cpu_clk_axi_div",
661	.ops = &clk_regmap_divider_ro_ops,	1031	.ops = &clk_regmap_divider_ro_ops,
662	.parent_names = (const char *[]){ "cpu_clk" },	1032	.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
663	.num_parents = 1,	1033	.num_parents = 1,
664	},	1034	},
665	};	1035	};
@@ -672,7 +1042,9 @@ static struct clk_regmap g12a_cpu_clk_axi = { · 6 unmodified lines
672	.hw.init = &(struct clk_init_data) {	1042	.hw.init = &(struct clk_init_data) {
673	.name = "cpu_clk_axi",	1043	.name = "cpu_clk_axi",
674	.ops = &clk_regmap_gate_ro_ops,	1044	.ops = &clk_regmap_gate_ro_ops,
675	.parent_names = (const char *[]){ "cpu_clk_axi_div" },	1045	.parent_hws = (const struct clk_hw *[]) {
		1046	&g12a_cpu_clk_axi_div.hw
		1047	},
676	.num_parents = 1,	1048	.num_parents = 1,
677	/*	1049	/*
678	* This clock is set by the ROM monitor code,	1050	* This clock is set by the ROM monitor code,
@@ -691,7 +1063,17 @@ static struct clk_regmap g12a_cpu_clk_trace_div = { · 12 unmodified lines
691	.hw.init = &(struct clk_init_data){	1063	.hw.init = &(struct clk_init_data){
692	.name = "cpu_clk_trace_div",	1064	.name = "cpu_clk_trace_div",
693	.ops = &clk_regmap_divider_ro_ops,	1065	.ops = &clk_regmap_divider_ro_ops,
694	.parent_names = (const char *[]){ "cpu_clk" },	1066	.parent_data = &(const struct clk_parent_data) {
		1067	/*
		1068	* Note:
		1069	* G12A and G12B have different cpu_clks (with
		1070	* different struct clk_hw). We fallback to the global
		1071	* naming string mechanism so cpu_clk_trace_div picks
		1072	* up the appropriate one.
		1073	*/
		1074	.name = "cpu_clk",
		1075	.index = -1,
		1076	},
695	.num_parents = 1,	1077	.num_parents = 1,
696	},	1078	},
697	};	1079	};
@@ -704,7 +1086,9 @@ static struct clk_regmap g12a_cpu_clk_trace = { · 6 unmodified lines
704	.hw.init = &(struct clk_init_data) {	1086	.hw.init = &(struct clk_init_data) {
705	.name = "cpu_clk_trace",	1087	.name = "cpu_clk_trace",
706	.ops = &clk_regmap_gate_ro_ops,	1088	.ops = &clk_regmap_gate_ro_ops,
707	.parent_names = (const char *[]){ "cpu_clk_trace_div" },	1089	.parent_hws = (const struct clk_hw *[]) {
		1090	&g12a_cpu_clk_trace_div.hw
		1091	},
708	.num_parents = 1,	1092	.num_parents = 1,
709	/*	1093	/*
710	* This clock is set by the ROM monitor code,	1094	* This clock is set by the ROM monitor code,
@@ -719,7 +1103,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div2 = { · 8 unmodified lines
719	.hw.init = &(struct clk_init_data){	1103	.hw.init = &(struct clk_init_data){
720	.name = "cpub_clk_div2",	1104	.name = "cpub_clk_div2",
721	.ops = &clk_fixed_factor_ops,	1105	.ops = &clk_fixed_factor_ops,
722	.parent_names = (const char *[]){ "cpub_clk" },	1106	.parent_hws = (const struct clk_hw *[]) {
		1107	&g12b_cpub_clk.hw
		1108	},
723	.num_parents = 1,	1109	.num_parents = 1,
724	},	1110	},
725	};	1111	};
@@ -730,7 +1116,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div3 = { · 4 unmodified lines
730	.hw.init = &(struct clk_init_data){	1116	.hw.init = &(struct clk_init_data){
731	.name = "cpub_clk_div3",	1117	.name = "cpub_clk_div3",
732	.ops = &clk_fixed_factor_ops,	1118	.ops = &clk_fixed_factor_ops,
733	.parent_names = (const char *[]){ "cpub_clk" },	1119	.parent_hws = (const struct clk_hw *[]) {
		1120	&g12b_cpub_clk.hw
		1121	},
734	.num_parents = 1,	1122	.num_parents = 1,
735	},	1123	},
736	};	1124	};
@@ -741,7 +1129,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div4 = { · 4 unmodified lines
741	.hw.init = &(struct clk_init_data){	1129	.hw.init = &(struct clk_init_data){
742	.name = "cpub_clk_div4",	1130	.name = "cpub_clk_div4",
743	.ops = &clk_fixed_factor_ops,	1131	.ops = &clk_fixed_factor_ops,
744	.parent_names = (const char *[]){ "cpub_clk" },	1132	.parent_hws = (const struct clk_hw *[]) {
		1133	&g12b_cpub_clk.hw
		1134	},
745	.num_parents = 1,	1135	.num_parents = 1,
746	},	1136	},
747	};	1137	};
@@ -752,7 +1142,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div5 = { · 4 unmodified lines
752	.hw.init = &(struct clk_init_data){	1142	.hw.init = &(struct clk_init_data){
753	.name = "cpub_clk_div5",	1143	.name = "cpub_clk_div5",
754	.ops = &clk_fixed_factor_ops,	1144	.ops = &clk_fixed_factor_ops,
755	.parent_names = (const char *[]){ "cpub_clk" },	1145	.parent_hws = (const struct clk_hw *[]) {
		1146	&g12b_cpub_clk.hw
		1147	},
756	.num_parents = 1,	1148	.num_parents = 1,
757	},	1149	},
758	};	1150	};
@@ -763,7 +1155,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div6 = { · 4 unmodified lines
763	.hw.init = &(struct clk_init_data){	1155	.hw.init = &(struct clk_init_data){
764	.name = "cpub_clk_div6",	1156	.name = "cpub_clk_div6",
765	.ops = &clk_fixed_factor_ops,	1157	.ops = &clk_fixed_factor_ops,
766	.parent_names = (const char *[]){ "cpub_clk" },	1158	.parent_hws = (const struct clk_hw *[]) {
		1159	&g12b_cpub_clk.hw
		1160	},
767	.num_parents = 1,	1161	.num_parents = 1,
768	},	1162	},
769	};	1163	};
@@ -774,7 +1168,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div7 = { · 4 unmodified lines
774	.hw.init = &(struct clk_init_data){	1168	.hw.init = &(struct clk_init_data){
775	.name = "cpub_clk_div7",	1169	.name = "cpub_clk_div7",
776	.ops = &clk_fixed_factor_ops,	1170	.ops = &clk_fixed_factor_ops,
777	.parent_names = (const char *[]){ "cpub_clk" },	1171	.parent_hws = (const struct clk_hw *[]) {
		1172	&g12b_cpub_clk.hw
		1173	},
778	.num_parents = 1,	1174	.num_parents = 1,
779	},	1175	},
780	};	1176	};
@@ -785,7 +1181,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div8 = { · 4 unmodified lines
785	.hw.init = &(struct clk_init_data){	1181	.hw.init = &(struct clk_init_data){
786	.name = "cpub_clk_div8",	1182	.name = "cpub_clk_div8",
787	.ops = &clk_fixed_factor_ops,	1183	.ops = &clk_fixed_factor_ops,
788	.parent_names = (const char *[]){ "cpub_clk" },	1184	.parent_hws = (const struct clk_hw *[]) {
		1185	&g12b_cpub_clk.hw
		1186	},
789	.num_parents = 1,	1187	.num_parents = 1,
790	},	1188	},
791	};	1189	};
@@ -801,13 +1199,15 @@ static struct clk_regmap g12b_cpub_clk_apb_sel = { · 9 unmodified lines
801	.hw.init = &(struct clk_init_data){	1199	.hw.init = &(struct clk_init_data){
802	.name = "cpub_clk_apb_sel",	1200	.name = "cpub_clk_apb_sel",
803	.ops = &clk_regmap_mux_ro_ops,	1201	.ops = &clk_regmap_mux_ro_ops,
804	.parent_names = (const char *[]){ "cpub_clk_div2",	1202	.parent_hws = (const struct clk_hw *[]) {
805	"cpub_clk_div3",	1203	&g12b_cpub_clk_div2.hw,
806	"cpub_clk_div4",	1204	&g12b_cpub_clk_div3.hw,
807	"cpub_clk_div5",	1205	&g12b_cpub_clk_div4.hw,
808	"cpub_clk_div6",	1206	&g12b_cpub_clk_div5.hw,
809	"cpub_clk_div7",	1207	&g12b_cpub_clk_div6.hw,
810	"cpub_clk_div8" },	1208	&g12b_cpub_clk_div7.hw,
		1209	&g12b_cpub_clk_div8.hw
		1210	},
811	.num_parents = 7,	1211	.num_parents = 7,
812	},	1212	},
813	};	1213	};
@@ -821,7 +1221,9 @@ static struct clk_regmap g12b_cpub_clk_apb = { · 7 unmodified lines
821	.hw.init = &(struct clk_init_data) {	1221	.hw.init = &(struct clk_init_data) {
822	.name = "cpub_clk_apb",	1222	.name = "cpub_clk_apb",
823	.ops = &clk_regmap_gate_ro_ops,	1223	.ops = &clk_regmap_gate_ro_ops,
824	.parent_names = (const char *[]){ "cpub_clk_apb_sel" },	1224	.parent_hws = (const struct clk_hw *[]) {
		1225	&g12b_cpub_clk_apb_sel.hw
		1226	},
825	.num_parents = 1,	1227	.num_parents = 1,
826	/*	1228	/*
827	* This clock is set by the ROM monitor code,	1229	* This clock is set by the ROM monitor code,
@@ -840,13 +1242,15 @@ static struct clk_regmap g12b_cpub_clk_atb_sel = { · 12 unmodified lines
840	.hw.init = &(struct clk_init_data){	1242	.hw.init = &(struct clk_init_data){
841	.name = "cpub_clk_atb_sel",	1243	.name = "cpub_clk_atb_sel",
842	.ops = &clk_regmap_mux_ro_ops,	1244	.ops = &clk_regmap_mux_ro_ops,
843	.parent_names = (const char *[]){ "cpub_clk_div2",	1245	.parent_hws = (const struct clk_hw *[]) {
844	"cpub_clk_div3",	1246	&g12b_cpub_clk_div2.hw,
845	"cpub_clk_div4",	1247	&g12b_cpub_clk_div3.hw,
846	"cpub_clk_div5",	1248	&g12b_cpub_clk_div4.hw,
847	"cpub_clk_div6",	1249	&g12b_cpub_clk_div5.hw,
848	"cpub_clk_div7",	1250	&g12b_cpub_clk_div6.hw,
849	"cpub_clk_div8" },	1251	&g12b_cpub_clk_div7.hw,
		1252	&g12b_cpub_clk_div8.hw
		1253	},
850	.num_parents = 7,	1254	.num_parents = 7,
851	},	1255	},
852	};	1256	};
@@ -860,7 +1264,9 @@ static struct clk_regmap g12b_cpub_clk_atb = { · 7 unmodified lines
860	.hw.init = &(struct clk_init_data) {	1264	.hw.init = &(struct clk_init_data) {
861	.name = "cpub_clk_atb",	1265	.name = "cpub_clk_atb",
862	.ops = &clk_regmap_gate_ro_ops,	1266	.ops = &clk_regmap_gate_ro_ops,
863	.parent_names = (const char *[]){ "cpub_clk_atb_sel" },	1267	.parent_hws = (const struct clk_hw *[]) {
		1268	&g12b_cpub_clk_atb_sel.hw
		1269	},
864	.num_parents = 1,	1270	.num_parents = 1,
865	/*	1271	/*
866	* This clock is set by the ROM monitor code,	1272	* This clock is set by the ROM monitor code,
@@ -879,13 +1285,15 @@ static struct clk_regmap g12b_cpub_clk_axi_sel = { · 12 unmodified lines
879	.hw.init = &(struct clk_init_data){	1285	.hw.init = &(struct clk_init_data){
880	.name = "cpub_clk_axi_sel",	1286	.name = "cpub_clk_axi_sel",
881	.ops = &clk_regmap_mux_ro_ops,	1287	.ops = &clk_regmap_mux_ro_ops,
882	.parent_names = (const char *[]){ "cpub_clk_div2",	1288	.parent_hws = (const struct clk_hw *[]) {
883	"cpub_clk_div3",	1289	&g12b_cpub_clk_div2.hw,
884	"cpub_clk_div4",	1290	&g12b_cpub_clk_div3.hw,
885	"cpub_clk_div5",	1291	&g12b_cpub_clk_div4.hw,
886	"cpub_clk_div6",	1292	&g12b_cpub_clk_div5.hw,
887	"cpub_clk_div7",	1293	&g12b_cpub_clk_div6.hw,
888	"cpub_clk_div8" },	1294	&g12b_cpub_clk_div7.hw,
		1295	&g12b_cpub_clk_div8.hw
		1296	},
889	.num_parents = 7,	1297	.num_parents = 7,
890	},	1298	},
891	};	1299	};
@@ -899,7 +1307,9 @@ static struct clk_regmap g12b_cpub_clk_axi = { · 7 unmodified lines
899	.hw.init = &(struct clk_init_data) {	1307	.hw.init = &(struct clk_init_data) {
900	.name = "cpub_clk_axi",	1308	.name = "cpub_clk_axi",
901	.ops = &clk_regmap_gate_ro_ops,	1309	.ops = &clk_regmap_gate_ro_ops,
902	.parent_names = (const char *[]){ "cpub_clk_axi_sel" },	1310	.parent_hws = (const struct clk_hw *[]) {
		1311	&g12b_cpub_clk_axi_sel.hw
		1312	},
903	.num_parents = 1,	1313	.num_parents = 1,
904	/*	1314	/*
905	* This clock is set by the ROM monitor code,	1315	* This clock is set by the ROM monitor code,
@@ -918,13 +1328,15 @@ static struct clk_regmap g12b_cpub_clk_trace_sel = { · 12 unmodified lines
918	.hw.init = &(struct clk_init_data){	1328	.hw.init = &(struct clk_init_data){
919	.name = "cpub_clk_trace_sel",	1329	.name = "cpub_clk_trace_sel",
920	.ops = &clk_regmap_mux_ro_ops,	1330	.ops = &clk_regmap_mux_ro_ops,
921	.parent_names = (const char *[]){ "cpub_clk_div2",	1331	.parent_hws = (const struct clk_hw *[]) {
922	"cpub_clk_div3",	1332	&g12b_cpub_clk_div2.hw,
923	"cpub_clk_div4",	1333	&g12b_cpub_clk_div3.hw,
924	"cpub_clk_div5",	1334	&g12b_cpub_clk_div4.hw,
925	"cpub_clk_div6",	1335	&g12b_cpub_clk_div5.hw,
926	"cpub_clk_div7",	1336	&g12b_cpub_clk_div6.hw,
927	"cpub_clk_div8" },	1337	&g12b_cpub_clk_div7.hw,
		1338	&g12b_cpub_clk_div8.hw
		1339	},
928	.num_parents = 7,	1340	.num_parents = 7,
929	},	1341	},
930	};	1342	};
@@ -938,7 +1350,9 @@ static struct clk_regmap g12b_cpub_clk_trace = { · 7 unmodified lines
938	.hw.init = &(struct clk_init_data) {	1350	.hw.init = &(struct clk_init_data) {
939	.name = "cpub_clk_trace",	1351	.name = "cpub_clk_trace",
940	.ops = &clk_regmap_gate_ro_ops,	1352	.ops = &clk_regmap_gate_ro_ops,
941	.parent_names = (const char *[]){ "cpub_clk_trace_sel" },	1353	.parent_hws = (const struct clk_hw *[]) {
		1354	&g12b_cpub_clk_trace_sel.hw
		1355	},
942	.num_parents = 1,	1356	.num_parents = 1,
943	/*	1357	/*
944	* This clock is set by the ROM monitor code,	1358	* This clock is set by the ROM monitor code,
@@ -1003,7 +1417,9 @@ static struct clk_regmap g12a_gp0_pll_dco = { · 58 unmodified lines
1003	.hw.init = &(struct clk_init_data){	1417	.hw.init = &(struct clk_init_data){
1004	.name = "gp0_pll_dco",	1418	.name = "gp0_pll_dco",
1005	.ops = &meson_clk_pll_ops,	1419	.ops = &meson_clk_pll_ops,
1006	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	1420	.parent_data = &(const struct clk_parent_data) {
		1421	.fw_name = "xtal",
		1422	},
1007	.num_parents = 1,	1423	.num_parents = 1,
1008	},	1424	},
1009	};	1425	};
@@ -1019,7 +1435,9 @@ static struct clk_regmap g12a_gp0_pll = { · 9 unmodified lines
1019	.hw.init = &(struct clk_init_data){	1435	.hw.init = &(struct clk_init_data){
1020	.name = "gp0_pll",	1436	.name = "gp0_pll",
1021	.ops = &clk_regmap_divider_ops,	1437	.ops = &clk_regmap_divider_ops,
1022	.parent_names = (const char *[]){ "gp0_pll_dco" },	1438	.parent_hws = (const struct clk_hw *[]) {
		1439	&g12a_gp0_pll_dco.hw
		1440	},
1023	.num_parents = 1,	1441	.num_parents = 1,
1024	.flags = CLK_SET_RATE_PARENT,	1442	.flags = CLK_SET_RATE_PARENT,
1025	},	1443	},
@@ -1077,7 +1495,9 @@ static struct clk_regmap g12a_hifi_pll_dco = { · 51 unmodified lines
1077	.hw.init = &(struct clk_init_data){	1495	.hw.init = &(struct clk_init_data){
1078	.name = "hifi_pll_dco",	1496	.name = "hifi_pll_dco",
1079	.ops = &meson_clk_pll_ops,	1497	.ops = &meson_clk_pll_ops,
1080	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	1498	.parent_data = &(const struct clk_parent_data) {
		1499	.fw_name = "xtal",
		1500	},
1081	.num_parents = 1,	1501	.num_parents = 1,
1082	},	1502	},
1083	};	1503	};
@@ -1093,7 +1513,9 @@ static struct clk_regmap g12a_hifi_pll = { · 9 unmodified lines
1093	.hw.init = &(struct clk_init_data){	1513	.hw.init = &(struct clk_init_data){
1094	.name = "hifi_pll",	1514	.name = "hifi_pll",
1095	.ops = &clk_regmap_divider_ops,	1515	.ops = &clk_regmap_divider_ops,
1096	.parent_names = (const char *[]){ "hifi_pll_dco" },	1516	.parent_hws = (const struct clk_hw *[]) {
		1517	&g12a_hifi_pll_dco.hw
		1518	},
1097	.num_parents = 1,	1519	.num_parents = 1,
1098	.flags = CLK_SET_RATE_PARENT,	1520	.flags = CLK_SET_RATE_PARENT,
1099	},	1521	},
@@ -1164,7 +1586,9 @@ static struct clk_regmap g12a_pcie_pll_dco = { · 64 unmodified lines
1164	.hw.init = &(struct clk_init_data){	1586	.hw.init = &(struct clk_init_data){
1165	.name = "pcie_pll_dco",	1587	.name = "pcie_pll_dco",
1166	.ops = &meson_clk_pcie_pll_ops,	1588	.ops = &meson_clk_pcie_pll_ops,
1167	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	1589	.parent_data = &(const struct clk_parent_data) {
		1590	.fw_name = "xtal",
		1591	},
1168	.num_parents = 1,	1592	.num_parents = 1,
1169	},	1593	},
1170	};	1594	};
@@ -1175,7 +1599,9 @@ static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = { · 4 unmodified lines
1175	.hw.init = &(struct clk_init_data){	1599	.hw.init = &(struct clk_init_data){
1176	.name = "pcie_pll_dco_div2",	1600	.name = "pcie_pll_dco_div2",
1177	.ops = &clk_fixed_factor_ops,	1601	.ops = &clk_fixed_factor_ops,
1178	.parent_names = (const char *[]){ "pcie_pll_dco" },	1602	.parent_hws = (const struct clk_hw *[]) {
		1603	&g12a_pcie_pll_dco.hw
		1604	},
1179	.num_parents = 1,	1605	.num_parents = 1,
1180	.flags = CLK_SET_RATE_PARENT,	1606	.flags = CLK_SET_RATE_PARENT,
1181	},	1607	},
@@ -1193,7 +1619,9 @@ static struct clk_regmap g12a_pcie_pll_od = { · 11 unmodified lines
1193	.hw.init = &(struct clk_init_data){	1619	.hw.init = &(struct clk_init_data){
1194	.name = "pcie_pll_od",	1620	.name = "pcie_pll_od",
1195	.ops = &clk_regmap_divider_ops,	1621	.ops = &clk_regmap_divider_ops,
1196	.parent_names = (const char *[]){ "pcie_pll_dco_div2" },	1622	.parent_hws = (const struct clk_hw *[]) {
		1623	&g12a_pcie_pll_dco_div2.hw
		1624	},
1197	.num_parents = 1,	1625	.num_parents = 1,
1198	.flags = CLK_SET_RATE_PARENT,	1626	.flags = CLK_SET_RATE_PARENT,
1199	},	1627	},
@@ -1205,7 +1633,9 @@ static struct clk_fixed_factor g12a_pcie_pll = { · 5 unmodified lines
1205	.hw.init = &(struct clk_init_data){	1633	.hw.init = &(struct clk_init_data){
1206	.name = "pcie_pll_pll",	1634	.name = "pcie_pll_pll",
1207	.ops = &clk_fixed_factor_ops,	1635	.ops = &clk_fixed_factor_ops,
1208	.parent_names = (const char *[]){ "pcie_pll_od" },	1636	.parent_hws = (const struct clk_hw *[]) {
		1637	&g12a_pcie_pll_od.hw
		1638	},
1209	.num_parents = 1,	1639	.num_parents = 1,
1210	.flags = CLK_SET_RATE_PARENT,	1640	.flags = CLK_SET_RATE_PARENT,
1211	},	1641	},
@@ -1247,7 +1677,9 @@ static struct clk_regmap g12a_hdmi_pll_dco = { · 35 unmodified lines
1247	.hw.init = &(struct clk_init_data){	1677	.hw.init = &(struct clk_init_data){
1248	.name = "hdmi_pll_dco",	1678	.name = "hdmi_pll_dco",
1249	.ops = &meson_clk_pll_ro_ops,	1679	.ops = &meson_clk_pll_ro_ops,
1250	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	1680	.parent_data = &(const struct clk_parent_data) {
		1681	.fw_name = "xtal",
		1682	},
1251	.num_parents = 1,	1683	.num_parents = 1,
1252	/*	1684	/*
1253	* Display directly handle hdmi pll registers ATM, we need	1685	* Display directly handle hdmi pll registers ATM, we need
@@ -1267,7 +1699,9 @@ static struct clk_regmap g12a_hdmi_pll_od = { · 13 unmodified lines
1267	.hw.init = &(struct clk_init_data){	1699	.hw.init = &(struct clk_init_data){
1268	.name = "hdmi_pll_od",	1700	.name = "hdmi_pll_od",
1269	.ops = &clk_regmap_divider_ro_ops,	1701	.ops = &clk_regmap_divider_ro_ops,
1270	.parent_names = (const char *[]){ "hdmi_pll_dco" },	1702	.parent_hws = (const struct clk_hw *[]) {
		1703	&g12a_hdmi_pll_dco.hw
		1704	},
1271	.num_parents = 1,	1705	.num_parents = 1,
1272	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	1706	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
1273	},	1707	},
@@ -1283,7 +1717,9 @@ static struct clk_regmap g12a_hdmi_pll_od2 = { · 9 unmodified lines
1283	.hw.init = &(struct clk_init_data){	1717	.hw.init = &(struct clk_init_data){
1284	.name = "hdmi_pll_od2",	1718	.name = "hdmi_pll_od2",
1285	.ops = &clk_regmap_divider_ro_ops,	1719	.ops = &clk_regmap_divider_ro_ops,
1286	.parent_names = (const char *[]){ "hdmi_pll_od" },	1720	.parent_hws = (const struct clk_hw *[]) {
		1721	&g12a_hdmi_pll_od.hw
		1722	},
1287	.num_parents = 1,	1723	.num_parents = 1,
1288	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	1724	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
1289	},	1725	},
@@ -1299,77 +1735,21 @@ static struct clk_regmap g12a_hdmi_pll = { · 9 unmodified lines
1299	.hw.init = &(struct clk_init_data){	1735	.hw.init = &(struct clk_init_data){
1300	.name = "hdmi_pll",	1736	.name = "hdmi_pll",
1301	.ops = &clk_regmap_divider_ro_ops,	1737	.ops = &clk_regmap_divider_ro_ops,
1302	.parent_names = (const char *[]){ "hdmi_pll_od2" },	1738	.parent_hws = (const struct clk_hw *[]) {
		1739	&g12a_hdmi_pll_od2.hw
		1740	},
1303	.num_parents = 1,	1741	.num_parents = 1,
1304	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	1742	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
1305	},	1743	},
1306	};	1744	};
1307		1745
1308	static struct clk_fixed_factor g12a_fclk_div2_div = {
1309	.mult = 1,
1310	.div = 2,
1311	.hw.init = &(struct clk_init_data){
1312	.name = "fclk_div2_div",
1313	.ops = &clk_fixed_factor_ops,
1314	.parent_names = (const char *[]){ "fixed_pll" },
1315	.num_parents = 1,
1316	},
1317	};
1318
1319	static struct clk_regmap g12a_fclk_div2 = {
1320	.data = &(struct clk_regmap_gate_data){
1321	.offset = HHI_FIX_PLL_CNTL1,
1322	.bit_idx = 24,
1323	},
1324	.hw.init = &(struct clk_init_data){
1325	.name = "fclk_div2",
1326	.ops = &clk_regmap_gate_ops,
1327	.parent_names = (const char *[]){ "fclk_div2_div" },
1328	.num_parents = 1,
1329	},
1330	};
1331
1332	static struct clk_fixed_factor g12a_fclk_div3_div = {
1333	.mult = 1,
1334	.div = 3,
1335	.hw.init = &(struct clk_init_data){
1336	.name = "fclk_div3_div",
1337	.ops = &clk_fixed_factor_ops,
1338	.parent_names = (const char *[]){ "fixed_pll" },
1339	.num_parents = 1,
1340	},
1341	};
1342
1343	static struct clk_regmap g12a_fclk_div3 = {
1344	.data = &(struct clk_regmap_gate_data){
1345	.offset = HHI_FIX_PLL_CNTL1,
1346	.bit_idx = 20,
1347	},
1348	.hw.init = &(struct clk_init_data){
1349	.name = "fclk_div3",
1350	.ops = &clk_regmap_gate_ops,
1351	.parent_names = (const char *[]){ "fclk_div3_div" },
1352	.num_parents = 1,
1353	/*
1354	* This clock is used by the resident firmware and is required
1355	* by the platform to operate correctly.
1356	* Until the following condition are met, we need this clock to
1357	* be marked as critical:
1358	* a) Mark the clock used by a firmware resource, if possible
1359	* b) CCF has a clock hand-off mechanism to make the sure the
1360	* clock stays on until the proper driver comes along
1361	*/
1362	.flags = CLK_IS_CRITICAL,
1363	},
1364	};
1365
1366	static struct clk_fixed_factor g12a_fclk_div4_div = {	1746	static struct clk_fixed_factor g12a_fclk_div4_div = {
1367	.mult = 1,	1747	.mult = 1,
1368	.div = 4,	1748	.div = 4,
1369	.hw.init = &(struct clk_init_data){	1749	.hw.init = &(struct clk_init_data){
1370	.name = "fclk_div4_div",	1750	.name = "fclk_div4_div",
1371	.ops = &clk_fixed_factor_ops,	1751	.ops = &clk_fixed_factor_ops,
1372	.parent_names = (const char *[]){ "fixed_pll" },	1752	.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1373	.num_parents = 1,	1753	.num_parents = 1,
1374	},	1754	},
1375	};	1755	};
@@ -1382,7 +1762,9 @@ static struct clk_regmap g12a_fclk_div4 = { · 6 unmodified lines
1382	.hw.init = &(struct clk_init_data){	1762	.hw.init = &(struct clk_init_data){
1383	.name = "fclk_div4",	1763	.name = "fclk_div4",
1384	.ops = &clk_regmap_gate_ops,	1764	.ops = &clk_regmap_gate_ops,
1385	.parent_names = (const char *[]){ "fclk_div4_div" },	1765	.parent_hws = (const struct clk_hw *[]) {
		1766	&g12a_fclk_div4_div.hw
		1767	},
1386	.num_parents = 1,	1768	.num_parents = 1,
1387	},	1769	},
1388	};	1770	};
@@ -1393,7 +1775,7 @@ static struct clk_fixed_factor g12a_fclk_div5_div = { · 4 unmodified lines
1393	.hw.init = &(struct clk_init_data){	1775	.hw.init = &(struct clk_init_data){
1394	.name = "fclk_div5_div",	1776	.name = "fclk_div5_div",
1395	.ops = &clk_fixed_factor_ops,	1777	.ops = &clk_fixed_factor_ops,
1396	.parent_names = (const char *[]){ "fixed_pll" },	1778	.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1397	.num_parents = 1,	1779	.num_parents = 1,
1398	},	1780	},
1399	};	1781	};
@@ -1406,7 +1788,9 @@ static struct clk_regmap g12a_fclk_div5 = { · 6 unmodified lines
1406	.hw.init = &(struct clk_init_data){	1788	.hw.init = &(struct clk_init_data){
1407	.name = "fclk_div5",	1789	.name = "fclk_div5",
1408	.ops = &clk_regmap_gate_ops,	1790	.ops = &clk_regmap_gate_ops,
1409	.parent_names = (const char *[]){ "fclk_div5_div" },	1791	.parent_hws = (const struct clk_hw *[]) {
		1792	&g12a_fclk_div5_div.hw
		1793	},
1410	.num_parents = 1,	1794	.num_parents = 1,
1411	},	1795	},
1412	};	1796	};
@@ -1417,7 +1801,7 @@ static struct clk_fixed_factor g12a_fclk_div7_div = { · 4 unmodified lines
1417	.hw.init = &(struct clk_init_data){	1801	.hw.init = &(struct clk_init_data){
1418	.name = "fclk_div7_div",	1802	.name = "fclk_div7_div",
1419	.ops = &clk_fixed_factor_ops,	1803	.ops = &clk_fixed_factor_ops,
1420	.parent_names = (const char *[]){ "fixed_pll" },	1804	.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1421	.num_parents = 1,	1805	.num_parents = 1,
1422	},	1806	},
1423	};	1807	};
@@ -1430,7 +1814,9 @@ static struct clk_regmap g12a_fclk_div7 = { · 6 unmodified lines
1430	.hw.init = &(struct clk_init_data){	1814	.hw.init = &(struct clk_init_data){
1431	.name = "fclk_div7",	1815	.name = "fclk_div7",
1432	.ops = &clk_regmap_gate_ops,	1816	.ops = &clk_regmap_gate_ops,
1433	.parent_names = (const char *[]){ "fclk_div7_div" },	1817	.parent_hws = (const struct clk_hw *[]) {
		1818	&g12a_fclk_div7_div.hw
		1819	},
1434	.num_parents = 1,	1820	.num_parents = 1,
1435	},	1821	},
1436	};	1822	};
@@ -1441,7 +1827,9 @@ static struct clk_fixed_factor g12a_fclk_div2p5_div = { · 4 unmodified lines
1441	.hw.init = &(struct clk_init_data){	1827	.hw.init = &(struct clk_init_data){
1442	.name = "fclk_div2p5_div",	1828	.name = "fclk_div2p5_div",
1443	.ops = &clk_fixed_factor_ops,	1829	.ops = &clk_fixed_factor_ops,
1444	.parent_names = (const char *[]){ "fixed_pll_dco" },	1830	.parent_hws = (const struct clk_hw *[]) {
		1831	&g12a_fixed_pll_dco.hw
		1832	},
1445	.num_parents = 1,	1833	.num_parents = 1,
1446	},	1834	},
1447	};	1835	};
@@ -1454,7 +1842,9 @@ static struct clk_regmap g12a_fclk_div2p5 = { · 6 unmodified lines
1454	.hw.init = &(struct clk_init_data){	1842	.hw.init = &(struct clk_init_data){
1455	.name = "fclk_div2p5",	1843	.name = "fclk_div2p5",
1456	.ops = &clk_regmap_gate_ops,	1844	.ops = &clk_regmap_gate_ops,
1457	.parent_names = (const char *[]){ "fclk_div2p5_div" },	1845	.parent_hws = (const struct clk_hw *[]) {
		1846	&g12a_fclk_div2p5_div.hw
		1847	},
1458	.num_parents = 1,	1848	.num_parents = 1,
1459	},	1849	},
1460	};	1850	};
@@ -1465,7 +1855,9 @@ static struct clk_fixed_factor g12a_mpll_50m_div = { · 4 unmodified lines
1465	.hw.init = &(struct clk_init_data){	1855	.hw.init = &(struct clk_init_data){
1466	.name = "mpll_50m_div",	1856	.name = "mpll_50m_div",
1467	.ops = &clk_fixed_factor_ops,	1857	.ops = &clk_fixed_factor_ops,
1468	.parent_names = (const char *[]){ "fixed_pll_dco" },	1858	.parent_hws = (const struct clk_hw *[]) {
		1859	&g12a_fixed_pll_dco.hw
		1860	},
1469	.num_parents = 1,	1861	.num_parents = 1,
1470	},	1862	},
1471	};	1863	};
@@ -1479,8 +1871,10 @@ static struct clk_regmap g12a_mpll_50m = { · 7 unmodified lines
1479	.hw.init = &(struct clk_init_data){	1871	.hw.init = &(struct clk_init_data){
1480	.name = "mpll_50m",	1872	.name = "mpll_50m",
1481	.ops = &clk_regmap_mux_ro_ops,	1873	.ops = &clk_regmap_mux_ro_ops,
1482	.parent_names = (const char *[]){ IN_PREFIX "xtal",	1874	.parent_data = (const struct clk_parent_data []) {
1483	"mpll_50m_div" },	1875	{ .fw_name = "xtal", },
		1876	{ .hw = &g12a_mpll_50m_div.hw },
		1877	},
1484	.num_parents = 2,	1878	.num_parents = 2,
1485	},	1879	},
1486	};	1880	};
@@ -1491,7 +1885,9 @@ static struct clk_fixed_factor g12a_mpll_prediv = { · 4 unmodified lines
1491	.hw.init = &(struct clk_init_data){	1885	.hw.init = &(struct clk_init_data){
1492	.name = "mpll_prediv",	1886	.name = "mpll_prediv",
1493	.ops = &clk_fixed_factor_ops,	1887	.ops = &clk_fixed_factor_ops,
1494	.parent_names = (const char *[]){ "fixed_pll_dco" },	1888	.parent_hws = (const struct clk_hw *[]) {
		1889	&g12a_fixed_pll_dco.hw
		1890	},
1495	.num_parents = 1,	1891	.num_parents = 1,
1496	},	1892	},
1497	};	1893	};
@@ -1529,7 +1925,9 @@ static struct clk_regmap g12a_mpll0_div = { · 31 unmodified lines
1529	.hw.init = &(struct clk_init_data){	1925	.hw.init = &(struct clk_init_data){
1530	.name = "mpll0_div",	1926	.name = "mpll0_div",
1531	.ops = &meson_clk_mpll_ops,	1927	.ops = &meson_clk_mpll_ops,
1532	.parent_names = (const char *[]){ "mpll_prediv" },	1928	.parent_hws = (const struct clk_hw *[]) {
		1929	&g12a_mpll_prediv.hw
		1930	},
1533	.num_parents = 1,	1931	.num_parents = 1,
1534	},	1932	},
1535	};	1933	};
@@ -1542,7 +1940,7 @@ static struct clk_regmap g12a_mpll0 = { · 6 unmodified lines
1542	.hw.init = &(struct clk_init_data){	1940	.hw.init = &(struct clk_init_data){
1543	.name = "mpll0",	1941	.name = "mpll0",
1544	.ops = &clk_regmap_gate_ops,	1942	.ops = &clk_regmap_gate_ops,
1545	.parent_names = (const char *[]){ "mpll0_div" },	1943	.parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
1546	.num_parents = 1,	1944	.num_parents = 1,
1547	.flags = CLK_SET_RATE_PARENT,	1945	.flags = CLK_SET_RATE_PARENT,
1548	},	1946	},
@@ -1581,7 +1979,9 @@ static struct clk_regmap g12a_mpll1_div = { · 32 unmodified lines
1581	.hw.init = &(struct clk_init_data){	1979	.hw.init = &(struct clk_init_data){
1582	.name = "mpll1_div",	1980	.name = "mpll1_div",
1583	.ops = &meson_clk_mpll_ops,	1981	.ops = &meson_clk_mpll_ops,
1584	.parent_names = (const char *[]){ "mpll_prediv" },	1982	.parent_hws = (const struct clk_hw *[]) {
		1983	&g12a_mpll_prediv.hw
		1984	},
1585	.num_parents = 1,	1985	.num_parents = 1,
1586	},	1986	},
1587	};	1987	};
@@ -1594,7 +1994,7 @@ static struct clk_regmap g12a_mpll1 = { · 6 unmodified lines
1594	.hw.init = &(struct clk_init_data){	1994	.hw.init = &(struct clk_init_data){
1595	.name = "mpll1",	1995	.name = "mpll1",
1596	.ops = &clk_regmap_gate_ops,	1996	.ops = &clk_regmap_gate_ops,
1597	.parent_names = (const char *[]){ "mpll1_div" },	1997	.parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
1598	.num_parents = 1,	1998	.num_parents = 1,
1599	.flags = CLK_SET_RATE_PARENT,	1999	.flags = CLK_SET_RATE_PARENT,
1600	},	2000	},
@@ -1633,7 +2033,9 @@ static struct clk_regmap g12a_mpll2_div = { · 32 unmodified lines
1633	.hw.init = &(struct clk_init_data){	2033	.hw.init = &(struct clk_init_data){
1634	.name = "mpll2_div",	2034	.name = "mpll2_div",
1635	.ops = &meson_clk_mpll_ops,	2035	.ops = &meson_clk_mpll_ops,
1636	.parent_names = (const char *[]){ "mpll_prediv" },	2036	.parent_hws = (const struct clk_hw *[]) {
		2037	&g12a_mpll_prediv.hw
		2038	},
1637	.num_parents = 1,	2039	.num_parents = 1,
1638	},	2040	},
1639	};	2041	};
@@ -1646,7 +2048,7 @@ static struct clk_regmap g12a_mpll2 = { · 6 unmodified lines
1646	.hw.init = &(struct clk_init_data){	2048	.hw.init = &(struct clk_init_data){
1647	.name = "mpll2",	2049	.name = "mpll2",
1648	.ops = &clk_regmap_gate_ops,	2050	.ops = &clk_regmap_gate_ops,
1649	.parent_names = (const char *[]){ "mpll2_div" },	2051	.parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
1650	.num_parents = 1,	2052	.num_parents = 1,
1651	.flags = CLK_SET_RATE_PARENT,	2053	.flags = CLK_SET_RATE_PARENT,
1652	},	2054	},
@@ -1685,7 +2087,9 @@ static struct clk_regmap g12a_mpll3_div = { · 32 unmodified lines
1685	.hw.init = &(struct clk_init_data){	2087	.hw.init = &(struct clk_init_data){
1686	.name = "mpll3_div",	2088	.name = "mpll3_div",
1687	.ops = &meson_clk_mpll_ops,	2089	.ops = &meson_clk_mpll_ops,
1688	.parent_names = (const char *[]){ "mpll_prediv" },	2090	.parent_hws = (const struct clk_hw *[]) {
		2091	&g12a_mpll_prediv.hw
		2092	},
1689	.num_parents = 1,	2093	.num_parents = 1,
1690	},	2094	},
1691	};	2095	};
@@ -1698,16 +2102,21 @@ static struct clk_regmap g12a_mpll3 = { · 6 unmodified lines
1698	.hw.init = &(struct clk_init_data){	2102	.hw.init = &(struct clk_init_data){
1699	.name = "mpll3",	2103	.name = "mpll3",
1700	.ops = &clk_regmap_gate_ops,	2104	.ops = &clk_regmap_gate_ops,
1701	.parent_names = (const char *[]){ "mpll3_div" },	2105	.parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
1702	.num_parents = 1,	2106	.num_parents = 1,
1703	.flags = CLK_SET_RATE_PARENT,	2107	.flags = CLK_SET_RATE_PARENT,
1704	},	2108	},
1705	};	2109	};
1706		2110
1707	static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };	2111	static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
1708	static const char * const clk81_parent_names[] = {	2112	static const struct clk_parent_data clk81_parent_data[] = {
1709	IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",	2113	{ .fw_name = "xtal", },
1710	"fclk_div3", "fclk_div5"	2114	{ .hw = &g12a_fclk_div7.hw },
		2115	{ .hw = &g12a_mpll1.hw },
		2116	{ .hw = &g12a_mpll2.hw },
		2117	{ .hw = &g12a_fclk_div4.hw },
		2118	{ .hw = &g12a_fclk_div3.hw },
		2119	{ .hw = &g12a_fclk_div5.hw },
1711	};	2120	};
1712		2121
1713	static struct clk_regmap g12a_mpeg_clk_sel = {	2122	static struct clk_regmap g12a_mpeg_clk_sel = {
@@ -1720,8 +2129,8 @@ static struct clk_regmap g12a_mpeg_clk_sel = { · 6 unmodified lines
1720	.hw.init = &(struct clk_init_data){	2129	.hw.init = &(struct clk_init_data){
1721	.name = "mpeg_clk_sel",	2130	.name = "mpeg_clk_sel",
1722	.ops = &clk_regmap_mux_ro_ops,	2131	.ops = &clk_regmap_mux_ro_ops,
1723	.parent_names = clk81_parent_names,	2132	.parent_data = clk81_parent_data,
1724	.num_parents = ARRAY_SIZE(clk81_parent_names),	2133	.num_parents = ARRAY_SIZE(clk81_parent_data),
1725	},	2134	},
1726	};	2135	};
1727		2136
@@ -1734,7 +2143,9 @@ static struct clk_regmap g12a_mpeg_clk_div = { · 6 unmodified lines
1734	.hw.init = &(struct clk_init_data){	2143	.hw.init = &(struct clk_init_data){
1735	.name = "mpeg_clk_div",	2144	.name = "mpeg_clk_div",
1736	.ops = &clk_regmap_divider_ops,	2145	.ops = &clk_regmap_divider_ops,
1737	.parent_names = (const char *[]){ "mpeg_clk_sel" },	2146	.parent_hws = (const struct clk_hw *[]) {
		2147	&g12a_mpeg_clk_sel.hw
		2148	},
1738	.num_parents = 1,	2149	.num_parents = 1,
1739	.flags = CLK_SET_RATE_PARENT,	2150	.flags = CLK_SET_RATE_PARENT,
1740	},	2151	},
@@ -1748,15 +2159,20 @@ static struct clk_regmap g12a_clk81 = { · 7 unmodified lines
1748	.hw.init = &(struct clk_init_data){	2159	.hw.init = &(struct clk_init_data){
1749	.name = "clk81",	2160	.name = "clk81",
1750	.ops = &clk_regmap_gate_ops,	2161	.ops = &clk_regmap_gate_ops,
1751	.parent_names = (const char *[]){ "mpeg_clk_div" },	2162	.parent_hws = (const struct clk_hw *[]) {
		2163	&g12a_mpeg_clk_div.hw
		2164	},
1752	.num_parents = 1,	2165	.num_parents = 1,
1753	.flags = (CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL),	2166	.flags = (CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL),
1754	},	2167	},
1755	};	2168	};
1756		2169
1757	static const char * const g12a_sd_emmc_clk0_parent_names[] = {	2170	static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
1758	IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",	2171	{ .fw_name = "xtal", },
1759		2172	{ .hw = &g12a_fclk_div2.hw },
		2173	{ .hw = &g12a_fclk_div3.hw },
		2174	{ .hw = &g12a_fclk_div5.hw },
		2175	{ .hw = &g12a_fclk_div7.hw },
1760	/*	2176	/*
1761	* Following these parent clocks, we should also have had mpll2, mpll3	2177	* Following these parent clocks, we should also have had mpll2, mpll3
1762	* and gp0_pll but these clocks are too precious to be used here. All	2178	* and gp0_pll but these clocks are too precious to be used here. All
@@ -1775,8 +2191,8 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_sel = { · 12 unmodified lines
1775	.hw.init = &(struct clk_init_data) {	2191	.hw.init = &(struct clk_init_data) {
1776	.name = "sd_emmc_a_clk0_sel",	2192	.name = "sd_emmc_a_clk0_sel",
1777	.ops = &clk_regmap_mux_ops,	2193	.ops = &clk_regmap_mux_ops,
1778	.parent_names = g12a_sd_emmc_clk0_parent_names,	2194	.parent_data = g12a_sd_emmc_clk0_parent_data,
1779	.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),	2195	.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
1780	.flags = CLK_SET_RATE_PARENT,	2196	.flags = CLK_SET_RATE_PARENT,
1781	},	2197	},
1782	};	2198	};
@@ -1790,7 +2206,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_div = { · 7 unmodified lines
1790	.hw.init = &(struct clk_init_data) {	2206	.hw.init = &(struct clk_init_data) {
1791	.name = "sd_emmc_a_clk0_div",	2207	.name = "sd_emmc_a_clk0_div",
1792	.ops = &clk_regmap_divider_ops,	2208	.ops = &clk_regmap_divider_ops,
1793	.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },	2209	.parent_hws = (const struct clk_hw *[]) {
		2210	&g12a_sd_emmc_a_clk0_sel.hw
		2211	},
1794	.num_parents = 1,	2212	.num_parents = 1,
1795	.flags = CLK_SET_RATE_PARENT,	2213	.flags = CLK_SET_RATE_PARENT,
1796	},	2214	},
@@ -1804,7 +2222,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0 = { · 7 unmodified lines
1804	.hw.init = &(struct clk_init_data){	2222	.hw.init = &(struct clk_init_data){
1805	.name = "sd_emmc_a_clk0",	2223	.name = "sd_emmc_a_clk0",
1806	.ops = &clk_regmap_gate_ops,	2224	.ops = &clk_regmap_gate_ops,
1807	.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },	2225	.parent_hws = (const struct clk_hw *[]) {
		2226	&g12a_sd_emmc_a_clk0_div.hw
		2227	},
1808	.num_parents = 1,	2228	.num_parents = 1,
1809	.flags = CLK_SET_RATE_PARENT,	2229	.flags = CLK_SET_RATE_PARENT,
1810	},	2230	},
@@ -1820,8 +2240,8 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_sel = { · 9 unmodified lines
1820	.hw.init = &(struct clk_init_data) {	2240	.hw.init = &(struct clk_init_data) {
1821	.name = "sd_emmc_b_clk0_sel",	2241	.name = "sd_emmc_b_clk0_sel",
1822	.ops = &clk_regmap_mux_ops,	2242	.ops = &clk_regmap_mux_ops,
1823	.parent_names = g12a_sd_emmc_clk0_parent_names,	2243	.parent_data = g12a_sd_emmc_clk0_parent_data,
1824	.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),	2244	.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
1825	.flags = CLK_SET_RATE_PARENT,	2245	.flags = CLK_SET_RATE_PARENT,
1826	},	2246	},
1827	};	2247	};
@@ -1835,7 +2255,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_div = { · 7 unmodified lines
1835	.hw.init = &(struct clk_init_data) {	2255	.hw.init = &(struct clk_init_data) {
1836	.name = "sd_emmc_b_clk0_div",	2256	.name = "sd_emmc_b_clk0_div",
1837	.ops = &clk_regmap_divider_ops,	2257	.ops = &clk_regmap_divider_ops,
1838	.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },	2258	.parent_hws = (const struct clk_hw *[]) {
		2259	&g12a_sd_emmc_b_clk0_sel.hw
		2260	},
1839	.num_parents = 1,	2261	.num_parents = 1,
1840	.flags = CLK_SET_RATE_PARENT,	2262	.flags = CLK_SET_RATE_PARENT,
1841	},	2263	},
@@ -1849,7 +2271,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0 = { · 7 unmodified lines
1849	.hw.init = &(struct clk_init_data){	2271	.hw.init = &(struct clk_init_data){
1850	.name = "sd_emmc_b_clk0",	2272	.name = "sd_emmc_b_clk0",
1851	.ops = &clk_regmap_gate_ops,	2273	.ops = &clk_regmap_gate_ops,
1852	.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },	2274	.parent_hws = (const struct clk_hw *[]) {
		2275	&g12a_sd_emmc_b_clk0_div.hw
		2276	},
1853	.num_parents = 1,	2277	.num_parents = 1,
1854	.flags = CLK_SET_RATE_PARENT,	2278	.flags = CLK_SET_RATE_PARENT,
1855	},	2279	},
@@ -1865,8 +2289,8 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_sel = { · 9 unmodified lines
1865	.hw.init = &(struct clk_init_data) {	2289	.hw.init = &(struct clk_init_data) {
1866	.name = "sd_emmc_c_clk0_sel",	2290	.name = "sd_emmc_c_clk0_sel",
1867	.ops = &clk_regmap_mux_ops,	2291	.ops = &clk_regmap_mux_ops,
1868	.parent_names = g12a_sd_emmc_clk0_parent_names,	2292	.parent_data = g12a_sd_emmc_clk0_parent_data,
1869	.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),	2293	.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
1870	.flags = CLK_SET_RATE_PARENT,	2294	.flags = CLK_SET_RATE_PARENT,
1871	},	2295	},
1872	};	2296	};
@@ -1880,7 +2304,9 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_div = { · 7 unmodified lines
1880	.hw.init = &(struct clk_init_data) {	2304	.hw.init = &(struct clk_init_data) {
1881	.name = "sd_emmc_c_clk0_div",	2305	.name = "sd_emmc_c_clk0_div",
1882	.ops = &clk_regmap_divider_ops,	2306	.ops = &clk_regmap_divider_ops,
1883	.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },	2307	.parent_hws = (const struct clk_hw *[]) {
		2308	&g12a_sd_emmc_c_clk0_sel.hw
		2309	},
1884	.num_parents = 1,	2310	.num_parents = 1,
1885	.flags = CLK_SET_RATE_PARENT,	2311	.flags = CLK_SET_RATE_PARENT,
1886	},	2312	},
@@ -1894,17 +2320,89 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = { · 7 unmodified lines
1894	.hw.init = &(struct clk_init_data){	2320	.hw.init = &(struct clk_init_data){
1895	.name = "sd_emmc_c_clk0",	2321	.name = "sd_emmc_c_clk0",
1896	.ops = &clk_regmap_gate_ops,	2322	.ops = &clk_regmap_gate_ops,
1897	.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },	2323	.parent_hws = (const struct clk_hw *[]) {
		2324	&g12a_sd_emmc_c_clk0_div.hw
		2325	},
1898	.num_parents = 1,	2326	.num_parents = 1,
1899	.flags = CLK_SET_RATE_PARENT,	2327	.flags = CLK_SET_RATE_PARENT,
1900	},	2328	},
1901	};	2329	};
1902		2330
		2331	/* Video Clocks */
		2332
		2333	static struct clk_regmap g12a_vid_pll_div = {
		2334	.data = &(struct meson_vid_pll_div_data){
		2335	.val = {
		2336	.reg_off = HHI_VID_PLL_CLK_DIV,
		2337	.shift = 0,
		2338	.width = 15,
		2339	},
		2340	.sel = {
		2341	.reg_off = HHI_VID_PLL_CLK_DIV,
		2342	.shift = 16,
		2343	.width = 2,
		2344	},
		2345	},
		2346	.hw.init = &(struct clk_init_data) {
		2347	.name = "vid_pll_div",
		2348	.ops = &meson_vid_pll_div_ro_ops,
		2349	.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
		2350	.num_parents = 1,
		2351	.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		2352	},
		2353	};
		2354
		2355	static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
		2356	&g12a_vid_pll_div.hw,
		2357	&g12a_hdmi_pll.hw,
		2358	};
		2359
		2360	static struct clk_regmap g12a_vid_pll_sel = {
		2361	.data = &(struct clk_regmap_mux_data){
		2362	.offset = HHI_VID_PLL_CLK_DIV,
		2363	.mask = 0x1,
		2364	.shift = 18,
		2365	},
		2366	.hw.init = &(struct clk_init_data){
		2367	.name = "vid_pll_sel",
		2368	.ops = &clk_regmap_mux_ops,
		2369	/*
		2370	* bit 18 selects from 2 possible parents:
		2371	* vid_pll_div or hdmi_pll
		2372	*/
		2373	.parent_hws = g12a_vid_pll_parent_hws,
		2374	.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
		2375	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
		2376	},
		2377	};
		2378
		2379	static struct clk_regmap g12a_vid_pll = {
		2380	.data = &(struct clk_regmap_gate_data){
		2381	.offset = HHI_VID_PLL_CLK_DIV,
		2382	.bit_idx = 19,
		2383	},
		2384	.hw.init = &(struct clk_init_data) {
		2385	.name = "vid_pll",
		2386	.ops = &clk_regmap_gate_ops,
		2387	.parent_hws = (const struct clk_hw *[]) {
		2388	&g12a_vid_pll_sel.hw
		2389	},
		2390	.num_parents = 1,
		2391	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
		2392	},
		2393	};
		2394
1903	/* VPU Clock */	2395	/* VPU Clock */
1904		2396
1905	static const char * const g12a_vpu_parent_names[] = {	2397	static const struct clk_hw *g12a_vpu_parent_hws[] = {
1906	"fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",	2398	&g12a_fclk_div3.hw,
1907	"mpll1", "vid_pll", "hifi_pll", "gp0_pll",	2399	&g12a_fclk_div4.hw,
		2400	&g12a_fclk_div5.hw,
		2401	&g12a_fclk_div7.hw,
		2402	&g12a_mpll1.hw,
		2403	&g12a_vid_pll.hw,
		2404	&g12a_hifi_pll.hw,
		2405	&g12a_gp0_pll.hw,
1908	};	2406	};
1909		2407
1910	static struct clk_regmap g12a_vpu_0_sel = {	2408	static struct clk_regmap g12a_vpu_0_sel = {
@@ -1916,8 +2414,8 @@ static struct clk_regmap g12a_vpu_0_sel = { · 5 unmodified lines
1916	.hw.init = &(struct clk_init_data){	2414	.hw.init = &(struct clk_init_data){
1917	.name = "vpu_0_sel",	2415	.name = "vpu_0_sel",
1918	.ops = &clk_regmap_mux_ops,	2416	.ops = &clk_regmap_mux_ops,
1919	.parent_names = g12a_vpu_parent_names,	2417	.parent_hws = g12a_vpu_parent_hws,
1920	.num_parents = ARRAY_SIZE(g12a_vpu_parent_names),	2418	.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
1921	.flags = CLK_SET_RATE_NO_REPARENT,	2419	.flags = CLK_SET_RATE_NO_REPARENT,
1922	},	2420	},
1923	};	2421	};
@@ -1931,7 +2429,7 @@ static struct clk_regmap g12a_vpu_0_div = { · 7 unmodified lines
1931	.hw.init = &(struct clk_init_data){	2429	.hw.init = &(struct clk_init_data){
1932	.name = "vpu_0_div",	2430	.name = "vpu_0_div",
1933	.ops = &clk_regmap_divider_ops,	2431	.ops = &clk_regmap_divider_ops,
1934	.parent_names = (const char *[]){ "vpu_0_sel" },	2432	.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
1935	.num_parents = 1,	2433	.num_parents = 1,
1936	.flags = CLK_SET_RATE_PARENT,	2434	.flags = CLK_SET_RATE_PARENT,
1937	},	2435	},
@@ -1945,7 +2443,7 @@ static struct clk_regmap g12a_vpu_0 = { · 7 unmodified lines
1945	.hw.init = &(struct clk_init_data) {	2443	.hw.init = &(struct clk_init_data) {
1946	.name = "vpu_0",	2444	.name = "vpu_0",
1947	.ops = &clk_regmap_gate_ops,	2445	.ops = &clk_regmap_gate_ops,
1948	.parent_names = (const char *[]){ "vpu_0_div" },	2446	.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
1949	.num_parents = 1,	2447	.num_parents = 1,
1950	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2448	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1951	},	2449	},
@@ -1960,8 +2458,8 @@ static struct clk_regmap g12a_vpu_1_sel = { · 8 unmodified lines
1960	.hw.init = &(struct clk_init_data){	2458	.hw.init = &(struct clk_init_data){
1961	.name = "vpu_1_sel",	2459	.name = "vpu_1_sel",
1962	.ops = &clk_regmap_mux_ops,	2460	.ops = &clk_regmap_mux_ops,
1963	.parent_names = g12a_vpu_parent_names,	2461	.parent_hws = g12a_vpu_parent_hws,
1964	.num_parents = ARRAY_SIZE(g12a_vpu_parent_names),	2462	.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
1965	.flags = CLK_SET_RATE_NO_REPARENT,	2463	.flags = CLK_SET_RATE_NO_REPARENT,
1966	},	2464	},
1967	};	2465	};
@@ -1975,7 +2473,7 @@ static struct clk_regmap g12a_vpu_1_div = { · 7 unmodified lines
1975	.hw.init = &(struct clk_init_data){	2473	.hw.init = &(struct clk_init_data){
1976	.name = "vpu_1_div",	2474	.name = "vpu_1_div",
1977	.ops = &clk_regmap_divider_ops,	2475	.ops = &clk_regmap_divider_ops,
1978	.parent_names = (const char *[]){ "vpu_1_sel" },	2476	.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
1979	.num_parents = 1,	2477	.num_parents = 1,
1980	.flags = CLK_SET_RATE_PARENT,	2478	.flags = CLK_SET_RATE_PARENT,
1981	},	2479	},
@@ -1989,7 +2487,7 @@ static struct clk_regmap g12a_vpu_1 = { · 7 unmodified lines
1989	.hw.init = &(struct clk_init_data) {	2487	.hw.init = &(struct clk_init_data) {
1990	.name = "vpu_1",	2488	.name = "vpu_1",
1991	.ops = &clk_regmap_gate_ops,	2489	.ops = &clk_regmap_gate_ops,
1992	.parent_names = (const char *[]){ "vpu_1_div" },	2490	.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
1993	.num_parents = 1,	2491	.num_parents = 1,
1994	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2492	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1995	},	2493	},
@@ -2008,7 +2506,10 @@ static struct clk_regmap g12a_vpu = { · 12 unmodified lines
2008	* bit 31 selects from 2 possible parents:	2506	* bit 31 selects from 2 possible parents:
2009	* vpu_0 or vpu_1	2507	* vpu_0 or vpu_1
2010	*/	2508	*/
2011	.parent_names = (const char *[]){ "vpu_0", "vpu_1" },	2509	.parent_hws = (const struct clk_hw *[]) {
		2510	&g12a_vpu_0.hw,
		2511	&g12a_vpu_1.hw,
		2512	},
2012	.num_parents = 2,	2513	.num_parents = 2,
2013	.flags = CLK_SET_RATE_NO_REPARENT,	2514	.flags = CLK_SET_RATE_NO_REPARENT,
2014	},	2515	},
@@ -2016,9 +2517,14 @@ static struct clk_regmap g12a_vpu = { · 1 unmodified line
2016		2517
2017	/* VDEC clocks */	2518	/* VDEC clocks */
2018		2519
2019	static const char * const g12a_vdec_parent_names[] = {	2520	static const struct clk_hw *g12a_vdec_parent_hws[] = {
2020	"fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",	2521	&g12a_fclk_div2p5.hw,
2021	"hifi_pll", "gp0_pll",	2522	&g12a_fclk_div3.hw,
		2523	&g12a_fclk_div4.hw,
		2524	&g12a_fclk_div5.hw,
		2525	&g12a_fclk_div7.hw,
		2526	&g12a_hifi_pll.hw,
		2527	&g12a_gp0_pll.hw,
2022	};	2528	};
2023		2529
2024	static struct clk_regmap g12a_vdec_1_sel = {	2530	static struct clk_regmap g12a_vdec_1_sel = {
@@ -2031,8 +2537,8 @@ static struct clk_regmap g12a_vdec_1_sel = { · 6 unmodified lines
2031	.hw.init = &(struct clk_init_data){	2537	.hw.init = &(struct clk_init_data){
2032	.name = "vdec_1_sel",	2538	.name = "vdec_1_sel",
2033	.ops = &clk_regmap_mux_ops,	2539	.ops = &clk_regmap_mux_ops,
2034	.parent_names = g12a_vdec_parent_names,	2540	.parent_hws = g12a_vdec_parent_hws,
2035	.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),	2541	.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2036	.flags = CLK_SET_RATE_PARENT,	2542	.flags = CLK_SET_RATE_PARENT,
2037	},	2543	},
2038	};	2544	};
@@ -2047,7 +2553,9 @@ static struct clk_regmap g12a_vdec_1_div = { · 8 unmodified lines
2047	.hw.init = &(struct clk_init_data){	2553	.hw.init = &(struct clk_init_data){
2048	.name = "vdec_1_div",	2554	.name = "vdec_1_div",
2049	.ops = &clk_regmap_divider_ops,	2555	.ops = &clk_regmap_divider_ops,
2050	.parent_names = (const char *[]){ "vdec_1_sel" },	2556	.parent_hws = (const struct clk_hw *[]) {
		2557	&g12a_vdec_1_sel.hw
		2558	},
2051	.num_parents = 1,	2559	.num_parents = 1,
2052	.flags = CLK_SET_RATE_PARENT,	2560	.flags = CLK_SET_RATE_PARENT,
2053	},	2561	},
@@ -2061,7 +2569,9 @@ static struct clk_regmap g12a_vdec_1 = { · 7 unmodified lines
2061	.hw.init = &(struct clk_init_data) {	2569	.hw.init = &(struct clk_init_data) {
2062	.name = "vdec_1",	2570	.name = "vdec_1",
2063	.ops = &clk_regmap_gate_ops,	2571	.ops = &clk_regmap_gate_ops,
2064	.parent_names = (const char *[]){ "vdec_1_div" },	2572	.parent_hws = (const struct clk_hw *[]) {
		2573	&g12a_vdec_1_div.hw
		2574	},
2065	.num_parents = 1,	2575	.num_parents = 1,
2066	.flags = CLK_SET_RATE_PARENT,	2576	.flags = CLK_SET_RATE_PARENT,
2067	},	2577	},
@@ -2077,8 +2587,8 @@ static struct clk_regmap g12a_vdec_hevcf_sel = { · 9 unmodified lines
2077	.hw.init = &(struct clk_init_data){	2587	.hw.init = &(struct clk_init_data){
2078	.name = "vdec_hevcf_sel",	2588	.name = "vdec_hevcf_sel",
2079	.ops = &clk_regmap_mux_ops,	2589	.ops = &clk_regmap_mux_ops,
2080	.parent_names = g12a_vdec_parent_names,	2590	.parent_hws = g12a_vdec_parent_hws,
2081	.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),	2591	.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2082	.flags = CLK_SET_RATE_PARENT,	2592	.flags = CLK_SET_RATE_PARENT,
2083	},	2593	},
2084	};	2594	};
@@ -2093,7 +2603,9 @@ static struct clk_regmap g12a_vdec_hevcf_div = { · 8 unmodified lines
2093	.hw.init = &(struct clk_init_data){	2603	.hw.init = &(struct clk_init_data){
2094	.name = "vdec_hevcf_div",	2604	.name = "vdec_hevcf_div",
2095	.ops = &clk_regmap_divider_ops,	2605	.ops = &clk_regmap_divider_ops,
2096	.parent_names = (const char *[]){ "vdec_hevcf_sel" },	2606	.parent_hws = (const struct clk_hw *[]) {
		2607	&g12a_vdec_hevcf_sel.hw
		2608	},
2097	.num_parents = 1,	2609	.num_parents = 1,
2098	.flags = CLK_SET_RATE_PARENT,	2610	.flags = CLK_SET_RATE_PARENT,
2099	},	2611	},
@@ -2107,7 +2619,9 @@ static struct clk_regmap g12a_vdec_hevcf = { · 7 unmodified lines
2107	.hw.init = &(struct clk_init_data) {	2619	.hw.init = &(struct clk_init_data) {
2108	.name = "vdec_hevcf",	2620	.name = "vdec_hevcf",
2109	.ops = &clk_regmap_gate_ops,	2621	.ops = &clk_regmap_gate_ops,
2110	.parent_names = (const char *[]){ "vdec_hevcf_div" },	2622	.parent_hws = (const struct clk_hw *[]) {
		2623	&g12a_vdec_hevcf_div.hw
		2624	},
2111	.num_parents = 1,	2625	.num_parents = 1,
2112	.flags = CLK_SET_RATE_PARENT,	2626	.flags = CLK_SET_RATE_PARENT,
2113	},	2627	},
@@ -2123,8 +2637,8 @@ static struct clk_regmap g12a_vdec_hevc_sel = { · 9 unmodified lines
2123	.hw.init = &(struct clk_init_data){	2637	.hw.init = &(struct clk_init_data){
2124	.name = "vdec_hevc_sel",	2638	.name = "vdec_hevc_sel",
2125	.ops = &clk_regmap_mux_ops,	2639	.ops = &clk_regmap_mux_ops,
2126	.parent_names = g12a_vdec_parent_names,	2640	.parent_hws = g12a_vdec_parent_hws,
2127	.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),	2641	.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2128	.flags = CLK_SET_RATE_PARENT,	2642	.flags = CLK_SET_RATE_PARENT,
2129	},	2643	},
2130	};	2644	};
@@ -2139,7 +2653,9 @@ static struct clk_regmap g12a_vdec_hevc_div = { · 8 unmodified lines
2139	.hw.init = &(struct clk_init_data){	2653	.hw.init = &(struct clk_init_data){
2140	.name = "vdec_hevc_div",	2654	.name = "vdec_hevc_div",
2141	.ops = &clk_regmap_divider_ops,	2655	.ops = &clk_regmap_divider_ops,
2142	.parent_names = (const char *[]){ "vdec_hevc_sel" },	2656	.parent_hws = (const struct clk_hw *[]) {
		2657	&g12a_vdec_hevc_sel.hw
		2658	},
2143	.num_parents = 1,	2659	.num_parents = 1,
2144	.flags = CLK_SET_RATE_PARENT,	2660	.flags = CLK_SET_RATE_PARENT,
2145	},	2661	},
@@ -2153,7 +2669,9 @@ static struct clk_regmap g12a_vdec_hevc = { · 7 unmodified lines
2153	.hw.init = &(struct clk_init_data) {	2669	.hw.init = &(struct clk_init_data) {
2154	.name = "vdec_hevc",	2670	.name = "vdec_hevc",
2155	.ops = &clk_regmap_gate_ops,	2671	.ops = &clk_regmap_gate_ops,
2156	.parent_names = (const char *[]){ "vdec_hevc_div" },	2672	.parent_hws = (const struct clk_hw *[]) {
		2673	&g12a_vdec_hevc_div.hw
		2674	},
2157	.num_parents = 1,	2675	.num_parents = 1,
2158	.flags = CLK_SET_RATE_PARENT,	2676	.flags = CLK_SET_RATE_PARENT,
2159	},	2677	},
@@ -2161,9 +2679,15 @@ static struct clk_regmap g12a_vdec_hevc = { · 1 unmodified line
2161		2679
2162	/* VAPB Clock */	2680	/* VAPB Clock */
2163		2681
2164	static const char * const g12a_vapb_parent_names[] = {	2682	static const struct clk_hw *g12a_vapb_parent_hws[] = {
2165	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",	2683	&g12a_fclk_div4.hw,
2166	"mpll1", "vid_pll", "mpll2", "fclk_div2p5",	2684	&g12a_fclk_div3.hw,
		2685	&g12a_fclk_div5.hw,
		2686	&g12a_fclk_div7.hw,
		2687	&g12a_mpll1.hw,
		2688	&g12a_vid_pll.hw,
		2689	&g12a_mpll2.hw,
		2690	&g12a_fclk_div2p5.hw,
2167	};	2691	};
2168		2692
2169	static struct clk_regmap g12a_vapb_0_sel = {	2693	static struct clk_regmap g12a_vapb_0_sel = {
@@ -2175,8 +2699,8 @@ static struct clk_regmap g12a_vapb_0_sel = { · 5 unmodified lines
2175	.hw.init = &(struct clk_init_data){	2699	.hw.init = &(struct clk_init_data){
2176	.name = "vapb_0_sel",	2700	.name = "vapb_0_sel",
2177	.ops = &clk_regmap_mux_ops,	2701	.ops = &clk_regmap_mux_ops,
2178	.parent_names = g12a_vapb_parent_names,	2702	.parent_hws = g12a_vapb_parent_hws,
2179	.num_parents = ARRAY_SIZE(g12a_vapb_parent_names),	2703	.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
2180	.flags = CLK_SET_RATE_NO_REPARENT,	2704	.flags = CLK_SET_RATE_NO_REPARENT,
2181	},	2705	},
2182	};	2706	};
@@ -2190,7 +2714,9 @@ static struct clk_regmap g12a_vapb_0_div = { · 7 unmodified lines
2190	.hw.init = &(struct clk_init_data){	2714	.hw.init = &(struct clk_init_data){
2191	.name = "vapb_0_div",	2715	.name = "vapb_0_div",
2192	.ops = &clk_regmap_divider_ops,	2716	.ops = &clk_regmap_divider_ops,
2193	.parent_names = (const char *[]){ "vapb_0_sel" },	2717	.parent_hws = (const struct clk_hw *[]) {
		2718	&g12a_vapb_0_sel.hw
		2719	},
2194	.num_parents = 1,	2720	.num_parents = 1,
2195	.flags = CLK_SET_RATE_PARENT,	2721	.flags = CLK_SET_RATE_PARENT,
2196	},	2722	},
@@ -2204,7 +2730,9 @@ static struct clk_regmap g12a_vapb_0 = { · 7 unmodified lines
2204	.hw.init = &(struct clk_init_data) {	2730	.hw.init = &(struct clk_init_data) {
2205	.name = "vapb_0",	2731	.name = "vapb_0",
2206	.ops = &clk_regmap_gate_ops,	2732	.ops = &clk_regmap_gate_ops,
2207	.parent_names = (const char *[]){ "vapb_0_div" },	2733	.parent_hws = (const struct clk_hw *[]) {
		2734	&g12a_vapb_0_div.hw
		2735	},
2208	.num_parents = 1,	2736	.num_parents = 1,
2209	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2737	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2210	},	2738	},
@@ -2219,8 +2747,8 @@ static struct clk_regmap g12a_vapb_1_sel = { · 8 unmodified lines
2219	.hw.init = &(struct clk_init_data){	2747	.hw.init = &(struct clk_init_data){
2220	.name = "vapb_1_sel",	2748	.name = "vapb_1_sel",
2221	.ops = &clk_regmap_mux_ops,	2749	.ops = &clk_regmap_mux_ops,
2222	.parent_names = g12a_vapb_parent_names,	2750	.parent_hws = g12a_vapb_parent_hws,
2223	.num_parents = ARRAY_SIZE(g12a_vapb_parent_names),	2751	.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
2224	.flags = CLK_SET_RATE_NO_REPARENT,	2752	.flags = CLK_SET_RATE_NO_REPARENT,
2225	},	2753	},
2226	};	2754	};
@@ -2234,7 +2762,9 @@ static struct clk_regmap g12a_vapb_1_div = { · 7 unmodified lines
2234	.hw.init = &(struct clk_init_data){	2762	.hw.init = &(struct clk_init_data){
2235	.name = "vapb_1_div",	2763	.name = "vapb_1_div",
2236	.ops = &clk_regmap_divider_ops,	2764	.ops = &clk_regmap_divider_ops,
2237	.parent_names = (const char *[]){ "vapb_1_sel" },	2765	.parent_hws = (const struct clk_hw *[]) {
		2766	&g12a_vapb_1_sel.hw
		2767	},
2238	.num_parents = 1,	2768	.num_parents = 1,
2239	.flags = CLK_SET_RATE_PARENT,	2769	.flags = CLK_SET_RATE_PARENT,
2240	},	2770	},
@@ -2248,7 +2778,9 @@ static struct clk_regmap g12a_vapb_1 = { · 7 unmodified lines
2248	.hw.init = &(struct clk_init_data) {	2778	.hw.init = &(struct clk_init_data) {
2249	.name = "vapb_1",	2779	.name = "vapb_1",
2250	.ops = &clk_regmap_gate_ops,	2780	.ops = &clk_regmap_gate_ops,
2251	.parent_names = (const char *[]){ "vapb_1_div" },	2781	.parent_hws = (const struct clk_hw *[]) {
		2782	&g12a_vapb_1_div.hw
		2783	},
2252	.num_parents = 1,	2784	.num_parents = 1,
2253	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2785	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2254	},	2786	},
@@ -2267,7 +2799,10 @@ static struct clk_regmap g12a_vapb_sel = { · 12 unmodified lines
2267	* bit 31 selects from 2 possible parents:	2799	* bit 31 selects from 2 possible parents:
2268	* vapb_0 or vapb_1	2800	* vapb_0 or vapb_1
2269	*/	2801	*/
2270	.parent_names = (const char *[]){ "vapb_0", "vapb_1" },	2802	.parent_hws = (const struct clk_hw *[]) {
		2803	&g12a_vapb_0.hw,
		2804	&g12a_vapb_1.hw,
		2805	},
2271	.num_parents = 2,	2806	.num_parents = 2,
2272	.flags = CLK_SET_RATE_NO_REPARENT,	2807	.flags = CLK_SET_RATE_NO_REPARENT,
2273	},	2808	},
@@ -2281,75 +2816,21 @@ static struct clk_regmap g12a_vapb = { · 7 unmodified lines
2281	.hw.init = &(struct clk_init_data) {	2816	.hw.init = &(struct clk_init_data) {
2282	.name = "vapb",	2817	.name = "vapb",
2283	.ops = &clk_regmap_gate_ops,	2818	.ops = &clk_regmap_gate_ops,
2284	.parent_names = (const char *[]){ "vapb_sel" },	2819	.parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
2285	.num_parents = 1,	2820	.num_parents = 1,
2286	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2821	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2287	},	2822	},
2288	};	2823	};
2289		2824
2290	/* Video Clocks */	2825	static const struct clk_hw *g12a_vclk_parent_hws[] = {
2291		2826	&g12a_vid_pll.hw,
2292	static struct clk_regmap g12a_vid_pll_div = {	2827	&g12a_gp0_pll.hw,
2293	.data = &(struct meson_vid_pll_div_data){	2828	&g12a_hifi_pll.hw,
2294	.val = {	2829	&g12a_mpll1.hw,
2295	.reg_off = HHI_VID_PLL_CLK_DIV,	2830	&g12a_fclk_div3.hw,
2296	.shift = 0,	2831	&g12a_fclk_div4.hw,
2297	.width = 15,	2832	&g12a_fclk_div5.hw,
2298	},	2833	&g12a_fclk_div7.hw,
2299	.sel = {
2300	.reg_off = HHI_VID_PLL_CLK_DIV,
2301	.shift = 16,
2302	.width = 2,
2303	},
2304	},
2305	.hw.init = &(struct clk_init_data) {
2306	.name = "vid_pll_div",
2307	.ops = &meson_vid_pll_div_ro_ops,
2308	.parent_names = (const char *[]){ "hdmi_pll" },
2309	.num_parents = 1,
2310	.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
2311	},
2312	};
2313
2314	static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
2315	"hdmi_pll" };
2316
2317	static struct clk_regmap g12a_vid_pll_sel = {
2318	.data = &(struct clk_regmap_mux_data){
2319	.offset = HHI_VID_PLL_CLK_DIV,
2320	.mask = 0x1,
2321	.shift = 18,
2322	},
2323	.hw.init = &(struct clk_init_data){
2324	.name = "vid_pll_sel",
2325	.ops = &clk_regmap_mux_ops,
2326	/*
2327	* bit 18 selects from 2 possible parents:
2328	* vid_pll_div or hdmi_pll
2329	*/
2330	.parent_names = g12a_vid_pll_parent_names,
2331	.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
2332	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2333	},
2334	};
2335
2336	static struct clk_regmap g12a_vid_pll = {
2337	.data = &(struct clk_regmap_gate_data){
2338	.offset = HHI_VID_PLL_CLK_DIV,
2339	.bit_idx = 19,
2340	},
2341	.hw.init = &(struct clk_init_data) {
2342	.name = "vid_pll",
2343	.ops = &clk_regmap_gate_ops,
2344	.parent_names = (const char *[]){ "vid_pll_sel" },
2345	.num_parents = 1,
2346	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2347	},
2348	};
2349
2350	static const char * const g12a_vclk_parent_names[] = {
2351	"vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
2352	"fclk_div5", "fclk_div7"
2353	};	2834	};
2354		2835
2355	static struct clk_regmap g12a_vclk_sel = {	2836	static struct clk_regmap g12a_vclk_sel = {
@@ -2361,8 +2842,8 @@ static struct clk_regmap g12a_vclk_sel = { · 5 unmodified lines
2361	.hw.init = &(struct clk_init_data){	2842	.hw.init = &(struct clk_init_data){
2362	.name = "vclk_sel",	2843	.name = "vclk_sel",
2363	.ops = &clk_regmap_mux_ops,	2844	.ops = &clk_regmap_mux_ops,
2364	.parent_names = g12a_vclk_parent_names,	2845	.parent_hws = g12a_vclk_parent_hws,
2365	.num_parents = ARRAY_SIZE(g12a_vclk_parent_names),	2846	.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
2366	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	2847	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2367	},	2848	},
2368	};	2849	};
@@ -2376,8 +2857,8 @@ static struct clk_regmap g12a_vclk2_sel = { · 7 unmodified lines
2376	.hw.init = &(struct clk_init_data){	2857	.hw.init = &(struct clk_init_data){
2377	.name = "vclk2_sel",	2858	.name = "vclk2_sel",
2378	.ops = &clk_regmap_mux_ops,	2859	.ops = &clk_regmap_mux_ops,
2379	.parent_names = g12a_vclk_parent_names,	2860	.parent_hws = g12a_vclk_parent_hws,
2380	.num_parents = ARRAY_SIZE(g12a_vclk_parent_names),	2861	.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
2381	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	2862	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2382	},	2863	},
2383	};	2864	};
@@ -2390,7 +2871,7 @@ static struct clk_regmap g12a_vclk_input = { · 6 unmodified lines
2390	.hw.init = &(struct clk_init_data) {	2871	.hw.init = &(struct clk_init_data) {
2391	.name = "vclk_input",	2872	.name = "vclk_input",
2392	.ops = &clk_regmap_gate_ops,	2873	.ops = &clk_regmap_gate_ops,
2393	.parent_names = (const char *[]){ "vclk_sel" },	2874	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
2394	.num_parents = 1,	2875	.num_parents = 1,
2395	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2876	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2396	},	2877	},
@@ -2404,7 +2885,7 @@ static struct clk_regmap g12a_vclk2_input = { · 7 unmodified lines
2404	.hw.init = &(struct clk_init_data) {	2885	.hw.init = &(struct clk_init_data) {
2405	.name = "vclk2_input",	2886	.name = "vclk2_input",
2406	.ops = &clk_regmap_gate_ops,	2887	.ops = &clk_regmap_gate_ops,
2407	.parent_names = (const char *[]){ "vclk2_sel" },	2888	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
2408	.num_parents = 1,	2889	.num_parents = 1,
2409	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2890	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2410	},	2891	},
@@ -2419,7 +2900,9 @@ static struct clk_regmap g12a_vclk_div = { · 8 unmodified lines
2419	.hw.init = &(struct clk_init_data){	2900	.hw.init = &(struct clk_init_data){
2420	.name = "vclk_div",	2901	.name = "vclk_div",
2421	.ops = &clk_regmap_divider_ops,	2902	.ops = &clk_regmap_divider_ops,
2422	.parent_names = (const char *[]){ "vclk_input" },	2903	.parent_hws = (const struct clk_hw *[]) {
		2904	&g12a_vclk_input.hw
		2905	},
2423	.num_parents = 1,	2906	.num_parents = 1,
2424	.flags = CLK_GET_RATE_NOCACHE,	2907	.flags = CLK_GET_RATE_NOCACHE,
2425	},	2908	},
@@ -2434,7 +2917,9 @@ static struct clk_regmap g12a_vclk2_div = { · 8 unmodified lines
2434	.hw.init = &(struct clk_init_data){	2917	.hw.init = &(struct clk_init_data){
2435	.name = "vclk2_div",	2918	.name = "vclk2_div",
2436	.ops = &clk_regmap_divider_ops,	2919	.ops = &clk_regmap_divider_ops,
2437	.parent_names = (const char *[]){ "vclk2_input" },	2920	.parent_hws = (const struct clk_hw *[]) {
		2921	&g12a_vclk2_input.hw
		2922	},
2438	.num_parents = 1,	2923	.num_parents = 1,
2439	.flags = CLK_GET_RATE_NOCACHE,	2924	.flags = CLK_GET_RATE_NOCACHE,
2440	},	2925	},
@@ -2448,7 +2933,7 @@ static struct clk_regmap g12a_vclk = { · 7 unmodified lines
2448	.hw.init = &(struct clk_init_data) {	2933	.hw.init = &(struct clk_init_data) {
2449	.name = "vclk",	2934	.name = "vclk",
2450	.ops = &clk_regmap_gate_ops,	2935	.ops = &clk_regmap_gate_ops,
2451	.parent_names = (const char *[]){ "vclk_div" },	2936	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
2452	.num_parents = 1,	2937	.num_parents = 1,
2453	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2938	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2454	},	2939	},
@@ -2462,7 +2947,7 @@ static struct clk_regmap g12a_vclk2 = { · 7 unmodified lines
2462	.hw.init = &(struct clk_init_data) {	2947	.hw.init = &(struct clk_init_data) {
2463	.name = "vclk2",	2948	.name = "vclk2",
2464	.ops = &clk_regmap_gate_ops,	2949	.ops = &clk_regmap_gate_ops,
2465	.parent_names = (const char *[]){ "vclk2_div" },	2950	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
2466	.num_parents = 1,	2951	.num_parents = 1,
2467	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2952	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2468	},	2953	},
@@ -2476,7 +2961,7 @@ static struct clk_regmap g12a_vclk_div1 = { · 7 unmodified lines
2476	.hw.init = &(struct clk_init_data) {	2961	.hw.init = &(struct clk_init_data) {
2477	.name = "vclk_div1",	2962	.name = "vclk_div1",
2478	.ops = &clk_regmap_gate_ops,	2963	.ops = &clk_regmap_gate_ops,
2479	.parent_names = (const char *[]){ "vclk" },	2964	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2480	.num_parents = 1,	2965	.num_parents = 1,
2481	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2966	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2482	},	2967	},
@@ -2490,7 +2975,7 @@ static struct clk_regmap g12a_vclk_div2_en = { · 7 unmodified lines
2490	.hw.init = &(struct clk_init_data) {	2975	.hw.init = &(struct clk_init_data) {
2491	.name = "vclk_div2_en",	2976	.name = "vclk_div2_en",
2492	.ops = &clk_regmap_gate_ops,	2977	.ops = &clk_regmap_gate_ops,
2493	.parent_names = (const char *[]){ "vclk" },	2978	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2494	.num_parents = 1,	2979	.num_parents = 1,
2495	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2980	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2496	},	2981	},
@@ -2504,7 +2989,7 @@ static struct clk_regmap g12a_vclk_div4_en = { · 7 unmodified lines
2504	.hw.init = &(struct clk_init_data) {	2989	.hw.init = &(struct clk_init_data) {
2505	.name = "vclk_div4_en",	2990	.name = "vclk_div4_en",
2506	.ops = &clk_regmap_gate_ops,	2991	.ops = &clk_regmap_gate_ops,
2507	.parent_names = (const char *[]){ "vclk" },	2992	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2508	.num_parents = 1,	2993	.num_parents = 1,
2509	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2994	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2510	},	2995	},
@@ -2518,7 +3003,7 @@ static struct clk_regmap g12a_vclk_div6_en = { · 7 unmodified lines
2518	.hw.init = &(struct clk_init_data) {	3003	.hw.init = &(struct clk_init_data) {
2519	.name = "vclk_div6_en",	3004	.name = "vclk_div6_en",
2520	.ops = &clk_regmap_gate_ops,	3005	.ops = &clk_regmap_gate_ops,
2521	.parent_names = (const char *[]){ "vclk" },	3006	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2522	.num_parents = 1,	3007	.num_parents = 1,
2523	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3008	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2524	},	3009	},
@@ -2532,7 +3017,7 @@ static struct clk_regmap g12a_vclk_div12_en = { · 7 unmodified lines
2532	.hw.init = &(struct clk_init_data) {	3017	.hw.init = &(struct clk_init_data) {
2533	.name = "vclk_div12_en",	3018	.name = "vclk_div12_en",
2534	.ops = &clk_regmap_gate_ops,	3019	.ops = &clk_regmap_gate_ops,
2535	.parent_names = (const char *[]){ "vclk" },	3020	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2536	.num_parents = 1,	3021	.num_parents = 1,
2537	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3022	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2538	},	3023	},
@@ -2546,7 +3031,7 @@ static struct clk_regmap g12a_vclk2_div1 = { · 7 unmodified lines
2546	.hw.init = &(struct clk_init_data) {	3031	.hw.init = &(struct clk_init_data) {
2547	.name = "vclk2_div1",	3032	.name = "vclk2_div1",
2548	.ops = &clk_regmap_gate_ops,	3033	.ops = &clk_regmap_gate_ops,
2549	.parent_names = (const char *[]){ "vclk2" },	3034	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2550	.num_parents = 1,	3035	.num_parents = 1,
2551	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3036	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2552	},	3037	},
@@ -2560,7 +3045,7 @@ static struct clk_regmap g12a_vclk2_div2_en = { · 7 unmodified lines
2560	.hw.init = &(struct clk_init_data) {	3045	.hw.init = &(struct clk_init_data) {
2561	.name = "vclk2_div2_en",	3046	.name = "vclk2_div2_en",
2562	.ops = &clk_regmap_gate_ops,	3047	.ops = &clk_regmap_gate_ops,
2563	.parent_names = (const char *[]){ "vclk2" },	3048	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2564	.num_parents = 1,	3049	.num_parents = 1,
2565	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3050	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2566	},	3051	},
@@ -2574,7 +3059,7 @@ static struct clk_regmap g12a_vclk2_div4_en = { · 7 unmodified lines
2574	.hw.init = &(struct clk_init_data) {	3059	.hw.init = &(struct clk_init_data) {
2575	.name = "vclk2_div4_en",	3060	.name = "vclk2_div4_en",
2576	.ops = &clk_regmap_gate_ops,	3061	.ops = &clk_regmap_gate_ops,
2577	.parent_names = (const char *[]){ "vclk2" },	3062	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2578	.num_parents = 1,	3063	.num_parents = 1,
2579	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3064	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2580	},	3065	},
@@ -2588,7 +3073,7 @@ static struct clk_regmap g12a_vclk2_div6_en = { · 7 unmodified lines
2588	.hw.init = &(struct clk_init_data) {	3073	.hw.init = &(struct clk_init_data) {
2589	.name = "vclk2_div6_en",	3074	.name = "vclk2_div6_en",
2590	.ops = &clk_regmap_gate_ops,	3075	.ops = &clk_regmap_gate_ops,
2591	.parent_names = (const char *[]){ "vclk2" },	3076	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2592	.num_parents = 1,	3077	.num_parents = 1,
2593	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3078	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2594	},	3079	},
@@ -2602,7 +3087,7 @@ static struct clk_regmap g12a_vclk2_div12_en = { · 7 unmodified lines
2602	.hw.init = &(struct clk_init_data) {	3087	.hw.init = &(struct clk_init_data) {
2603	.name = "vclk2_div12_en",	3088	.name = "vclk2_div12_en",
2604	.ops = &clk_regmap_gate_ops,	3089	.ops = &clk_regmap_gate_ops,
2605	.parent_names = (const char *[]){ "vclk2" },	3090	.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2606	.num_parents = 1,	3091	.num_parents = 1,
2607	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3092	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2608	},	3093	},
@@ -2614,7 +3099,9 @@ static struct clk_fixed_factor g12a_vclk_div2 = { · 5 unmodified lines
2614	.hw.init = &(struct clk_init_data){	3099	.hw.init = &(struct clk_init_data){
2615	.name = "vclk_div2",	3100	.name = "vclk_div2",
2616	.ops = &clk_fixed_factor_ops,	3101	.ops = &clk_fixed_factor_ops,
2617	.parent_names = (const char *[]){ "vclk_div2_en" },	3102	.parent_hws = (const struct clk_hw *[]) {
		3103	&g12a_vclk_div2_en.hw
		3104	},
2618	.num_parents = 1,	3105	.num_parents = 1,
2619	},	3106	},
2620	};	3107	};
@@ -2625,7 +3112,9 @@ static struct clk_fixed_factor g12a_vclk_div4 = { · 4 unmodified lines
2625	.hw.init = &(struct clk_init_data){	3112	.hw.init = &(struct clk_init_data){
2626	.name = "vclk_div4",	3113	.name = "vclk_div4",
2627	.ops = &clk_fixed_factor_ops,	3114	.ops = &clk_fixed_factor_ops,
2628	.parent_names = (const char *[]){ "vclk_div4_en" },	3115	.parent_hws = (const struct clk_hw *[]) {
		3116	&g12a_vclk_div4_en.hw
		3117	},
2629	.num_parents = 1,	3118	.num_parents = 1,
2630	},	3119	},
2631	};	3120	};
@@ -2636,7 +3125,9 @@ static struct clk_fixed_factor g12a_vclk_div6 = { · 4 unmodified lines
2636	.hw.init = &(struct clk_init_data){	3125	.hw.init = &(struct clk_init_data){
2637	.name = "vclk_div6",	3126	.name = "vclk_div6",
2638	.ops = &clk_fixed_factor_ops,	3127	.ops = &clk_fixed_factor_ops,
2639	.parent_names = (const char *[]){ "vclk_div6_en" },	3128	.parent_hws = (const struct clk_hw *[]) {
		3129	&g12a_vclk_div6_en.hw
		3130	},
2640	.num_parents = 1,	3131	.num_parents = 1,
2641	},	3132	},
2642	};	3133	};
@@ -2647,7 +3138,9 @@ static struct clk_fixed_factor g12a_vclk_div12 = { · 4 unmodified lines
2647	.hw.init = &(struct clk_init_data){	3138	.hw.init = &(struct clk_init_data){
2648	.name = "vclk_div12",	3139	.name = "vclk_div12",
2649	.ops = &clk_fixed_factor_ops,	3140	.ops = &clk_fixed_factor_ops,
2650	.parent_names = (const char *[]){ "vclk_div12_en" },	3141	.parent_hws = (const struct clk_hw *[]) {
		3142	&g12a_vclk_div12_en.hw
		3143	},
2651	.num_parents = 1,	3144	.num_parents = 1,
2652	},	3145	},
2653	};	3146	};
@@ -2658,7 +3151,9 @@ static struct clk_fixed_factor g12a_vclk2_div2 = { · 4 unmodified lines
2658	.hw.init = &(struct clk_init_data){	3151	.hw.init = &(struct clk_init_data){
2659	.name = "vclk2_div2",	3152	.name = "vclk2_div2",
2660	.ops = &clk_fixed_factor_ops,	3153	.ops = &clk_fixed_factor_ops,
2661	.parent_names = (const char *[]){ "vclk2_div2_en" },	3154	.parent_hws = (const struct clk_hw *[]) {
		3155	&g12a_vclk2_div2_en.hw
		3156	},
2662	.num_parents = 1,	3157	.num_parents = 1,
2663	},	3158	},
2664	};	3159	};
@@ -2669,7 +3164,9 @@ static struct clk_fixed_factor g12a_vclk2_div4 = { · 4 unmodified lines
2669	.hw.init = &(struct clk_init_data){	3164	.hw.init = &(struct clk_init_data){
2670	.name = "vclk2_div4",	3165	.name = "vclk2_div4",
2671	.ops = &clk_fixed_factor_ops,	3166	.ops = &clk_fixed_factor_ops,
2672	.parent_names = (const char *[]){ "vclk2_div4_en" },	3167	.parent_hws = (const struct clk_hw *[]) {
		3168	&g12a_vclk2_div4_en.hw
		3169	},
2673	.num_parents = 1,	3170	.num_parents = 1,
2674	},	3171	},
2675	};	3172	};
@@ -2680,7 +3177,9 @@ static struct clk_fixed_factor g12a_vclk2_div6 = { · 4 unmodified lines
2680	.hw.init = &(struct clk_init_data){	3177	.hw.init = &(struct clk_init_data){
2681	.name = "vclk2_div6",	3178	.name = "vclk2_div6",
2682	.ops = &clk_fixed_factor_ops,	3179	.ops = &clk_fixed_factor_ops,
2683	.parent_names = (const char *[]){ "vclk2_div6_en" },	3180	.parent_hws = (const struct clk_hw *[]) {
		3181	&g12a_vclk2_div6_en.hw
		3182	},
2684	.num_parents = 1,	3183	.num_parents = 1,
2685	},	3184	},
2686	};	3185	};
@@ -2691,16 +3190,25 @@ static struct clk_fixed_factor g12a_vclk2_div12 = { · 4 unmodified lines
2691	.hw.init = &(struct clk_init_data){	3190	.hw.init = &(struct clk_init_data){
2692	.name = "vclk2_div12",	3191	.name = "vclk2_div12",
2693	.ops = &clk_fixed_factor_ops,	3192	.ops = &clk_fixed_factor_ops,
2694	.parent_names = (const char *[]){ "vclk2_div12_en" },	3193	.parent_hws = (const struct clk_hw *[]) {
		3194	&g12a_vclk2_div12_en.hw
		3195	},
2695	.num_parents = 1,	3196	.num_parents = 1,
2696	},	3197	},
2697	};	3198	};
2698		3199
2699	static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };	3200	static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2700	static const char * const g12a_cts_parent_names[] = {	3201	static const struct clk_hw *g12a_cts_parent_hws[] = {
2701	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",	3202	&g12a_vclk_div1.hw,
2702	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",	3203	&g12a_vclk_div2.hw,
2703	"vclk2_div6", "vclk2_div12"	3204	&g12a_vclk_div4.hw,
		3205	&g12a_vclk_div6.hw,
		3206	&g12a_vclk_div12.hw,
		3207	&g12a_vclk2_div1.hw,
		3208	&g12a_vclk2_div2.hw,
		3209	&g12a_vclk2_div4.hw,
		3210	&g12a_vclk2_div6.hw,
		3211	&g12a_vclk2_div12.hw,
2704	};	3212	};
2705		3213
2706	static struct clk_regmap g12a_cts_enci_sel = {	3214	static struct clk_regmap g12a_cts_enci_sel = {
@@ -2713,8 +3221,8 @@ static struct clk_regmap g12a_cts_enci_sel = { · 6 unmodified lines
2713	.hw.init = &(struct clk_init_data){	3221	.hw.init = &(struct clk_init_data){
2714	.name = "cts_enci_sel",	3222	.name = "cts_enci_sel",
2715	.ops = &clk_regmap_mux_ops,	3223	.ops = &clk_regmap_mux_ops,
2716	.parent_names = g12a_cts_parent_names,	3224	.parent_hws = g12a_cts_parent_hws,
2717	.num_parents = ARRAY_SIZE(g12a_cts_parent_names),	3225	.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
2718	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	3226	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2719	},	3227	},
2720	};	3228	};
@@ -2729,8 +3237,8 @@ static struct clk_regmap g12a_cts_encp_sel = { · 8 unmodified lines
2729	.hw.init = &(struct clk_init_data){	3237	.hw.init = &(struct clk_init_data){
2730	.name = "cts_encp_sel",	3238	.name = "cts_encp_sel",
2731	.ops = &clk_regmap_mux_ops,	3239	.ops = &clk_regmap_mux_ops,
2732	.parent_names = g12a_cts_parent_names,	3240	.parent_hws = g12a_cts_parent_hws,
2733	.num_parents = ARRAY_SIZE(g12a_cts_parent_names),	3241	.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
2734	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	3242	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2735	},	3243	},
2736	};	3244	};
@@ -2745,18 +3253,25 @@ static struct clk_regmap g12a_cts_vdac_sel = { · 8 unmodified lines
2745	.hw.init = &(struct clk_init_data){	3253	.hw.init = &(struct clk_init_data){
2746	.name = "cts_vdac_sel",	3254	.name = "cts_vdac_sel",
2747	.ops = &clk_regmap_mux_ops,	3255	.ops = &clk_regmap_mux_ops,
2748	.parent_names = g12a_cts_parent_names,	3256	.parent_hws = g12a_cts_parent_hws,
2749	.num_parents = ARRAY_SIZE(g12a_cts_parent_names),	3257	.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
2750	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	3258	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2751	},	3259	},
2752	};	3260	};
2753		3261
2754	/* TOFIX: add support for cts_tcon */	3262	/* TOFIX: add support for cts_tcon */
2755	static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };	3263	static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2756	static const char * const g12a_cts_hdmi_tx_parent_names[] = {	3264	static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
2757	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",	3265	&g12a_vclk_div1.hw,
2758	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",	3266	&g12a_vclk_div2.hw,
2759	"vclk2_div6", "vclk2_div12"	3267	&g12a_vclk_div4.hw,
		3268	&g12a_vclk_div6.hw,
		3269	&g12a_vclk_div12.hw,
		3270	&g12a_vclk2_div1.hw,
		3271	&g12a_vclk2_div2.hw,
		3272	&g12a_vclk2_div4.hw,
		3273	&g12a_vclk2_div6.hw,
		3274	&g12a_vclk2_div12.hw,
2760	};	3275	};
2761		3276
2762	static struct clk_regmap g12a_hdmi_tx_sel = {	3277	static struct clk_regmap g12a_hdmi_tx_sel = {
@@ -2769,8 +3284,8 @@ static struct clk_regmap g12a_hdmi_tx_sel = { · 6 unmodified lines
2769	.hw.init = &(struct clk_init_data){	3284	.hw.init = &(struct clk_init_data){
2770	.name = "hdmi_tx_sel",	3285	.name = "hdmi_tx_sel",
2771	.ops = &clk_regmap_mux_ops,	3286	.ops = &clk_regmap_mux_ops,
2772	.parent_names = g12a_cts_hdmi_tx_parent_names,	3287	.parent_hws = g12a_cts_hdmi_tx_parent_hws,
2773	.num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names),	3288	.num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
2774	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	3289	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2775	},	3290	},
2776	};	3291	};
@@ -2783,7 +3298,9 @@ static struct clk_regmap g12a_cts_enci = { · 6 unmodified lines
2783	.hw.init = &(struct clk_init_data) {	3298	.hw.init = &(struct clk_init_data) {
2784	.name = "cts_enci",	3299	.name = "cts_enci",
2785	.ops = &clk_regmap_gate_ops,	3300	.ops = &clk_regmap_gate_ops,
2786	.parent_names = (const char *[]){ "cts_enci_sel" },	3301	.parent_hws = (const struct clk_hw *[]) {
		3302	&g12a_cts_enci_sel.hw
		3303	},
2787	.num_parents = 1,	3304	.num_parents = 1,
2788	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3305	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2789	},	3306	},
@@ -2797,7 +3314,9 @@ static struct clk_regmap g12a_cts_encp = { · 7 unmodified lines
2797	.hw.init = &(struct clk_init_data) {	3314	.hw.init = &(struct clk_init_data) {
2798	.name = "cts_encp",	3315	.name = "cts_encp",
2799	.ops = &clk_regmap_gate_ops,	3316	.ops = &clk_regmap_gate_ops,
2800	.parent_names = (const char *[]){ "cts_encp_sel" },	3317	.parent_hws = (const struct clk_hw *[]) {
		3318	&g12a_cts_encp_sel.hw
		3319	},
2801	.num_parents = 1,	3320	.num_parents = 1,
2802	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3321	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2803	},	3322	},
@@ -2811,7 +3330,9 @@ static struct clk_regmap g12a_cts_vdac = { · 7 unmodified lines
2811	.hw.init = &(struct clk_init_data) {	3330	.hw.init = &(struct clk_init_data) {
2812	.name = "cts_vdac",	3331	.name = "cts_vdac",
2813	.ops = &clk_regmap_gate_ops,	3332	.ops = &clk_regmap_gate_ops,
2814	.parent_names = (const char *[]){ "cts_vdac_sel" },	3333	.parent_hws = (const struct clk_hw *[]) {
		3334	&g12a_cts_vdac_sel.hw
		3335	},
2815	.num_parents = 1,	3336	.num_parents = 1,
2816	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3337	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2817	},	3338	},
@@ -2825,7 +3346,9 @@ static struct clk_regmap g12a_hdmi_tx = { · 7 unmodified lines
2825	.hw.init = &(struct clk_init_data) {	3346	.hw.init = &(struct clk_init_data) {
2826	.name = "hdmi_tx",	3347	.name = "hdmi_tx",
2827	.ops = &clk_regmap_gate_ops,	3348	.ops = &clk_regmap_gate_ops,
2828	.parent_names = (const char *[]){ "hdmi_tx_sel" },	3349	.parent_hws = (const struct clk_hw *[]) {
		3350	&g12a_hdmi_tx_sel.hw
		3351	},
2829	.num_parents = 1,	3352	.num_parents = 1,
2830	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3353	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2831	},	3354	},
@@ -2833,8 +3356,11 @@ static struct clk_regmap g12a_hdmi_tx = { · 1 unmodified line
2833		3356
2834	/* HDMI Clocks */	3357	/* HDMI Clocks */
2835		3358
2836	static const char * const g12a_hdmi_parent_names[] = {	3359	static const struct clk_parent_data g12a_hdmi_parent_data[] = {
2837	IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"	3360	{ .fw_name = "xtal", },
		3361	{ .hw = &g12a_fclk_div4.hw },
		3362	{ .hw = &g12a_fclk_div3.hw },
		3363	{ .hw = &g12a_fclk_div5.hw },
2838	};	3364	};
2839		3365
2840	static struct clk_regmap g12a_hdmi_sel = {	3366	static struct clk_regmap g12a_hdmi_sel = {
@@ -2847,8 +3373,8 @@ static struct clk_regmap g12a_hdmi_sel = { · 6 unmodified lines
2847	.hw.init = &(struct clk_init_data){	3373	.hw.init = &(struct clk_init_data){
2848	.name = "hdmi_sel",	3374	.name = "hdmi_sel",
2849	.ops = &clk_regmap_mux_ops,	3375	.ops = &clk_regmap_mux_ops,
2850	.parent_names = g12a_hdmi_parent_names,	3376	.parent_data = g12a_hdmi_parent_data,
2851	.num_parents = ARRAY_SIZE(g12a_hdmi_parent_names),	3377	.num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
2852	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	3378	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2853	},	3379	},
2854	};	3380	};
@@ -2862,7 +3388,7 @@ static struct clk_regmap g12a_hdmi_div = { · 7 unmodified lines
2862	.hw.init = &(struct clk_init_data){	3388	.hw.init = &(struct clk_init_data){
2863	.name = "hdmi_div",	3389	.name = "hdmi_div",
2864	.ops = &clk_regmap_divider_ops,	3390	.ops = &clk_regmap_divider_ops,
2865	.parent_names = (const char *[]){ "hdmi_sel" },	3391	.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
2866	.num_parents = 1,	3392	.num_parents = 1,
2867	.flags = CLK_GET_RATE_NOCACHE,	3393	.flags = CLK_GET_RATE_NOCACHE,
2868	},	3394	},
@@ -2876,7 +3402,7 @@ static struct clk_regmap g12a_hdmi = { · 7 unmodified lines
2876	.hw.init = &(struct clk_init_data) {	3402	.hw.init = &(struct clk_init_data) {
2877	.name = "hdmi",	3403	.name = "hdmi",
2878	.ops = &clk_regmap_gate_ops,	3404	.ops = &clk_regmap_gate_ops,
2879	.parent_names = (const char *[]){ "hdmi_div" },	3405	.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
2880	.num_parents = 1,	3406	.num_parents = 1,
2881	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	3407	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2882	},	3408	},
@@ -2886,10 +3412,15 @@ static struct clk_regmap g12a_hdmi = { · 3 unmodified lines
2886	* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)	3412	* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
2887	* muxed by a glitch-free switch.	3413	* muxed by a glitch-free switch.
2888	*/	3414	*/
2889		3415	static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
2890	static const char * const g12a_mali_0_1_parent_names[] = {	3416	{ .fw_name = "xtal", },
2891	IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5",	3417	{ .hw = &g12a_gp0_pll.hw },
2892	"fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"	3418	{ .hw = &g12a_hifi_pll.hw },
		3419	{ .hw = &g12a_fclk_div2p5.hw },
		3420	{ .hw = &g12a_fclk_div3.hw },
		3421	{ .hw = &g12a_fclk_div4.hw },
		3422	{ .hw = &g12a_fclk_div5.hw },
		3423	{ .hw = &g12a_fclk_div7.hw },
2893	};	3424	};
2894		3425
2895	static struct clk_regmap g12a_mali_0_sel = {	3426	static struct clk_regmap g12a_mali_0_sel = {
@@ -2901,7 +3432,7 @@ static struct clk_regmap g12a_mali_0_sel = { · 5 unmodified lines
2901	.hw.init = &(struct clk_init_data){	3432	.hw.init = &(struct clk_init_data){
2902	.name = "mali_0_sel",	3433	.name = "mali_0_sel",
2903	.ops = &clk_regmap_mux_ops,	3434	.ops = &clk_regmap_mux_ops,
2904	.parent_names = g12a_mali_0_1_parent_names,	3435	.parent_data = g12a_mali_0_1_parent_data,
2905	.num_parents = 8,	3436	.num_parents = 8,
2906	.flags = CLK_SET_RATE_NO_REPARENT,	3437	.flags = CLK_SET_RATE_NO_REPARENT,
2907	},	3438	},
@@ -2916,7 +3447,9 @@ static struct clk_regmap g12a_mali_0_div = { · 8 unmodified lines
2916	.hw.init = &(struct clk_init_data){	3447	.hw.init = &(struct clk_init_data){
2917	.name = "mali_0_div",	3448	.name = "mali_0_div",
2918	.ops = &clk_regmap_divider_ops,	3449	.ops = &clk_regmap_divider_ops,
2919	.parent_names = (const char *[]){ "mali_0_sel" },	3450	.parent_hws = (const struct clk_hw *[]) {
		3451	&g12a_mali_0_sel.hw
		3452	},
2920	.num_parents = 1,	3453	.num_parents = 1,
2921	.flags = CLK_SET_RATE_NO_REPARENT,	3454	.flags = CLK_SET_RATE_NO_REPARENT,
2922	},	3455	},
@@ -2930,7 +3463,9 @@ static struct clk_regmap g12a_mali_0 = { · 7 unmodified lines
2930	.hw.init = &(struct clk_init_data){	3463	.hw.init = &(struct clk_init_data){
2931	.name = "mali_0",	3464	.name = "mali_0",
2932	.ops = &clk_regmap_gate_ops,	3465	.ops = &clk_regmap_gate_ops,
2933	.parent_names = (const char *[]){ "mali_0_div" },	3466	.parent_hws = (const struct clk_hw *[]) {
		3467	&g12a_mali_0_div.hw
		3468	},
2934	.num_parents = 1,	3469	.num_parents = 1,
2935	.flags = CLK_SET_RATE_PARENT,	3470	.flags = CLK_SET_RATE_PARENT,
2936	},	3471	},
@@ -2945,7 +3480,7 @@ static struct clk_regmap g12a_mali_1_sel = { · 8 unmodified lines
2945	.hw.init = &(struct clk_init_data){	3480	.hw.init = &(struct clk_init_data){
2946	.name = "mali_1_sel",	3481	.name = "mali_1_sel",
2947	.ops = &clk_regmap_mux_ops,	3482	.ops = &clk_regmap_mux_ops,
2948	.parent_names = g12a_mali_0_1_parent_names,	3483	.parent_data = g12a_mali_0_1_parent_data,
2949	.num_parents = 8,	3484	.num_parents = 8,
2950	.flags = CLK_SET_RATE_NO_REPARENT,	3485	.flags = CLK_SET_RATE_NO_REPARENT,
2951	},	3486	},
@@ -2960,7 +3495,9 @@ static struct clk_regmap g12a_mali_1_div = { · 8 unmodified lines
2960	.hw.init = &(struct clk_init_data){	3495	.hw.init = &(struct clk_init_data){
2961	.name = "mali_1_div",	3496	.name = "mali_1_div",
2962	.ops = &clk_regmap_divider_ops,	3497	.ops = &clk_regmap_divider_ops,
2963	.parent_names = (const char *[]){ "mali_1_sel" },	3498	.parent_hws = (const struct clk_hw *[]) {
		3499	&g12a_mali_1_sel.hw
		3500	},
2964	.num_parents = 1,	3501	.num_parents = 1,
2965	.flags = CLK_SET_RATE_NO_REPARENT,	3502	.flags = CLK_SET_RATE_NO_REPARENT,
2966	},	3503	},
@@ -2974,14 +3511,17 @@ static struct clk_regmap g12a_mali_1 = { · 7 unmodified lines
2974	.hw.init = &(struct clk_init_data){	3511	.hw.init = &(struct clk_init_data){
2975	.name = "mali_1",	3512	.name = "mali_1",
2976	.ops = &clk_regmap_gate_ops,	3513	.ops = &clk_regmap_gate_ops,
2977	.parent_names = (const char *[]){ "mali_1_div" },	3514	.parent_hws = (const struct clk_hw *[]) {
		3515	&g12a_mali_1_div.hw
		3516	},
2978	.num_parents = 1,	3517	.num_parents = 1,
2979	.flags = CLK_SET_RATE_PARENT,	3518	.flags = CLK_SET_RATE_PARENT,
2980	},	3519	},
2981	};	3520	};
2982		3521
2983	static const char * const g12a_mali_parent_names[] = {	3522	static const struct clk_hw *g12a_mali_parent_hws[] = {
2984	"mali_0", "mali_1"	3523	&g12a_mali_0.hw,
		3524	&g12a_mali_1.hw,
2985	};	3525	};
2986		3526
2987	static struct clk_regmap g12a_mali = {	3527	static struct clk_regmap g12a_mali = {
@@ -2993,7 +3533,7 @@ static struct clk_regmap g12a_mali = { · 5 unmodified lines
2993	.hw.init = &(struct clk_init_data){	3533	.hw.init = &(struct clk_init_data){
2994	.name = "mali",	3534	.name = "mali",
2995	.ops = &clk_regmap_mux_ops,	3535	.ops = &clk_regmap_mux_ops,
2996	.parent_names = g12a_mali_parent_names,	3536	.parent_hws = g12a_mali_parent_hws,
2997	.num_parents = 2,	3537	.num_parents = 2,
2998	.flags = CLK_SET_RATE_NO_REPARENT,	3538	.flags = CLK_SET_RATE_NO_REPARENT,
2999	},	3539	},
@@ -3008,7 +3548,9 @@ static struct clk_regmap g12a_ts_div = { · 8 unmodified lines
3008	.hw.init = &(struct clk_init_data){	3548	.hw.init = &(struct clk_init_data){
3009	.name = "ts_div",	3549	.name = "ts_div",
3010	.ops = &clk_regmap_divider_ro_ops,	3550	.ops = &clk_regmap_divider_ro_ops,
3011	.parent_names = (const char *[]){ "xtal" },	3551	.parent_data = &(const struct clk_parent_data) {
		3552	.fw_name = "xtal",
		3553	},
3012	.num_parents = 1,	3554	.num_parents = 1,
3013	},	3555	},
3014	};	3556	};
@@ -3021,11 +3563,19 @@ static struct clk_regmap g12a_ts = { · 6 unmodified lines
3021	.hw.init = &(struct clk_init_data){	3563	.hw.init = &(struct clk_init_data){
3022	.name = "ts",	3564	.name = "ts",
3023	.ops = &clk_regmap_gate_ops,	3565	.ops = &clk_regmap_gate_ops,
3024	.parent_names = (const char *[]){ "ts_div" },	3566	.parent_hws = (const struct clk_hw *[]) {
		3567	&g12a_ts_div.hw
		3568	},
3025	.num_parents = 1,	3569	.num_parents = 1,
3026	},	3570	},
3027	};	3571	};
3028		3572
		3573	#define MESON_GATE(_name, _reg, _bit) \
		3574	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
		3575
		3576	#define MESON_GATE_RO(_name, _reg, _bit) \
		3577	MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
		3578
3029	/* Everything Else (EE) domain gates */	3579	/* Everything Else (EE) domain gates */
3030	static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);	3580	static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
3031	static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);	3581	static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
@@ -3792,28 +4342,210 @@ static const struct reg_sequence g12a_init_regs[] = { · 760 unmodified lines
3792	{ .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },	4342	{ .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
3793	};	4343	};
3794		4344
3795	static const struct meson_eeclkc_data g12a_clkc_data = {	4345	static int meson_g12a_dvfs_setup_common(struct platform_device *pdev,
3796	.regmap_clks = g12a_clk_regmaps,	4346	struct clk_hw **hws)
3797	.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),	4347	{
3798	.hw_onecell_data = &g12a_hw_onecell_data,	4348	const char *notifier_clk_name;
3799	.init_regs = g12a_init_regs,	4349	struct clk *notifier_clk;
3800	.init_count = ARRAY_SIZE(g12a_init_regs),	4350	struct clk_hw *xtal;
3801	};	4351	int ret;
3802		4352
3803	static const struct meson_eeclkc_data g12b_clkc_data = {	4353	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
3804	.regmap_clks = g12a_clk_regmaps,	4354
3805	.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),	4355	/* Setup clock notifier for cpu_clk_postmux0 */
3806	.hw_onecell_data = &g12b_hw_onecell_data	4356	g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
		4357	notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw);
		4358	notifier_clk = __clk_lookup(notifier_clk_name);
		4359	ret = clk_notifier_register(notifier_clk,
		4360	&g12a_cpu_clk_postmux0_nb_data.nb);
		4361	if (ret) {
		4362	dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");
		4363	return ret;
		4364	}
		4365
		4366	/* Setup clock notifier for cpu_clk_dyn mux */
		4367	notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw);
		4368	notifier_clk = __clk_lookup(notifier_clk_name);
		4369	ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
		4370	if (ret) {
		4371	dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");
		4372	return ret;
		4373	}
		4374
		4375	return 0;
		4376	}
		4377
		4378	static int meson_g12b_dvfs_setup(struct platform_device *pdev)
		4379	{
		4380	struct clk_hw **hws = g12b_hw_onecell_data.hws;
		4381	const char *notifier_clk_name;
		4382	struct clk *notifier_clk;
		4383	struct clk_hw *xtal;
		4384	int ret;
		4385
		4386	ret = meson_g12a_dvfs_setup_common(pdev, hws);
		4387	if (ret)
		4388	return ret;
		4389
		4390	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
		4391
		4392	/* Setup clock notifier for cpu_clk mux */
		4393	notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw);
		4394	notifier_clk = __clk_lookup(notifier_clk_name);
		4395	ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
		4396	if (ret) {
		4397	dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
		4398	return ret;
		4399	}
		4400
		4401	/* Setup clock notifier for sys1_pll */
		4402	notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw);
		4403	notifier_clk = __clk_lookup(notifier_clk_name);
		4404	ret = clk_notifier_register(notifier_clk,
		4405	&g12b_cpu_clk_sys1_pll_nb_data.nb);
		4406	if (ret) {
		4407	dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");
		4408	return ret;
		4409	}
		4410
		4411	/* Add notifiers for the second CPU cluster */
		4412
		4413	/* Setup clock notifier for cpub_clk_postmux0 */
		4414	g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
		4415	notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw);
		4416	notifier_clk = __clk_lookup(notifier_clk_name);
		4417	ret = clk_notifier_register(notifier_clk,
		4418	&g12b_cpub_clk_postmux0_nb_data.nb);
		4419	if (ret) {
		4420	dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");
		4421	return ret;
		4422	}
		4423
		4424	/* Setup clock notifier for cpub_clk_dyn mux */
		4425	notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw);
		4426	notifier_clk = __clk_lookup(notifier_clk_name);
		4427	ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
		4428	if (ret) {
		4429	dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");
		4430	return ret;
		4431	}
		4432
		4433	/* Setup clock notifier for cpub_clk mux */
		4434	notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw);
		4435	notifier_clk = __clk_lookup(notifier_clk_name);
		4436	ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
		4437	if (ret) {
		4438	dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");
		4439	return ret;
		4440	}
		4441
		4442	/* Setup clock notifier for sys_pll */
		4443	notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
		4444	notifier_clk = __clk_lookup(notifier_clk_name);
		4445	ret = clk_notifier_register(notifier_clk,
		4446	&g12b_cpub_clk_sys_pll_nb_data.nb);
		4447	if (ret) {
		4448	dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
		4449	return ret;
		4450	}
		4451
		4452	return 0;
		4453	}
		4454
		4455	static int meson_g12a_dvfs_setup(struct platform_device *pdev)
		4456	{
		4457	struct clk_hw **hws = g12a_hw_onecell_data.hws;
		4458	const char *notifier_clk_name;
		4459	struct clk *notifier_clk;
		4460	int ret;
		4461
		4462	ret = meson_g12a_dvfs_setup_common(pdev, hws);
		4463	if (ret)
		4464	return ret;
		4465
		4466	/* Setup clock notifier for cpu_clk mux */
		4467	notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw);
		4468	notifier_clk = __clk_lookup(notifier_clk_name);
		4469	ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
		4470	if (ret) {
		4471	dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
		4472	return ret;
		4473	}
		4474
		4475	/* Setup clock notifier for sys_pll */
		4476	notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
		4477	notifier_clk = __clk_lookup(notifier_clk_name);
		4478	ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb);
		4479	if (ret) {
		4480	dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
		4481	return ret;
		4482	}
		4483
		4484	return 0;
		4485	}
		4486
		4487	struct meson_g12a_data {
		4488	const struct meson_eeclkc_data eeclkc_data;
		4489	int (dvfs_setup)(struct platform_device pdev);
		4490	};
		4491
		4492	static int meson_g12a_probe(struct platform_device *pdev)
		4493	{
		4494	const struct meson_eeclkc_data *eeclkc_data;
		4495	const struct meson_g12a_data *g12a_data;
		4496	int ret;
		4497
		4498	eeclkc_data = of_device_get_match_data(&pdev->dev);
		4499	if (!eeclkc_data)
		4500	return -EINVAL;
		4501
		4502	ret = meson_eeclkc_probe(pdev);
		4503	if (ret)
		4504	return ret;
		4505
		4506	g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
		4507	eeclkc_data);
		4508
		4509	if (g12a_data->dvfs_setup)
		4510	return g12a_data->dvfs_setup(pdev);
		4511
		4512	return 0;
		4513	}
		4514
		4515	static const struct meson_g12a_data g12a_clkc_data = {
		4516	.eeclkc_data = {
		4517	.regmap_clks = g12a_clk_regmaps,
		4518	.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
		4519	.hw_onecell_data = &g12a_hw_onecell_data,
		4520	.init_regs = g12a_init_regs,
		4521	.init_count = ARRAY_SIZE(g12a_init_regs),
		4522	},
		4523	.dvfs_setup = meson_g12a_dvfs_setup,
		4524	};
		4525
		4526	static const struct meson_g12a_data g12b_clkc_data = {
		4527	.eeclkc_data = {
		4528	.regmap_clks = g12a_clk_regmaps,
		4529	.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
		4530	.hw_onecell_data = &g12b_hw_onecell_data,
		4531	},
		4532	.dvfs_setup = meson_g12b_dvfs_setup,
3807	};	4533	};
3808		4534
3809	static const struct of_device_id clkc_match_table[] = {	4535	static const struct of_device_id clkc_match_table[] = {
3810	{ .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data },	4536	{
3811	{ .compatible = "amlogic,g12b-clkc", .data = &g12b_clkc_data },	4537	.compatible = "amlogic,g12a-clkc",
		4538	.data = &g12a_clkc_data.eeclkc_data
		4539	},
		4540	{
		4541	.compatible = "amlogic,g12b-clkc",
		4542	.data = &g12b_clkc_data.eeclkc_data
		4543	},
3812	{}	4544	{}
3813	};	4545	};
3814		4546
3815	static struct platform_driver g12a_driver = {	4547	static struct platform_driver g12a_driver = {
3816	.probe = meson_eeclkc_probe,	4548	.probe = meson_g12a_probe,
3817	.driver = {	4549	.driver = {
3818	.name = "g12a-clkc",	4550	.name = "g12a-clkc",
3819	.of_match_table = clkc_match_table,	4551	.of_match_table = clkc_match_table,

drivers/clk/meson/g12a.h+0−1

@@ -216,7 +216,6 @@ · 215 unmodified lines
216	#define CLKID_CPUB_CLK_DYN1_DIV 221	216	#define CLKID_CPUB_CLK_DYN1_DIV 221
217	#define CLKID_CPUB_CLK_DYN1 222	217	#define CLKID_CPUB_CLK_DYN1 222
218	#define CLKID_CPUB_CLK_DYN 223	218	#define CLKID_CPUB_CLK_DYN 223
219	#define CLKID_CPUB_CLK 224
220	#define CLKID_CPUB_CLK_DIV16_EN 225	219	#define CLKID_CPUB_CLK_DIV16_EN 225
221	#define CLKID_CPUB_CLK_DIV16 226	220	#define CLKID_CPUB_CLK_DIV16 226
222	#define CLKID_CPUB_CLK_DIV2 227	221	#define CLKID_CPUB_CLK_DIV2 227

drivers/clk/meson/gxbb-aoclk.c+27−28

 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
-#define IN_PREFIX "ao-in-"
 /* AO Configuration Clock registers offsets */
 #define AO_RTI_PWR_CNTL_REG1	0x0c
 #define AO_RTI_PWR_CNTL_REG0	0x10
 	.hw.init = &(struct clk_init_data) {				\
 		.name = #_name "_ao",					\
 		.ops = &clk_regmap_gate_ops,				\
-		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+		.parent_data = &(const struct clk_parent_data) {	\
+			.fw_name = "mpeg-clk",				\
+		},							\
 		.num_parents = 1,					\
 		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 	.hw.init = &(struct clk_init_data){
 		.name = "ao_cts_oscin",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "xtal" },
+		.parent_data = &(const struct clk_parent_data) {
+			.fw_name = "xtal",
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "ao_32k_pre",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "ao_cts_oscin" },
+		.parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "ao_32k_div",
 		.ops = &meson_clk_dualdiv_ops,
-		.parent_names = (const char *[]){ "ao_32k_pre" },
+		.parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "ao_32k_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "ao_32k_div",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "ao_32k_pre" },
+			&ao_32k_div.hw,
+			&ao_32k_pre.hw
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "ao_32k",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "ao_32k_sel" },
+		.parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "ao_cts_rtc_oscin",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "ext-32k-0",
+		.parent_data = (const struct clk_parent_data []) {
-						  IN_PREFIX "ext-32k-1",
+			{ .fw_name = "ext-32k-0", },
-						  IN_PREFIX "ext-32k-2",
+			{ .fw_name = "ext-32k-1", },
-						  "ao_32k" },
+			{ .fw_name = "ext-32k-2", },
+			{ .hw = &ao_32k.hw },
+		},
 		.num_parents = 4,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "ao_clk81",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
+		.parent_data = (const struct clk_parent_data []) {
-						  "ao_cts_rtc_oscin" },
+			{ .fw_name = "mpeg-clk", },
+			{ .hw = &ao_cts_rtc_oscin.hw },
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 		 * Until CCF gets fixed, adding this fake parent that won't
 		 * ever be registered should work around the problem
 		 */
-		.parent_names = (const char *[]){ "fixme",
+		.parent_data = (const struct clk_parent_data []) {
-						  "ao_cts_rtc_oscin" },
+			{ .name = "fixme", .index = -1, },
+			{ .hw = &ao_cts_rtc_oscin.hw },
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.num = NR_CLKS,
 };
-static const struct meson_aoclk_input gxbb_aoclk_inputs[] = {
-	{ .name = "xtal",	.required = true,  },
-	{ .name = "mpeg-clk",	.required = true,  },
-	{. name = "ext-32k-0",	.required = false, },
-	{. name = "ext-32k-1",	.required = false, },
-	{. name = "ext-32k-2",	.required = false, },
-};
 static const struct meson_aoclk_data gxbb_aoclkc_data = {
 	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
 	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
 	.num_clks	= ARRAY_SIZE(gxbb_aoclk),
 	.clks		= gxbb_aoclk,
 	.hw_data	= &gxbb_aoclk_onecell_data,
-	.inputs		= gxbb_aoclk_inputs,
-	.num_inputs	= ARRAY_SIZE(gxbb_aoclk_inputs),
-	.input_prefix	= IN_PREFIX,
 };
 static const struct of_device_id gxbb_aoclkc_match_table[] = {

drivers/clk/meson/gxbb.c+454−203

@@ -10,15 +10,12 @@ · 9 unmodified lines
10	#include <linux/platform_device.h>	10	#include <linux/platform_device.h>
11		11
12	#include "gxbb.h"	12	#include "gxbb.h"
13	#include "clk-input.h"
14	#include "clk-regmap.h"	13	#include "clk-regmap.h"
15	#include "clk-pll.h"	14	#include "clk-pll.h"
16	#include "clk-mpll.h"	15	#include "clk-mpll.h"
17	#include "meson-eeclk.h"	16	#include "meson-eeclk.h"
18	#include "vid-pll-div.h"	17	#include "vid-pll-div.h"
19		18
20	#define IN_PREFIX "ee-in-"
21
22	static DEFINE_SPINLOCK(meson_clk_lock);	19	static DEFINE_SPINLOCK(meson_clk_lock);
23		20
24	static const struct pll_params_table gxbb_gp0_pll_params_table[] = {	21	static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
@@ -121,7 +118,9 @@ static struct clk_regmap gxbb_fixed_pll_dco = { · 96 unmodified lines
121	.hw.init = &(struct clk_init_data){	118	.hw.init = &(struct clk_init_data){
122	.name = "fixed_pll_dco",	119	.name = "fixed_pll_dco",
123	.ops = &meson_clk_pll_ro_ops,	120	.ops = &meson_clk_pll_ro_ops,
124	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	121	.parent_data = &(const struct clk_parent_data) {
		122	.fw_name = "xtal",
		123	},
125	.num_parents = 1,	124	.num_parents = 1,
126	},	125	},
127	};	126	};
@@ -136,7 +135,9 @@ static struct clk_regmap gxbb_fixed_pll = { · 8 unmodified lines
136	.hw.init = &(struct clk_init_data){	135	.hw.init = &(struct clk_init_data){
137	.name = "fixed_pll",	136	.name = "fixed_pll",
138	.ops = &clk_regmap_divider_ro_ops,	137	.ops = &clk_regmap_divider_ro_ops,
139	.parent_names = (const char *[]){ "fixed_pll_dco" },	138	.parent_hws = (const struct clk_hw *[]) {
		139	&gxbb_fixed_pll_dco.hw
		140	},
140	.num_parents = 1,	141	.num_parents = 1,
141	/*	142	/*
142	* This clock won't ever change at runtime so	143	* This clock won't ever change at runtime so
@@ -151,7 +152,9 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { · 8 unmodified lines
151	.hw.init = &(struct clk_init_data){	152	.hw.init = &(struct clk_init_data){
152	.name = "hdmi_pll_pre_mult",	153	.name = "hdmi_pll_pre_mult",
153	.ops = &clk_fixed_factor_ops,	154	.ops = &clk_fixed_factor_ops,
154	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	155	.parent_data = &(const struct clk_parent_data) {
		156	.fw_name = "xtal",
		157	},
155	.num_parents = 1,	158	.num_parents = 1,
156	},	159	},
157	};	160	};
@@ -192,7 +195,9 @@ static struct clk_regmap gxbb_hdmi_pll_dco = { · 34 unmodified lines
192	.hw.init = &(struct clk_init_data){	195	.hw.init = &(struct clk_init_data){
193	.name = "hdmi_pll_dco",	196	.name = "hdmi_pll_dco",
194	.ops = &meson_clk_pll_ro_ops,	197	.ops = &meson_clk_pll_ro_ops,
195	.parent_names = (const char *[]){ "hdmi_pll_pre_mult" },	198	.parent_hws = (const struct clk_hw *[]) {
		199	&gxbb_hdmi_pll_pre_mult.hw
		200	},
196	.num_parents = 1,	201	.num_parents = 1,
197	/*	202	/*
198	* Display directly handle hdmi pll registers ATM, we need	203	* Display directly handle hdmi pll registers ATM, we need
@@ -244,7 +249,9 @@ static struct clk_regmap gxl_hdmi_pll_dco = { · 45 unmodified lines
244	.hw.init = &(struct clk_init_data){	249	.hw.init = &(struct clk_init_data){
245	.name = "hdmi_pll_dco",	250	.name = "hdmi_pll_dco",
246	.ops = &meson_clk_pll_ro_ops,	251	.ops = &meson_clk_pll_ro_ops,
247	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	252	.parent_data = &(const struct clk_parent_data) {
		253	.fw_name = "xtal",
		254	},
248	.num_parents = 1,	255	.num_parents = 1,
249	/*	256	/*
250	* Display directly handle hdmi pll registers ATM, we need	257	* Display directly handle hdmi pll registers ATM, we need
@@ -264,7 +271,9 @@ static struct clk_regmap gxbb_hdmi_pll_od = { · 13 unmodified lines
264	.hw.init = &(struct clk_init_data){	271	.hw.init = &(struct clk_init_data){
265	.name = "hdmi_pll_od",	272	.name = "hdmi_pll_od",
266	.ops = &clk_regmap_divider_ro_ops,	273	.ops = &clk_regmap_divider_ro_ops,
267	.parent_names = (const char *[]){ "hdmi_pll_dco" },	274	.parent_hws = (const struct clk_hw *[]) {
		275	&gxbb_hdmi_pll_dco.hw
		276	},
268	.num_parents = 1,	277	.num_parents = 1,
269	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	278	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
270	},	279	},
@@ -280,7 +289,9 @@ static struct clk_regmap gxbb_hdmi_pll_od2 = { · 9 unmodified lines
280	.hw.init = &(struct clk_init_data){	289	.hw.init = &(struct clk_init_data){
281	.name = "hdmi_pll_od2",	290	.name = "hdmi_pll_od2",
282	.ops = &clk_regmap_divider_ro_ops,	291	.ops = &clk_regmap_divider_ro_ops,
283	.parent_names = (const char *[]){ "hdmi_pll_od" },	292	.parent_hws = (const struct clk_hw *[]) {
		293	&gxbb_hdmi_pll_od.hw
		294	},
284	.num_parents = 1,	295	.num_parents = 1,
285	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	296	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
286	},	297	},
@@ -296,7 +307,9 @@ static struct clk_regmap gxbb_hdmi_pll = { · 9 unmodified lines
296	.hw.init = &(struct clk_init_data){	307	.hw.init = &(struct clk_init_data){
297	.name = "hdmi_pll",	308	.name = "hdmi_pll",
298	.ops = &clk_regmap_divider_ro_ops,	309	.ops = &clk_regmap_divider_ro_ops,
299	.parent_names = (const char *[]){ "hdmi_pll_od2" },	310	.parent_hws = (const struct clk_hw *[]) {
		311	&gxbb_hdmi_pll_od2.hw
		312	},
300	.num_parents = 1,	313	.num_parents = 1,
301	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	314	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
302	},	315	},
@@ -312,7 +325,9 @@ static struct clk_regmap gxl_hdmi_pll_od = { · 9 unmodified lines
312	.hw.init = &(struct clk_init_data){	325	.hw.init = &(struct clk_init_data){
313	.name = "hdmi_pll_od",	326	.name = "hdmi_pll_od",
314	.ops = &clk_regmap_divider_ro_ops,	327	.ops = &clk_regmap_divider_ro_ops,
315	.parent_names = (const char *[]){ "hdmi_pll_dco" },	328	.parent_hws = (const struct clk_hw *[]) {
		329	&gxl_hdmi_pll_dco.hw
		330	},
316	.num_parents = 1,	331	.num_parents = 1,
317	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	332	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
318	},	333	},
@@ -328,7 +343,9 @@ static struct clk_regmap gxl_hdmi_pll_od2 = { · 9 unmodified lines
328	.hw.init = &(struct clk_init_data){	343	.hw.init = &(struct clk_init_data){
329	.name = "hdmi_pll_od2",	344	.name = "hdmi_pll_od2",
330	.ops = &clk_regmap_divider_ro_ops,	345	.ops = &clk_regmap_divider_ro_ops,
331	.parent_names = (const char *[]){ "hdmi_pll_od" },	346	.parent_hws = (const struct clk_hw *[]) {
		347	&gxl_hdmi_pll_od.hw
		348	},
332	.num_parents = 1,	349	.num_parents = 1,
333	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	350	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
334	},	351	},
@@ -344,7 +361,9 @@ static struct clk_regmap gxl_hdmi_pll = { · 9 unmodified lines
344	.hw.init = &(struct clk_init_data){	361	.hw.init = &(struct clk_init_data){
345	.name = "hdmi_pll",	362	.name = "hdmi_pll",
346	.ops = &clk_regmap_divider_ro_ops,	363	.ops = &clk_regmap_divider_ro_ops,
347	.parent_names = (const char *[]){ "hdmi_pll_od2" },	364	.parent_hws = (const struct clk_hw *[]) {
		365	&gxl_hdmi_pll_od2.hw
		366	},
348	.num_parents = 1,	367	.num_parents = 1,
349	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,	368	.flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
350	},	369	},
@@ -381,7 +400,9 @@ static struct clk_regmap gxbb_sys_pll_dco = { · 30 unmodified lines
381	.hw.init = &(struct clk_init_data){	400	.hw.init = &(struct clk_init_data){
382	.name = "sys_pll_dco",	401	.name = "sys_pll_dco",
383	.ops = &meson_clk_pll_ro_ops,	402	.ops = &meson_clk_pll_ro_ops,
384	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	403	.parent_data = &(const struct clk_parent_data) {
		404	.fw_name = "xtal",
		405	},
385	.num_parents = 1,	406	.num_parents = 1,
386	},	407	},
387	};	408	};
@@ -396,7 +417,9 @@ static struct clk_regmap gxbb_sys_pll = { · 8 unmodified lines
396	.hw.init = &(struct clk_init_data){	417	.hw.init = &(struct clk_init_data){
397	.name = "sys_pll",	418	.name = "sys_pll",
398	.ops = &clk_regmap_divider_ro_ops,	419	.ops = &clk_regmap_divider_ro_ops,
399	.parent_names = (const char *[]){ "sys_pll_dco" },	420	.parent_hws = (const struct clk_hw *[]) {
		421	&gxbb_sys_pll_dco.hw
		422	},
400	.num_parents = 1,	423	.num_parents = 1,
401	.flags = CLK_SET_RATE_PARENT,	424	.flags = CLK_SET_RATE_PARENT,
402	},	425	},
@@ -442,7 +465,9 @@ static struct clk_regmap gxbb_gp0_pll_dco = { · 39 unmodified lines
442	.hw.init = &(struct clk_init_data){	465	.hw.init = &(struct clk_init_data){
443	.name = "gp0_pll_dco",	466	.name = "gp0_pll_dco",
444	.ops = &meson_clk_pll_ops,	467	.ops = &meson_clk_pll_ops,
445	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	468	.parent_data = &(const struct clk_parent_data) {
		469	.fw_name = "xtal",
		470	},
446	.num_parents = 1,	471	.num_parents = 1,
447	},	472	},
448	};	473	};
@@ -494,7 +519,9 @@ static struct clk_regmap gxl_gp0_pll_dco = { · 45 unmodified lines
494	.hw.init = &(struct clk_init_data){	519	.hw.init = &(struct clk_init_data){
495	.name = "gp0_pll_dco",	520	.name = "gp0_pll_dco",
496	.ops = &meson_clk_pll_ops,	521	.ops = &meson_clk_pll_ops,
497	.parent_names = (const char *[]){ IN_PREFIX "xtal" },	522	.parent_data = &(const struct clk_parent_data) {
		523	.fw_name = "xtal",
		524	},
498	.num_parents = 1,	525	.num_parents = 1,
499	},	526	},
500	};	527	};
@@ -509,7 +536,17 @@ static struct clk_regmap gxbb_gp0_pll = { · 8 unmodified lines
509	.hw.init = &(struct clk_init_data){	536	.hw.init = &(struct clk_init_data){
510	.name = "gp0_pll",	537	.name = "gp0_pll",
511	.ops = &clk_regmap_divider_ops,	538	.ops = &clk_regmap_divider_ops,
512	.parent_names = (const char *[]){ "gp0_pll_dco" },	539	.parent_data = &(const struct clk_parent_data) {
		540	/*
		541	* Note:
		542	* GXL and GXBB have different gp0_pll_dco (with
		543	* different struct clk_hw). We fallback to the global
		544	* naming string mechanism so gp0_pll picks up the
		545	* appropriate one.
		546	*/
		547	.name = "gp0_pll_dco",
		548	.index = -1,
		549	},
513	.num_parents = 1,	550	.num_parents = 1,
514	.flags = CLK_SET_RATE_PARENT,	551	.flags = CLK_SET_RATE_PARENT,
515	},	552	},
@@ -521,7 +558,9 @@ static struct clk_fixed_factor gxbb_fclk_div2_div = { · 5 unmodified lines
521	.hw.init = &(struct clk_init_data){	558	.hw.init = &(struct clk_init_data){
522	.name = "fclk_div2_div",	559	.name = "fclk_div2_div",
523	.ops = &clk_fixed_factor_ops,	560	.ops = &clk_fixed_factor_ops,
524	.parent_names = (const char *[]){ "fixed_pll" },	561	.parent_hws = (const struct clk_hw *[]) {
		562	&gxbb_fixed_pll.hw
		563	},
525	.num_parents = 1,	564	.num_parents = 1,
526	},	565	},
527	};	566	};
@@ -534,7 +573,9 @@ static struct clk_regmap gxbb_fclk_div2 = { · 6 unmodified lines
534	.hw.init = &(struct clk_init_data){	573	.hw.init = &(struct clk_init_data){
535	.name = "fclk_div2",	574	.name = "fclk_div2",
536	.ops = &clk_regmap_gate_ops,	575	.ops = &clk_regmap_gate_ops,
537	.parent_names = (const char *[]){ "fclk_div2_div" },	576	.parent_hws = (const struct clk_hw *[]) {
		577	&gxbb_fclk_div2_div.hw
		578	},
538	.num_parents = 1,	579	.num_parents = 1,
539	.flags = CLK_IS_CRITICAL,	580	.flags = CLK_IS_CRITICAL,
540	},	581	},
@@ -546,7 +587,7 @@ static struct clk_fixed_factor gxbb_fclk_div3_div = { · 5 unmodified lines
546	.hw.init = &(struct clk_init_data){	587	.hw.init = &(struct clk_init_data){
547	.name = "fclk_div3_div",	588	.name = "fclk_div3_div",
548	.ops = &clk_fixed_factor_ops,	589	.ops = &clk_fixed_factor_ops,
549	.parent_names = (const char *[]){ "fixed_pll" },	590	.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
550	.num_parents = 1,	591	.num_parents = 1,
551	},	592	},
552	};	593	};
@@ -559,7 +600,9 @@ static struct clk_regmap gxbb_fclk_div3 = { · 6 unmodified lines
559	.hw.init = &(struct clk_init_data){	600	.hw.init = &(struct clk_init_data){
560	.name = "fclk_div3",	601	.name = "fclk_div3",
561	.ops = &clk_regmap_gate_ops,	602	.ops = &clk_regmap_gate_ops,
562	.parent_names = (const char *[]){ "fclk_div3_div" },	603	.parent_hws = (const struct clk_hw *[]) {
		604	&gxbb_fclk_div3_div.hw
		605	},
563	.num_parents = 1,	606	.num_parents = 1,
564	/*	607	/*
565	* FIXME:	608	* FIXME:
@@ -582,7 +625,7 @@ static struct clk_fixed_factor gxbb_fclk_div4_div = { · 16 unmodified lines
582	.hw.init = &(struct clk_init_data){	625	.hw.init = &(struct clk_init_data){
583	.name = "fclk_div4_div",	626	.name = "fclk_div4_div",
584	.ops = &clk_fixed_factor_ops,	627	.ops = &clk_fixed_factor_ops,
585	.parent_names = (const char *[]){ "fixed_pll" },	628	.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
586	.num_parents = 1,	629	.num_parents = 1,
587	},	630	},
588	};	631	};
@@ -595,7 +638,9 @@ static struct clk_regmap gxbb_fclk_div4 = { · 6 unmodified lines
595	.hw.init = &(struct clk_init_data){	638	.hw.init = &(struct clk_init_data){
596	.name = "fclk_div4",	639	.name = "fclk_div4",
597	.ops = &clk_regmap_gate_ops,	640	.ops = &clk_regmap_gate_ops,
598	.parent_names = (const char *[]){ "fclk_div4_div" },	641	.parent_hws = (const struct clk_hw *[]) {
		642	&gxbb_fclk_div4_div.hw
		643	},
599	.num_parents = 1,	644	.num_parents = 1,
600	},	645	},
601	};	646	};
@@ -606,7 +651,7 @@ static struct clk_fixed_factor gxbb_fclk_div5_div = { · 4 unmodified lines
606	.hw.init = &(struct clk_init_data){	651	.hw.init = &(struct clk_init_data){
607	.name = "fclk_div5_div",	652	.name = "fclk_div5_div",
608	.ops = &clk_fixed_factor_ops,	653	.ops = &clk_fixed_factor_ops,
609	.parent_names = (const char *[]){ "fixed_pll" },	654	.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
610	.num_parents = 1,	655	.num_parents = 1,
611	},	656	},
612	};	657	};
@@ -619,7 +664,9 @@ static struct clk_regmap gxbb_fclk_div5 = { · 6 unmodified lines
619	.hw.init = &(struct clk_init_data){	664	.hw.init = &(struct clk_init_data){
620	.name = "fclk_div5",	665	.name = "fclk_div5",
621	.ops = &clk_regmap_gate_ops,	666	.ops = &clk_regmap_gate_ops,
622	.parent_names = (const char *[]){ "fclk_div5_div" },	667	.parent_hws = (const struct clk_hw *[]) {
		668	&gxbb_fclk_div5_div.hw
		669	},
623	.num_parents = 1,	670	.num_parents = 1,
624	},	671	},
625	};	672	};
@@ -630,7 +677,7 @@ static struct clk_fixed_factor gxbb_fclk_div7_div = { · 4 unmodified lines
630	.hw.init = &(struct clk_init_data){	677	.hw.init = &(struct clk_init_data){
631	.name = "fclk_div7_div",	678	.name = "fclk_div7_div",
632	.ops = &clk_fixed_factor_ops,	679	.ops = &clk_fixed_factor_ops,
633	.parent_names = (const char *[]){ "fixed_pll" },	680	.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
634	.num_parents = 1,	681	.num_parents = 1,
635	},	682	},
636	};	683	};
@@ -643,7 +690,9 @@ static struct clk_regmap gxbb_fclk_div7 = { · 6 unmodified lines
643	.hw.init = &(struct clk_init_data){	690	.hw.init = &(struct clk_init_data){
644	.name = "fclk_div7",	691	.name = "fclk_div7",
645	.ops = &clk_regmap_gate_ops,	692	.ops = &clk_regmap_gate_ops,
646	.parent_names = (const char *[]){ "fclk_div7_div" },	693	.parent_hws = (const struct clk_hw *[]) {
		694	&gxbb_fclk_div7_div.hw
		695	},
647	.num_parents = 1,	696	.num_parents = 1,
648	},	697	},
649	};	698	};
@@ -657,7 +706,7 @@ static struct clk_regmap gxbb_mpll_prediv = { · 7 unmodified lines
657	.hw.init = &(struct clk_init_data){	706	.hw.init = &(struct clk_init_data){
658	.name = "mpll_prediv",	707	.name = "mpll_prediv",
659	.ops = &clk_regmap_divider_ro_ops,	708	.ops = &clk_regmap_divider_ro_ops,
660	.parent_names = (const char *[]){ "fixed_pll" },	709	.parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
661	.num_parents = 1,	710	.num_parents = 1,
662	},	711	},
663	};	712	};
@@ -684,7 +733,9 @@ static struct clk_regmap gxbb_mpll0_div = { · 20 unmodified lines
684	.hw.init = &(struct clk_init_data){	733	.hw.init = &(struct clk_init_data){
685	.name = "mpll0_div",	734	.name = "mpll0_div",
686	.ops = &meson_clk_mpll_ops,	735	.ops = &meson_clk_mpll_ops,
687	.parent_names = (const char *[]){ "mpll_prediv" },	736	.parent_hws = (const struct clk_hw *[]) {
		737	&gxbb_mpll_prediv.hw
		738	},
688	.num_parents = 1,	739	.num_parents = 1,
689	},	740	},
690	};	741	};
@@ -697,7 +748,7 @@ static struct clk_regmap gxbb_mpll0 = { · 6 unmodified lines
697	.hw.init = &(struct clk_init_data){	748	.hw.init = &(struct clk_init_data){
698	.name = "mpll0",	749	.name = "mpll0",
699	.ops = &clk_regmap_gate_ops,	750	.ops = &clk_regmap_gate_ops,
700	.parent_names = (const char *[]){ "mpll0_div" },	751	.parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
701	.num_parents = 1,	752	.num_parents = 1,
702	.flags = CLK_SET_RATE_PARENT,	753	.flags = CLK_SET_RATE_PARENT,
703	},	754	},
@@ -725,7 +776,9 @@ static struct clk_regmap gxbb_mpll1_div = { · 21 unmodified lines
725	.hw.init = &(struct clk_init_data){	776	.hw.init = &(struct clk_init_data){
726	.name = "mpll1_div",	777	.name = "mpll1_div",
727	.ops = &meson_clk_mpll_ops,	778	.ops = &meson_clk_mpll_ops,
728	.parent_names = (const char *[]){ "mpll_prediv" },	779	.parent_hws = (const struct clk_hw *[]) {
		780	&gxbb_mpll_prediv.hw
		781	},
729	.num_parents = 1,	782	.num_parents = 1,
730	},	783	},
731	};	784	};
@@ -738,7 +791,7 @@ static struct clk_regmap gxbb_mpll1 = { · 6 unmodified lines
738	.hw.init = &(struct clk_init_data){	791	.hw.init = &(struct clk_init_data){
739	.name = "mpll1",	792	.name = "mpll1",
740	.ops = &clk_regmap_gate_ops,	793	.ops = &clk_regmap_gate_ops,
741	.parent_names = (const char *[]){ "mpll1_div" },	794	.parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
742	.num_parents = 1,	795	.num_parents = 1,
743	.flags = CLK_SET_RATE_PARENT,	796	.flags = CLK_SET_RATE_PARENT,
744	},	797	},
@@ -766,7 +819,9 @@ static struct clk_regmap gxbb_mpll2_div = { · 21 unmodified lines
766	.hw.init = &(struct clk_init_data){	819	.hw.init = &(struct clk_init_data){
767	.name = "mpll2_div",	820	.name = "mpll2_div",
768	.ops = &meson_clk_mpll_ops,	821	.ops = &meson_clk_mpll_ops,
769	.parent_names = (const char *[]){ "mpll_prediv" },	822	.parent_hws = (const struct clk_hw *[]) {
		823	&gxbb_mpll_prediv.hw
		824	},
770	.num_parents = 1,	825	.num_parents = 1,
771	},	826	},
772	};	827	};
@@ -779,16 +834,21 @@ static struct clk_regmap gxbb_mpll2 = { · 6 unmodified lines
779	.hw.init = &(struct clk_init_data){	834	.hw.init = &(struct clk_init_data){
780	.name = "mpll2",	835	.name = "mpll2",
781	.ops = &clk_regmap_gate_ops,	836	.ops = &clk_regmap_gate_ops,
782	.parent_names = (const char *[]){ "mpll2_div" },	837	.parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
783	.num_parents = 1,	838	.num_parents = 1,
784	.flags = CLK_SET_RATE_PARENT,	839	.flags = CLK_SET_RATE_PARENT,
785	},	840	},
786	};	841	};
787		842
788	static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };	843	static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
789	static const char * const clk81_parent_names[] = {	844	static const struct clk_parent_data clk81_parent_data[] = {
790	IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",	845	{ .fw_name = "xtal", },
791	"fclk_div3", "fclk_div5"	846	{ .hw = &gxbb_fclk_div7.hw },
		847	{ .hw = &gxbb_mpll1.hw },
		848	{ .hw = &gxbb_mpll2.hw },
		849	{ .hw = &gxbb_fclk_div4.hw },
		850	{ .hw = &gxbb_fclk_div3.hw },
		851	{ .hw = &gxbb_fclk_div5.hw },
792	};	852	};
793		853
794	static struct clk_regmap gxbb_mpeg_clk_sel = {	854	static struct clk_regmap gxbb_mpeg_clk_sel = {
@@ -806,8 +866,8 @@ static struct clk_regmap gxbb_mpeg_clk_sel = { · 11 unmodified lines
806	* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,	866	* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
807	* fclk_div4, fclk_div3, fclk_div5	867	* fclk_div4, fclk_div3, fclk_div5
808	*/	868	*/
809	.parent_names = clk81_parent_names,	869	.parent_data = clk81_parent_data,
810	.num_parents = ARRAY_SIZE(clk81_parent_names),	870	.num_parents = ARRAY_SIZE(clk81_parent_data),
811	},	871	},
812	};	872	};
813		873
@@ -820,7 +880,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = { · 6 unmodified lines
820	.hw.init = &(struct clk_init_data){	880	.hw.init = &(struct clk_init_data){
821	.name = "mpeg_clk_div",	881	.name = "mpeg_clk_div",
822	.ops = &clk_regmap_divider_ro_ops,	882	.ops = &clk_regmap_divider_ro_ops,
823	.parent_names = (const char *[]){ "mpeg_clk_sel" },	883	.parent_hws = (const struct clk_hw *[]) {
		884	&gxbb_mpeg_clk_sel.hw
		885	},
824	.num_parents = 1,	886	.num_parents = 1,
825	},	887	},
826	};	888	};
@@ -834,7 +896,9 @@ static struct clk_regmap gxbb_clk81 = { · 7 unmodified lines
834	.hw.init = &(struct clk_init_data){	896	.hw.init = &(struct clk_init_data){
835	.name = "clk81",	897	.name = "clk81",
836	.ops = &clk_regmap_gate_ops,	898	.ops = &clk_regmap_gate_ops,
837	.parent_names = (const char *[]){ "mpeg_clk_div" },	899	.parent_hws = (const struct clk_hw *[]) {
		900	&gxbb_mpeg_clk_div.hw
		901	},
838	.num_parents = 1,	902	.num_parents = 1,
839	.flags = CLK_IS_CRITICAL,	903	.flags = CLK_IS_CRITICAL,
840	},	904	},
@@ -850,7 +914,10 @@ static struct clk_regmap gxbb_sar_adc_clk_sel = { · 9 unmodified lines
850	.name = "sar_adc_clk_sel",	914	.name = "sar_adc_clk_sel",
851	.ops = &clk_regmap_mux_ops,	915	.ops = &clk_regmap_mux_ops,
852	/* NOTE: The datasheet doesn't list the parents for bit 10 */	916	/* NOTE: The datasheet doesn't list the parents for bit 10 */
853	.parent_names = (const char *[]){ IN_PREFIX "xtal", "clk81", },	917	.parent_data = (const struct clk_parent_data []) {
		918	{ .fw_name = "xtal", },
		919	{ .hw = &gxbb_clk81.hw },
		920	},
854	.num_parents = 2,	921	.num_parents = 2,
855	},	922	},
856	};	923	};
@@ -864,7 +931,9 @@ static struct clk_regmap gxbb_sar_adc_clk_div = { · 7 unmodified lines
864	.hw.init = &(struct clk_init_data){	931	.hw.init = &(struct clk_init_data){
865	.name = "sar_adc_clk_div",	932	.name = "sar_adc_clk_div",
866	.ops = &clk_regmap_divider_ops,	933	.ops = &clk_regmap_divider_ops,
867	.parent_names = (const char *[]){ "sar_adc_clk_sel" },	934	.parent_hws = (const struct clk_hw *[]) {
		935	&gxbb_sar_adc_clk_sel.hw
		936	},
868	.num_parents = 1,	937	.num_parents = 1,
869	},	938	},
870	};	939	};
@@ -877,7 +946,9 @@ static struct clk_regmap gxbb_sar_adc_clk = { · 6 unmodified lines
877	.hw.init = &(struct clk_init_data){	946	.hw.init = &(struct clk_init_data){
878	.name = "sar_adc_clk",	947	.name = "sar_adc_clk",
879	.ops = &clk_regmap_gate_ops,	948	.ops = &clk_regmap_gate_ops,
880	.parent_names = (const char *[]){ "sar_adc_clk_div" },	949	.parent_hws = (const struct clk_hw *[]) {
		950	&gxbb_sar_adc_clk_div.hw
		951	},
881	.num_parents = 1,	952	.num_parents = 1,
882	.flags = CLK_SET_RATE_PARENT,	953	.flags = CLK_SET_RATE_PARENT,
883	},	954	},
@@ -888,9 +959,15 @@ static struct clk_regmap gxbb_sar_adc_clk = { · 4 unmodified lines
888	* muxed by a glitch-free switch.	959	* muxed by a glitch-free switch.
889	*/	960	*/
890		961
891	static const char * const gxbb_mali_0_1_parent_names[] = {	962	static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
892	IN_PREFIX "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",	963	{ .fw_name = "xtal", },
893	"fclk_div4", "fclk_div3", "fclk_div5"	964	{ .hw = &gxbb_gp0_pll.hw },
		965	{ .hw = &gxbb_mpll2.hw },
		966	{ .hw = &gxbb_mpll1.hw },
		967	{ .hw = &gxbb_fclk_div7.hw },
		968	{ .hw = &gxbb_fclk_div4.hw },
		969	{ .hw = &gxbb_fclk_div3.hw },
		970	{ .hw = &gxbb_fclk_div5.hw },
894	};	971	};
895		972
896	static struct clk_regmap gxbb_mali_0_sel = {	973	static struct clk_regmap gxbb_mali_0_sel = {
@@ -907,7 +984,7 @@ static struct clk_regmap gxbb_mali_0_sel = { · 10 unmodified lines
907	* xtal, gp0_pll, mpll2, mpll1, fclk_div7,	984	* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
908	* fclk_div4, fclk_div3, fclk_div5	985	* fclk_div4, fclk_div3, fclk_div5
909	*/	986	*/
910	.parent_names = gxbb_mali_0_1_parent_names,	987	.parent_data = gxbb_mali_0_1_parent_data,
911	.num_parents = 8,	988	.num_parents = 8,
912	.flags = CLK_SET_RATE_NO_REPARENT,	989	.flags = CLK_SET_RATE_NO_REPARENT,
913	},	990	},
@@ -922,7 +999,9 @@ static struct clk_regmap gxbb_mali_0_div = { · 8 unmodified lines
922	.hw.init = &(struct clk_init_data){	999	.hw.init = &(struct clk_init_data){
923	.name = "mali_0_div",	1000	.name = "mali_0_div",
924	.ops = &clk_regmap_divider_ops,	1001	.ops = &clk_regmap_divider_ops,
925	.parent_names = (const char *[]){ "mali_0_sel" },	1002	.parent_hws = (const struct clk_hw *[]) {
		1003	&gxbb_mali_0_sel.hw
		1004	},
926	.num_parents = 1,	1005	.num_parents = 1,
927	.flags = CLK_SET_RATE_NO_REPARENT,	1006	.flags = CLK_SET_RATE_NO_REPARENT,
928	},	1007	},
@@ -936,7 +1015,9 @@ static struct clk_regmap gxbb_mali_0 = { · 7 unmodified lines
936	.hw.init = &(struct clk_init_data){	1015	.hw.init = &(struct clk_init_data){
937	.name = "mali_0",	1016	.name = "mali_0",
938	.ops = &clk_regmap_gate_ops,	1017	.ops = &clk_regmap_gate_ops,
939	.parent_names = (const char *[]){ "mali_0_div" },	1018	.parent_hws = (const struct clk_hw *[]) {
		1019	&gxbb_mali_0_div.hw
		1020	},
940	.num_parents = 1,	1021	.num_parents = 1,
941	.flags = CLK_SET_RATE_PARENT,	1022	.flags = CLK_SET_RATE_PARENT,
942	},	1023	},
@@ -956,7 +1037,7 @@ static struct clk_regmap gxbb_mali_1_sel = { · 13 unmodified lines
956	* xtal, gp0_pll, mpll2, mpll1, fclk_div7,	1037	* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
957	* fclk_div4, fclk_div3, fclk_div5	1038	* fclk_div4, fclk_div3, fclk_div5
958	*/	1039	*/
959	.parent_names = gxbb_mali_0_1_parent_names,	1040	.parent_data = gxbb_mali_0_1_parent_data,
960	.num_parents = 8,	1041	.num_parents = 8,
961	.flags = CLK_SET_RATE_NO_REPARENT,	1042	.flags = CLK_SET_RATE_NO_REPARENT,
962	},	1043	},
@@ -971,7 +1052,9 @@ static struct clk_regmap gxbb_mali_1_div = { · 8 unmodified lines
971	.hw.init = &(struct clk_init_data){	1052	.hw.init = &(struct clk_init_data){
972	.name = "mali_1_div",	1053	.name = "mali_1_div",
973	.ops = &clk_regmap_divider_ops,	1054	.ops = &clk_regmap_divider_ops,
974	.parent_names = (const char *[]){ "mali_1_sel" },	1055	.parent_hws = (const struct clk_hw *[]) {
		1056	&gxbb_mali_1_sel.hw
		1057	},
975	.num_parents = 1,	1058	.num_parents = 1,
976	.flags = CLK_SET_RATE_NO_REPARENT,	1059	.flags = CLK_SET_RATE_NO_REPARENT,
977	},	1060	},
@@ -985,14 +1068,17 @@ static struct clk_regmap gxbb_mali_1 = { · 7 unmodified lines
985	.hw.init = &(struct clk_init_data){	1068	.hw.init = &(struct clk_init_data){
986	.name = "mali_1",	1069	.name = "mali_1",
987	.ops = &clk_regmap_gate_ops,	1070	.ops = &clk_regmap_gate_ops,
988	.parent_names = (const char *[]){ "mali_1_div" },	1071	.parent_hws = (const struct clk_hw *[]) {
		1072	&gxbb_mali_1_div.hw
		1073	},
989	.num_parents = 1,	1074	.num_parents = 1,
990	.flags = CLK_SET_RATE_PARENT,	1075	.flags = CLK_SET_RATE_PARENT,
991	},	1076	},
992	};	1077	};
993		1078
994	static const char * const gxbb_mali_parent_names[] = {	1079	static const struct clk_hw *gxbb_mali_parent_hws[] = {
995	"mali_0", "mali_1"	1080	&gxbb_mali_0.hw,
		1081	&gxbb_mali_1.hw,
996	};	1082	};
997		1083
998	static struct clk_regmap gxbb_mali = {	1084	static struct clk_regmap gxbb_mali = {
@@ -1004,7 +1090,7 @@ static struct clk_regmap gxbb_mali = { · 5 unmodified lines
1004	.hw.init = &(struct clk_init_data){	1090	.hw.init = &(struct clk_init_data){
1005	.name = "mali",	1091	.name = "mali",
1006	.ops = &clk_regmap_mux_ops,	1092	.ops = &clk_regmap_mux_ops,
1007	.parent_names = gxbb_mali_parent_names,	1093	.parent_hws = gxbb_mali_parent_hws,
1008	.num_parents = 2,	1094	.num_parents = 2,
1009	.flags = CLK_SET_RATE_NO_REPARENT,	1095	.flags = CLK_SET_RATE_NO_REPARENT,
1010	},	1096	},
@@ -1021,7 +1107,11 @@ static struct clk_regmap gxbb_cts_amclk_sel = { · 10 unmodified lines
1021	.hw.init = &(struct clk_init_data){	1107	.hw.init = &(struct clk_init_data){
1022	.name = "cts_amclk_sel",	1108	.name = "cts_amclk_sel",
1023	.ops = &clk_regmap_mux_ops,	1109	.ops = &clk_regmap_mux_ops,
1024	.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },	1110	.parent_hws = (const struct clk_hw *[]) {
		1111	&gxbb_mpll0.hw,
		1112	&gxbb_mpll1.hw,
		1113	&gxbb_mpll2.hw,
		1114	},
1025	.num_parents = 3,	1115	.num_parents = 3,
1026	},	1116	},
1027	};	1117	};
@@ -1036,7 +1126,9 @@ static struct clk_regmap gxbb_cts_amclk_div = { · 8 unmodified lines
1036	.hw.init = &(struct clk_init_data){	1126	.hw.init = &(struct clk_init_data){
1037	.name = "cts_amclk_div",	1127	.name = "cts_amclk_div",
1038	.ops = &clk_regmap_divider_ops,	1128	.ops = &clk_regmap_divider_ops,
1039	.parent_names = (const char *[]){ "cts_amclk_sel" },	1129	.parent_hws = (const struct clk_hw *[]) {
		1130	&gxbb_cts_amclk_sel.hw
		1131	},
1040	.num_parents = 1,	1132	.num_parents = 1,
1041	.flags = CLK_SET_RATE_PARENT,	1133	.flags = CLK_SET_RATE_PARENT,
1042	},	1134	},
@@ -1050,7 +1142,9 @@ static struct clk_regmap gxbb_cts_amclk = { · 7 unmodified lines
1050	.hw.init = &(struct clk_init_data){	1142	.hw.init = &(struct clk_init_data){
1051	.name = "cts_amclk",	1143	.name = "cts_amclk",
1052	.ops = &clk_regmap_gate_ops,	1144	.ops = &clk_regmap_gate_ops,
1053	.parent_names = (const char *[]){ "cts_amclk_div" },	1145	.parent_hws = (const struct clk_hw *[]) {
		1146	&gxbb_cts_amclk_div.hw
		1147	},
1054	.num_parents = 1,	1148	.num_parents = 1,
1055	.flags = CLK_SET_RATE_PARENT,	1149	.flags = CLK_SET_RATE_PARENT,
1056	},	1150	},
@@ -1067,7 +1161,11 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel = { · 10 unmodified lines
1067	.hw.init = &(struct clk_init_data) {	1161	.hw.init = &(struct clk_init_data) {
1068	.name = "cts_mclk_i958_sel",	1162	.name = "cts_mclk_i958_sel",
1069	.ops = &clk_regmap_mux_ops,	1163	.ops = &clk_regmap_mux_ops,
1070	.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },	1164	.parent_hws = (const struct clk_hw *[]) {
		1165	&gxbb_mpll0.hw,
		1166	&gxbb_mpll1.hw,
		1167	&gxbb_mpll2.hw,
		1168	},
1071	.num_parents = 3,	1169	.num_parents = 3,
1072	},	1170	},
1073	};	1171	};
@@ -1082,7 +1180,9 @@ static struct clk_regmap gxbb_cts_mclk_i958_div = { · 8 unmodified lines
1082	.hw.init = &(struct clk_init_data) {	1180	.hw.init = &(struct clk_init_data) {
1083	.name = "cts_mclk_i958_div",	1181	.name = "cts_mclk_i958_div",
1084	.ops = &clk_regmap_divider_ops,	1182	.ops = &clk_regmap_divider_ops,
1085	.parent_names = (const char *[]){ "cts_mclk_i958_sel" },	1183	.parent_hws = (const struct clk_hw *[]) {
		1184	&gxbb_cts_mclk_i958_sel.hw
		1185	},
1086	.num_parents = 1,	1186	.num_parents = 1,
1087	.flags = CLK_SET_RATE_PARENT,	1187	.flags = CLK_SET_RATE_PARENT,
1088	},	1188	},
@@ -1096,7 +1196,9 @@ static struct clk_regmap gxbb_cts_mclk_i958 = { · 7 unmodified lines
1096	.hw.init = &(struct clk_init_data){	1196	.hw.init = &(struct clk_init_data){
1097	.name = "cts_mclk_i958",	1197	.name = "cts_mclk_i958",
1098	.ops = &clk_regmap_gate_ops,	1198	.ops = &clk_regmap_gate_ops,
1099	.parent_names = (const char *[]){ "cts_mclk_i958_div" },	1199	.parent_hws = (const struct clk_hw *[]) {
		1200	&gxbb_cts_mclk_i958_div.hw
		1201	},
1100	.num_parents = 1,	1202	.num_parents = 1,
1101	.flags = CLK_SET_RATE_PARENT,	1203	.flags = CLK_SET_RATE_PARENT,
1102	},	1204	},
@@ -1111,7 +1213,10 @@ static struct clk_regmap gxbb_cts_i958 = { · 8 unmodified lines
1111	.hw.init = &(struct clk_init_data){	1213	.hw.init = &(struct clk_init_data){
1112	.name = "cts_i958",	1214	.name = "cts_i958",
1113	.ops = &clk_regmap_mux_ops,	1215	.ops = &clk_regmap_mux_ops,
1114	.parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },	1216	.parent_hws = (const struct clk_hw *[]) {
		1217	&gxbb_cts_amclk.hw,
		1218	&gxbb_cts_mclk_i958.hw
		1219	},
1115	.num_parents = 2,	1220	.num_parents = 2,
1116	/*	1221	/*
1117	*The parent is specific to origin of the audio data. Let the	1222	*The parent is specific to origin of the audio data. Let the
@@ -1121,6 +1226,33 @@ static struct clk_regmap gxbb_cts_i958 = { · 3 unmodified lines
1121	},	1226	},
1122	};	1227	};
1123		1228
		1229	static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
		1230	{ .fw_name = "xtal", },
		1231	/*
		1232	* FIXME: This clock is provided by the ao clock controller but the
		1233	* clock is not yet part of the binding of this controller, so string
		1234	* name must be use to set this parent.
		1235	*/
		1236	{ .name = "cts_slow_oscin", .index = -1 },
		1237	{ .hw = &gxbb_fclk_div3.hw },
		1238	{ .hw = &gxbb_fclk_div5.hw },
		1239	};
		1240
		1241	static struct clk_regmap gxbb_32k_clk_sel = {
		1242	.data = &(struct clk_regmap_mux_data){
		1243	.offset = HHI_32K_CLK_CNTL,
		1244	.mask = 0x3,
		1245	.shift = 16,
		1246	},
		1247	.hw.init = &(struct clk_init_data){
		1248	.name = "32k_clk_sel",
		1249	.ops = &clk_regmap_mux_ops,
		1250	.parent_data = gxbb_32k_clk_parent_data,
		1251	.num_parents = 4,
		1252	.flags = CLK_SET_RATE_PARENT,
		1253	},
		1254	};
		1255
1124	static struct clk_regmap gxbb_32k_clk_div = {	1256	static struct clk_regmap gxbb_32k_clk_div = {
1125	.data = &(struct clk_regmap_div_data){	1257	.data = &(struct clk_regmap_div_data){
1126	.offset = HHI_32K_CLK_CNTL,	1258	.offset = HHI_32K_CLK_CNTL,
@@ -1130,7 +1262,9 @@ static struct clk_regmap gxbb_32k_clk_div = { · 3 unmodified lines
1130	.hw.init = &(struct clk_init_data){	1262	.hw.init = &(struct clk_init_data){
1131	.name = "32k_clk_div",	1263	.name = "32k_clk_div",
1132	.ops = &clk_regmap_divider_ops,	1264	.ops = &clk_regmap_divider_ops,
1133	.parent_names = (const char *[]){ "32k_clk_sel" },	1265	.parent_hws = (const struct clk_hw *[]) {
		1266	&gxbb_32k_clk_sel.hw
		1267	},
1134	.num_parents = 1,	1268	.num_parents = 1,
1135	.flags = CLK_SET_RATE_PARENT \| CLK_DIVIDER_ROUND_CLOSEST,	1269	.flags = CLK_SET_RATE_PARENT \| CLK_DIVIDER_ROUND_CLOSEST,
1136	},	1270	},
@@ -1144,34 +1278,20 @@ static struct clk_regmap gxbb_32k_clk = { · 7 unmodified lines
1144	.hw.init = &(struct clk_init_data){	1278	.hw.init = &(struct clk_init_data){
1145	.name = "32k_clk",	1279	.name = "32k_clk",
1146	.ops = &clk_regmap_gate_ops,	1280	.ops = &clk_regmap_gate_ops,
1147	.parent_names = (const char *[]){ "32k_clk_div" },	1281	.parent_hws = (const struct clk_hw *[]) {
1148	.num_parents = 1,	1282	&gxbb_32k_clk_div.hw
1149	.flags = CLK_SET_RATE_PARENT,
1150	},
1151	};
1152
1153	static const char * const gxbb_32k_clk_parent_names[] = {
1154	IN_PREFIX "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1155	};
1156
1157	static struct clk_regmap gxbb_32k_clk_sel = {
1158	.data = &(struct clk_regmap_mux_data){
1159	.offset = HHI_32K_CLK_CNTL,
1160	.mask = 0x3,
1161	.shift = 16,
1162	},	1283	},
1163	.hw.init = &(struct clk_init_data){	1284	.num_parents = 1,
1164	.name = "32k_clk_sel",
1165	.ops = &clk_regmap_mux_ops,
1166	.parent_names = gxbb_32k_clk_parent_names,
1167	.num_parents = 4,
1168	.flags = CLK_SET_RATE_PARENT,	1285	.flags = CLK_SET_RATE_PARENT,
1169	},	1286	},
1170	};	1287	};
1171		1288
1172	static const char * const gxbb_sd_emmc_clk0_parent_names[] = {	1289	static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1173	IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",	1290	{ .fw_name = "xtal", },
1174		1291	{ .hw = &gxbb_fclk_div2.hw },
		1292	{ .hw = &gxbb_fclk_div3.hw },
		1293	{ .hw = &gxbb_fclk_div5.hw },
		1294	{ .hw = &gxbb_fclk_div7.hw },
1175	/*	1295	/*
1176	* Following these parent clocks, we should also have had mpll2, mpll3	1296	* Following these parent clocks, we should also have had mpll2, mpll3
1177	* and gp0_pll but these clocks are too precious to be used here. All	1297	* and gp0_pll but these clocks are too precious to be used here. All
@@ -1190,8 +1310,8 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { · 12 unmodified lines
1190	.hw.init = &(struct clk_init_data) {	1310	.hw.init = &(struct clk_init_data) {
1191	.name = "sd_emmc_a_clk0_sel",	1311	.name = "sd_emmc_a_clk0_sel",
1192	.ops = &clk_regmap_mux_ops,	1312	.ops = &clk_regmap_mux_ops,
1193	.parent_names = gxbb_sd_emmc_clk0_parent_names,	1313	.parent_data = gxbb_sd_emmc_clk0_parent_data,
1194	.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),	1314	.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1195	.flags = CLK_SET_RATE_PARENT,	1315	.flags = CLK_SET_RATE_PARENT,
1196	},	1316	},
1197	};	1317	};
@@ -1206,7 +1326,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { · 8 unmodified lines
1206	.hw.init = &(struct clk_init_data) {	1326	.hw.init = &(struct clk_init_data) {
1207	.name = "sd_emmc_a_clk0_div",	1327	.name = "sd_emmc_a_clk0_div",
1208	.ops = &clk_regmap_divider_ops,	1328	.ops = &clk_regmap_divider_ops,
1209	.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },	1329	.parent_hws = (const struct clk_hw *[]) {
		1330	&gxbb_sd_emmc_a_clk0_sel.hw
		1331	},
1210	.num_parents = 1,	1332	.num_parents = 1,
1211	.flags = CLK_SET_RATE_PARENT,	1333	.flags = CLK_SET_RATE_PARENT,
1212	},	1334	},
@@ -1220,7 +1342,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0 = { · 7 unmodified lines
1220	.hw.init = &(struct clk_init_data){	1342	.hw.init = &(struct clk_init_data){
1221	.name = "sd_emmc_a_clk0",	1343	.name = "sd_emmc_a_clk0",
1222	.ops = &clk_regmap_gate_ops,	1344	.ops = &clk_regmap_gate_ops,
1223	.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },	1345	.parent_hws = (const struct clk_hw *[]) {
		1346	&gxbb_sd_emmc_a_clk0_div.hw
		1347	},
1224	.num_parents = 1,	1348	.num_parents = 1,
1225	.flags = CLK_SET_RATE_PARENT,	1349	.flags = CLK_SET_RATE_PARENT,
1226	},	1350	},
@@ -1236,8 +1360,8 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { · 9 unmodified lines
1236	.hw.init = &(struct clk_init_data) {	1360	.hw.init = &(struct clk_init_data) {
1237	.name = "sd_emmc_b_clk0_sel",	1361	.name = "sd_emmc_b_clk0_sel",
1238	.ops = &clk_regmap_mux_ops,	1362	.ops = &clk_regmap_mux_ops,
1239	.parent_names = gxbb_sd_emmc_clk0_parent_names,	1363	.parent_data = gxbb_sd_emmc_clk0_parent_data,
1240	.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),	1364	.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1241	.flags = CLK_SET_RATE_PARENT,	1365	.flags = CLK_SET_RATE_PARENT,
1242	},	1366	},
1243	};	1367	};
@@ -1252,7 +1376,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { · 8 unmodified lines
1252	.hw.init = &(struct clk_init_data) {	1376	.hw.init = &(struct clk_init_data) {
1253	.name = "sd_emmc_b_clk0_div",	1377	.name = "sd_emmc_b_clk0_div",
1254	.ops = &clk_regmap_divider_ops,	1378	.ops = &clk_regmap_divider_ops,
1255	.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },	1379	.parent_hws = (const struct clk_hw *[]) {
		1380	&gxbb_sd_emmc_b_clk0_sel.hw
		1381	},
1256	.num_parents = 1,	1382	.num_parents = 1,
1257	.flags = CLK_SET_RATE_PARENT,	1383	.flags = CLK_SET_RATE_PARENT,
1258	},	1384	},
@@ -1266,7 +1392,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0 = { · 7 unmodified lines
1266	.hw.init = &(struct clk_init_data){	1392	.hw.init = &(struct clk_init_data){
1267	.name = "sd_emmc_b_clk0",	1393	.name = "sd_emmc_b_clk0",
1268	.ops = &clk_regmap_gate_ops,	1394	.ops = &clk_regmap_gate_ops,
1269	.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },	1395	.parent_hws = (const struct clk_hw *[]) {
		1396	&gxbb_sd_emmc_b_clk0_div.hw
		1397	},
1270	.num_parents = 1,	1398	.num_parents = 1,
1271	.flags = CLK_SET_RATE_PARENT,	1399	.flags = CLK_SET_RATE_PARENT,
1272	},	1400	},
@@ -1282,8 +1410,8 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { · 9 unmodified lines
1282	.hw.init = &(struct clk_init_data) {	1410	.hw.init = &(struct clk_init_data) {
1283	.name = "sd_emmc_c_clk0_sel",	1411	.name = "sd_emmc_c_clk0_sel",
1284	.ops = &clk_regmap_mux_ops,	1412	.ops = &clk_regmap_mux_ops,
1285	.parent_names = gxbb_sd_emmc_clk0_parent_names,	1413	.parent_data = gxbb_sd_emmc_clk0_parent_data,
1286	.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),	1414	.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1287	.flags = CLK_SET_RATE_PARENT,	1415	.flags = CLK_SET_RATE_PARENT,
1288	},	1416	},
1289	};	1417	};
@@ -1298,7 +1426,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { · 8 unmodified lines
1298	.hw.init = &(struct clk_init_data) {	1426	.hw.init = &(struct clk_init_data) {
1299	.name = "sd_emmc_c_clk0_div",	1427	.name = "sd_emmc_c_clk0_div",
1300	.ops = &clk_regmap_divider_ops,	1428	.ops = &clk_regmap_divider_ops,
1301	.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },	1429	.parent_hws = (const struct clk_hw *[]) {
		1430	&gxbb_sd_emmc_c_clk0_sel.hw
		1431	},
1302	.num_parents = 1,	1432	.num_parents = 1,
1303	.flags = CLK_SET_RATE_PARENT,	1433	.flags = CLK_SET_RATE_PARENT,
1304	},	1434	},
@@ -1312,7 +1442,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = { · 7 unmodified lines
1312	.hw.init = &(struct clk_init_data){	1442	.hw.init = &(struct clk_init_data){
1313	.name = "sd_emmc_c_clk0",	1443	.name = "sd_emmc_c_clk0",
1314	.ops = &clk_regmap_gate_ops,	1444	.ops = &clk_regmap_gate_ops,
1315	.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },	1445	.parent_hws = (const struct clk_hw *[]) {
		1446	&gxbb_sd_emmc_c_clk0_div.hw
		1447	},
1316	.num_parents = 1,	1448	.num_parents = 1,
1317	.flags = CLK_SET_RATE_PARENT,	1449	.flags = CLK_SET_RATE_PARENT,
1318	},	1450	},
@@ -1320,8 +1452,11 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = { · 1 unmodified line
1320		1452
1321	/* VPU Clock */	1453	/* VPU Clock */
1322		1454
1323	static const char * const gxbb_vpu_parent_names[] = {	1455	static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1324	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"	1456	&gxbb_fclk_div4.hw,
		1457	&gxbb_fclk_div3.hw,
		1458	&gxbb_fclk_div5.hw,
		1459	&gxbb_fclk_div7.hw,
1325	};	1460	};
1326		1461
1327	static struct clk_regmap gxbb_vpu_0_sel = {	1462	static struct clk_regmap gxbb_vpu_0_sel = {
@@ -1337,8 +1472,8 @@ static struct clk_regmap gxbb_vpu_0_sel = { · 9 unmodified lines
1337	* bits 9:10 selects from 4 possible parents:	1472	* bits 9:10 selects from 4 possible parents:
1338	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,	1473	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1339	*/	1474	*/
1340	.parent_names = gxbb_vpu_parent_names,	1475	.parent_hws = gxbb_vpu_parent_hws,
1341	.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),	1476	.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1342	.flags = CLK_SET_RATE_NO_REPARENT,	1477	.flags = CLK_SET_RATE_NO_REPARENT,
1343	},	1478	},
1344	};	1479	};
@@ -1352,7 +1487,7 @@ static struct clk_regmap gxbb_vpu_0_div = { · 7 unmodified lines
1352	.hw.init = &(struct clk_init_data){	1487	.hw.init = &(struct clk_init_data){
1353	.name = "vpu_0_div",	1488	.name = "vpu_0_div",
1354	.ops = &clk_regmap_divider_ops,	1489	.ops = &clk_regmap_divider_ops,
1355	.parent_names = (const char *[]){ "vpu_0_sel" },	1490	.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1356	.num_parents = 1,	1491	.num_parents = 1,
1357	.flags = CLK_SET_RATE_PARENT,	1492	.flags = CLK_SET_RATE_PARENT,
1358	},	1493	},
@@ -1366,7 +1501,7 @@ static struct clk_regmap gxbb_vpu_0 = { · 7 unmodified lines
1366	.hw.init = &(struct clk_init_data) {	1501	.hw.init = &(struct clk_init_data) {
1367	.name = "vpu_0",	1502	.name = "vpu_0",
1368	.ops = &clk_regmap_gate_ops,	1503	.ops = &clk_regmap_gate_ops,
1369	.parent_names = (const char *[]){ "vpu_0_div" },	1504	.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1370	.num_parents = 1,	1505	.num_parents = 1,
1371	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1506	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1372	},	1507	},
@@ -1385,8 +1520,8 @@ static struct clk_regmap gxbb_vpu_1_sel = { · 12 unmodified lines
1385	* bits 25:26 selects from 4 possible parents:	1520	* bits 25:26 selects from 4 possible parents:
1386	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,	1521	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1387	*/	1522	*/
1388	.parent_names = gxbb_vpu_parent_names,	1523	.parent_hws = gxbb_vpu_parent_hws,
1389	.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),	1524	.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1390	.flags = CLK_SET_RATE_NO_REPARENT,	1525	.flags = CLK_SET_RATE_NO_REPARENT,
1391	},	1526	},
1392	};	1527	};
@@ -1400,7 +1535,7 @@ static struct clk_regmap gxbb_vpu_1_div = { · 7 unmodified lines
1400	.hw.init = &(struct clk_init_data){	1535	.hw.init = &(struct clk_init_data){
1401	.name = "vpu_1_div",	1536	.name = "vpu_1_div",
1402	.ops = &clk_regmap_divider_ops,	1537	.ops = &clk_regmap_divider_ops,
1403	.parent_names = (const char *[]){ "vpu_1_sel" },	1538	.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1404	.num_parents = 1,	1539	.num_parents = 1,
1405	.flags = CLK_SET_RATE_PARENT,	1540	.flags = CLK_SET_RATE_PARENT,
1406	},	1541	},
@@ -1414,7 +1549,7 @@ static struct clk_regmap gxbb_vpu_1 = { · 7 unmodified lines
1414	.hw.init = &(struct clk_init_data) {	1549	.hw.init = &(struct clk_init_data) {
1415	.name = "vpu_1",	1550	.name = "vpu_1",
1416	.ops = &clk_regmap_gate_ops,	1551	.ops = &clk_regmap_gate_ops,
1417	.parent_names = (const char *[]){ "vpu_1_div" },	1552	.parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1418	.num_parents = 1,	1553	.num_parents = 1,
1419	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1554	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1420	},	1555	},
@@ -1433,7 +1568,10 @@ static struct clk_regmap gxbb_vpu = { · 12 unmodified lines
1433	* bit 31 selects from 2 possible parents:	1568	* bit 31 selects from 2 possible parents:
1434	* vpu_0 or vpu_1	1569	* vpu_0 or vpu_1
1435	*/	1570	*/
1436	.parent_names = (const char *[]){ "vpu_0", "vpu_1" },	1571	.parent_hws = (const struct clk_hw *[]) {
		1572	&gxbb_vpu_0.hw,
		1573	&gxbb_vpu_1.hw
		1574	},
1437	.num_parents = 2,	1575	.num_parents = 2,
1438	.flags = CLK_SET_RATE_NO_REPARENT,	1576	.flags = CLK_SET_RATE_NO_REPARENT,
1439	},	1577	},
@@ -1441,8 +1579,11 @@ static struct clk_regmap gxbb_vpu = { · 1 unmodified line
1441		1579
1442	/* VAPB Clock */	1580	/* VAPB Clock */
1443		1581
1444	static const char * const gxbb_vapb_parent_names[] = {	1582	static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1445	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"	1583	&gxbb_fclk_div4.hw,
		1584	&gxbb_fclk_div3.hw,
		1585	&gxbb_fclk_div5.hw,
		1586	&gxbb_fclk_div7.hw,
1446	};	1587	};
1447		1588
1448	static struct clk_regmap gxbb_vapb_0_sel = {	1589	static struct clk_regmap gxbb_vapb_0_sel = {
@@ -1458,8 +1599,8 @@ static struct clk_regmap gxbb_vapb_0_sel = { · 9 unmodified lines
1458	* bits 9:10 selects from 4 possible parents:	1599	* bits 9:10 selects from 4 possible parents:
1459	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,	1600	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1460	*/	1601	*/
1461	.parent_names = gxbb_vapb_parent_names,	1602	.parent_hws = gxbb_vapb_parent_hws,
1462	.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),	1603	.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1463	.flags = CLK_SET_RATE_NO_REPARENT,	1604	.flags = CLK_SET_RATE_NO_REPARENT,
1464	},	1605	},
1465	};	1606	};
@@ -1473,7 +1614,9 @@ static struct clk_regmap gxbb_vapb_0_div = { · 7 unmodified lines
1473	.hw.init = &(struct clk_init_data){	1614	.hw.init = &(struct clk_init_data){
1474	.name = "vapb_0_div",	1615	.name = "vapb_0_div",
1475	.ops = &clk_regmap_divider_ops,	1616	.ops = &clk_regmap_divider_ops,
1476	.parent_names = (const char *[]){ "vapb_0_sel" },	1617	.parent_hws = (const struct clk_hw *[]) {
		1618	&gxbb_vapb_0_sel.hw
		1619	},
1477	.num_parents = 1,	1620	.num_parents = 1,
1478	.flags = CLK_SET_RATE_PARENT,	1621	.flags = CLK_SET_RATE_PARENT,
1479	},	1622	},
@@ -1487,7 +1630,9 @@ static struct clk_regmap gxbb_vapb_0 = { · 7 unmodified lines
1487	.hw.init = &(struct clk_init_data) {	1630	.hw.init = &(struct clk_init_data) {
1488	.name = "vapb_0",	1631	.name = "vapb_0",
1489	.ops = &clk_regmap_gate_ops,	1632	.ops = &clk_regmap_gate_ops,
1490	.parent_names = (const char *[]){ "vapb_0_div" },	1633	.parent_hws = (const struct clk_hw *[]) {
		1634	&gxbb_vapb_0_div.hw
		1635	},
1491	.num_parents = 1,	1636	.num_parents = 1,
1492	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1637	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1493	},	1638	},
@@ -1506,8 +1651,8 @@ static struct clk_regmap gxbb_vapb_1_sel = { · 12 unmodified lines
1506	* bits 25:26 selects from 4 possible parents:	1651	* bits 25:26 selects from 4 possible parents:
1507	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,	1652	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1508	*/	1653	*/
1509	.parent_names = gxbb_vapb_parent_names,	1654	.parent_hws = gxbb_vapb_parent_hws,
1510	.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),	1655	.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1511	.flags = CLK_SET_RATE_NO_REPARENT,	1656	.flags = CLK_SET_RATE_NO_REPARENT,
1512	},	1657	},
1513	};	1658	};
@@ -1521,7 +1666,9 @@ static struct clk_regmap gxbb_vapb_1_div = { · 7 unmodified lines
1521	.hw.init = &(struct clk_init_data){	1666	.hw.init = &(struct clk_init_data){
1522	.name = "vapb_1_div",	1667	.name = "vapb_1_div",
1523	.ops = &clk_regmap_divider_ops,	1668	.ops = &clk_regmap_divider_ops,
1524	.parent_names = (const char *[]){ "vapb_1_sel" },	1669	.parent_hws = (const struct clk_hw *[]) {
		1670	&gxbb_vapb_1_sel.hw
		1671	},
1525	.num_parents = 1,	1672	.num_parents = 1,
1526	.flags = CLK_SET_RATE_PARENT,	1673	.flags = CLK_SET_RATE_PARENT,
1527	},	1674	},
@@ -1535,7 +1682,9 @@ static struct clk_regmap gxbb_vapb_1 = { · 7 unmodified lines
1535	.hw.init = &(struct clk_init_data) {	1682	.hw.init = &(struct clk_init_data) {
1536	.name = "vapb_1",	1683	.name = "vapb_1",
1537	.ops = &clk_regmap_gate_ops,	1684	.ops = &clk_regmap_gate_ops,
1538	.parent_names = (const char *[]){ "vapb_1_div" },	1685	.parent_hws = (const struct clk_hw *[]) {
		1686	&gxbb_vapb_1_div.hw
		1687	},
1539	.num_parents = 1,	1688	.num_parents = 1,
1540	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1689	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1541	},	1690	},
@@ -1554,7 +1703,10 @@ static struct clk_regmap gxbb_vapb_sel = { · 12 unmodified lines
1554	* bit 31 selects from 2 possible parents:	1703	* bit 31 selects from 2 possible parents:
1555	* vapb_0 or vapb_1	1704	* vapb_0 or vapb_1
1556	*/	1705	*/
1557	.parent_names = (const char *[]){ "vapb_0", "vapb_1" },	1706	.parent_hws = (const struct clk_hw *[]) {
		1707	&gxbb_vapb_0.hw,
		1708	&gxbb_vapb_1.hw
		1709	},
1558	.num_parents = 2,	1710	.num_parents = 2,
1559	.flags = CLK_SET_RATE_NO_REPARENT,	1711	.flags = CLK_SET_RATE_NO_REPARENT,
1560	},	1712	},
@@ -1568,7 +1720,7 @@ static struct clk_regmap gxbb_vapb = { · 7 unmodified lines
1568	.hw.init = &(struct clk_init_data) {	1720	.hw.init = &(struct clk_init_data) {
1569	.name = "vapb",	1721	.name = "vapb",
1570	.ops = &clk_regmap_gate_ops,	1722	.ops = &clk_regmap_gate_ops,
1571	.parent_names = (const char *[]){ "vapb_sel" },	1723	.parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1572	.num_parents = 1,	1724	.num_parents = 1,
1573	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1725	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1574	},	1726	},
@@ -1592,13 +1744,33 @@ static struct clk_regmap gxbb_vid_pll_div = { · 17 unmodified lines
1592	.hw.init = &(struct clk_init_data) {	1744	.hw.init = &(struct clk_init_data) {
1593	.name = "vid_pll_div",	1745	.name = "vid_pll_div",
1594	.ops = &meson_vid_pll_div_ro_ops,	1746	.ops = &meson_vid_pll_div_ro_ops,
1595	.parent_names = (const char *[]){ "hdmi_pll" },	1747	.parent_data = &(const struct clk_parent_data) {
		1748	/*
		1749	* Note:
		1750	* GXL and GXBB have different hdmi_plls (with
		1751	* different struct clk_hw). We fallback to the global
		1752	* naming string mechanism so vid_pll_div picks up the
		1753	* appropriate one.
		1754	*/
		1755	.name = "hdmi_pll",
		1756	.index = -1,
		1757	},
1596	.num_parents = 1,	1758	.num_parents = 1,
1597	.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,	1759	.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
1598	},	1760	},
1599	};	1761	};
1600		1762
1601	static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };	1763	static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
		1764	{ .hw = &gxbb_vid_pll_div.hw },
		1765	/*
		1766	* Note:
		1767	* GXL and GXBB have different hdmi_plls (with
		1768	* different struct clk_hw). We fallback to the global
		1769	* naming string mechanism so vid_pll_div picks up the
		1770	* appropriate one.
		1771	*/
		1772	{ .name = "hdmi_pll", .index = -1 },
		1773	};
1602		1774
1603	static struct clk_regmap gxbb_vid_pll_sel = {	1775	static struct clk_regmap gxbb_vid_pll_sel = {
1604	.data = &(struct clk_regmap_mux_data){	1776	.data = &(struct clk_regmap_mux_data){
@@ -1613,8 +1785,8 @@ static struct clk_regmap gxbb_vid_pll_sel = { · 8 unmodified lines
1613	* bit 18 selects from 2 possible parents:	1785	* bit 18 selects from 2 possible parents:
1614	* vid_pll_div or hdmi_pll	1786	* vid_pll_div or hdmi_pll
1615	*/	1787	*/
1616	.parent_names = gxbb_vid_pll_parent_names,	1788	.parent_data = gxbb_vid_pll_parent_data,
1617	.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names),	1789	.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1618	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	1790	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
1619	},	1791	},
1620	};	1792	};
@@ -1627,15 +1799,22 @@ static struct clk_regmap gxbb_vid_pll = { · 6 unmodified lines
1627	.hw.init = &(struct clk_init_data) {	1799	.hw.init = &(struct clk_init_data) {
1628	.name = "vid_pll",	1800	.name = "vid_pll",
1629	.ops = &clk_regmap_gate_ops,	1801	.ops = &clk_regmap_gate_ops,
1630	.parent_names = (const char *[]){ "vid_pll_sel" },	1802	.parent_hws = (const struct clk_hw *[]) {
		1803	&gxbb_vid_pll_sel.hw
		1804	},
1631	.num_parents = 1,	1805	.num_parents = 1,
1632	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1806	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1633	},	1807	},
1634	};	1808	};
1635		1809
1636	static const char * const gxbb_vclk_parent_names[] = {	1810	static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1637	"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",	1811	&gxbb_vid_pll.hw,
1638	"fclk_div7", "mpll1",	1812	&gxbb_fclk_div4.hw,
		1813	&gxbb_fclk_div3.hw,
		1814	&gxbb_fclk_div5.hw,
		1815	&gxbb_vid_pll.hw,
		1816	&gxbb_fclk_div7.hw,
		1817	&gxbb_mpll1.hw,
1639	};	1818	};
1640		1819
1641	static struct clk_regmap gxbb_vclk_sel = {	1820	static struct clk_regmap gxbb_vclk_sel = {
@@ -1652,8 +1831,8 @@ static struct clk_regmap gxbb_vclk_sel = { · 10 unmodified lines
1652	* vid_pll, fclk_div4, fclk_div3, fclk_div5,	1831	* vid_pll, fclk_div4, fclk_div3, fclk_div5,
1653	* vid_pll, fclk_div7, mp1	1832	* vid_pll, fclk_div7, mp1
1654	*/	1833	*/
1655	.parent_names = gxbb_vclk_parent_names,	1834	.parent_hws = gxbb_vclk_parent_hws,
1656	.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),	1835	.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1657	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	1836	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
1658	},	1837	},
1659	};	1838	};
@@ -1672,8 +1851,8 @@ static struct clk_regmap gxbb_vclk2_sel = { · 12 unmodified lines
1672	* vid_pll, fclk_div4, fclk_div3, fclk_div5,	1851	* vid_pll, fclk_div4, fclk_div3, fclk_div5,
1673	* vid_pll, fclk_div7, mp1	1852	* vid_pll, fclk_div7, mp1
1674	*/	1853	*/
1675	.parent_names = gxbb_vclk_parent_names,	1854	.parent_hws = gxbb_vclk_parent_hws,
1676	.num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),	1855	.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1677	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	1856	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
1678	},	1857	},
1679	};	1858	};
@@ -1686,7 +1865,7 @@ static struct clk_regmap gxbb_vclk_input = { · 6 unmodified lines
1686	.hw.init = &(struct clk_init_data) {	1865	.hw.init = &(struct clk_init_data) {
1687	.name = "vclk_input",	1866	.name = "vclk_input",
1688	.ops = &clk_regmap_gate_ops,	1867	.ops = &clk_regmap_gate_ops,
1689	.parent_names = (const char *[]){ "vclk_sel" },	1868	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1690	.num_parents = 1,	1869	.num_parents = 1,
1691	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1870	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1692	},	1871	},
@@ -1700,7 +1879,7 @@ static struct clk_regmap gxbb_vclk2_input = { · 7 unmodified lines
1700	.hw.init = &(struct clk_init_data) {	1879	.hw.init = &(struct clk_init_data) {
1701	.name = "vclk2_input",	1880	.name = "vclk2_input",
1702	.ops = &clk_regmap_gate_ops,	1881	.ops = &clk_regmap_gate_ops,
1703	.parent_names = (const char *[]){ "vclk2_sel" },	1882	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1704	.num_parents = 1,	1883	.num_parents = 1,
1705	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1884	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1706	},	1885	},
@@ -1715,7 +1894,9 @@ static struct clk_regmap gxbb_vclk_div = { · 8 unmodified lines
1715	.hw.init = &(struct clk_init_data){	1894	.hw.init = &(struct clk_init_data){
1716	.name = "vclk_div",	1895	.name = "vclk_div",
1717	.ops = &clk_regmap_divider_ops,	1896	.ops = &clk_regmap_divider_ops,
1718	.parent_names = (const char *[]){ "vclk_input" },	1897	.parent_hws = (const struct clk_hw *[]) {
		1898	&gxbb_vclk_input.hw
		1899	},
1719	.num_parents = 1,	1900	.num_parents = 1,
1720	.flags = CLK_GET_RATE_NOCACHE,	1901	.flags = CLK_GET_RATE_NOCACHE,
1721	},	1902	},
@@ -1730,7 +1911,9 @@ static struct clk_regmap gxbb_vclk2_div = { · 8 unmodified lines
1730	.hw.init = &(struct clk_init_data){	1911	.hw.init = &(struct clk_init_data){
1731	.name = "vclk2_div",	1912	.name = "vclk2_div",
1732	.ops = &clk_regmap_divider_ops,	1913	.ops = &clk_regmap_divider_ops,
1733	.parent_names = (const char *[]){ "vclk2_input" },	1914	.parent_hws = (const struct clk_hw *[]) {
		1915	&gxbb_vclk2_input.hw
		1916	},
1734	.num_parents = 1,	1917	.num_parents = 1,
1735	.flags = CLK_GET_RATE_NOCACHE,	1918	.flags = CLK_GET_RATE_NOCACHE,
1736	},	1919	},
@@ -1744,7 +1927,7 @@ static struct clk_regmap gxbb_vclk = { · 7 unmodified lines
1744	.hw.init = &(struct clk_init_data) {	1927	.hw.init = &(struct clk_init_data) {
1745	.name = "vclk",	1928	.name = "vclk",
1746	.ops = &clk_regmap_gate_ops,	1929	.ops = &clk_regmap_gate_ops,
1747	.parent_names = (const char *[]){ "vclk_div" },	1930	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1748	.num_parents = 1,	1931	.num_parents = 1,
1749	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1932	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1750	},	1933	},
@@ -1758,7 +1941,7 @@ static struct clk_regmap gxbb_vclk2 = { · 7 unmodified lines
1758	.hw.init = &(struct clk_init_data) {	1941	.hw.init = &(struct clk_init_data) {
1759	.name = "vclk2",	1942	.name = "vclk2",
1760	.ops = &clk_regmap_gate_ops,	1943	.ops = &clk_regmap_gate_ops,
1761	.parent_names = (const char *[]){ "vclk2_div" },	1944	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1762	.num_parents = 1,	1945	.num_parents = 1,
1763	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1946	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1764	},	1947	},
@@ -1772,7 +1955,7 @@ static struct clk_regmap gxbb_vclk_div1 = { · 7 unmodified lines
1772	.hw.init = &(struct clk_init_data) {	1955	.hw.init = &(struct clk_init_data) {
1773	.name = "vclk_div1",	1956	.name = "vclk_div1",
1774	.ops = &clk_regmap_gate_ops,	1957	.ops = &clk_regmap_gate_ops,
1775	.parent_names = (const char *[]){ "vclk" },	1958	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1776	.num_parents = 1,	1959	.num_parents = 1,
1777	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1960	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1778	},	1961	},
@@ -1786,7 +1969,7 @@ static struct clk_regmap gxbb_vclk_div2_en = { · 7 unmodified lines
1786	.hw.init = &(struct clk_init_data) {	1969	.hw.init = &(struct clk_init_data) {
1787	.name = "vclk_div2_en",	1970	.name = "vclk_div2_en",
1788	.ops = &clk_regmap_gate_ops,	1971	.ops = &clk_regmap_gate_ops,
1789	.parent_names = (const char *[]){ "vclk" },	1972	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1790	.num_parents = 1,	1973	.num_parents = 1,
1791	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1974	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1792	},	1975	},
@@ -1800,7 +1983,7 @@ static struct clk_regmap gxbb_vclk_div4_en = { · 7 unmodified lines
1800	.hw.init = &(struct clk_init_data) {	1983	.hw.init = &(struct clk_init_data) {
1801	.name = "vclk_div4_en",	1984	.name = "vclk_div4_en",
1802	.ops = &clk_regmap_gate_ops,	1985	.ops = &clk_regmap_gate_ops,
1803	.parent_names = (const char *[]){ "vclk" },	1986	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1804	.num_parents = 1,	1987	.num_parents = 1,
1805	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	1988	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1806	},	1989	},
@@ -1814,7 +1997,7 @@ static struct clk_regmap gxbb_vclk_div6_en = { · 7 unmodified lines
1814	.hw.init = &(struct clk_init_data) {	1997	.hw.init = &(struct clk_init_data) {
1815	.name = "vclk_div6_en",	1998	.name = "vclk_div6_en",
1816	.ops = &clk_regmap_gate_ops,	1999	.ops = &clk_regmap_gate_ops,
1817	.parent_names = (const char *[]){ "vclk" },	2000	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1818	.num_parents = 1,	2001	.num_parents = 1,
1819	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2002	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1820	},	2003	},
@@ -1828,7 +2011,7 @@ static struct clk_regmap gxbb_vclk_div12_en = { · 7 unmodified lines
1828	.hw.init = &(struct clk_init_data) {	2011	.hw.init = &(struct clk_init_data) {
1829	.name = "vclk_div12_en",	2012	.name = "vclk_div12_en",
1830	.ops = &clk_regmap_gate_ops,	2013	.ops = &clk_regmap_gate_ops,
1831	.parent_names = (const char *[]){ "vclk" },	2014	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1832	.num_parents = 1,	2015	.num_parents = 1,
1833	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2016	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1834	},	2017	},
@@ -1842,7 +2025,7 @@ static struct clk_regmap gxbb_vclk2_div1 = { · 7 unmodified lines
1842	.hw.init = &(struct clk_init_data) {	2025	.hw.init = &(struct clk_init_data) {
1843	.name = "vclk2_div1",	2026	.name = "vclk2_div1",
1844	.ops = &clk_regmap_gate_ops,	2027	.ops = &clk_regmap_gate_ops,
1845	.parent_names = (const char *[]){ "vclk2" },	2028	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1846	.num_parents = 1,	2029	.num_parents = 1,
1847	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2030	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1848	},	2031	},
@@ -1856,7 +2039,7 @@ static struct clk_regmap gxbb_vclk2_div2_en = { · 7 unmodified lines
1856	.hw.init = &(struct clk_init_data) {	2039	.hw.init = &(struct clk_init_data) {
1857	.name = "vclk2_div2_en",	2040	.name = "vclk2_div2_en",
1858	.ops = &clk_regmap_gate_ops,	2041	.ops = &clk_regmap_gate_ops,
1859	.parent_names = (const char *[]){ "vclk2" },	2042	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1860	.num_parents = 1,	2043	.num_parents = 1,
1861	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2044	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1862	},	2045	},
@@ -1870,7 +2053,7 @@ static struct clk_regmap gxbb_vclk2_div4_en = { · 7 unmodified lines
1870	.hw.init = &(struct clk_init_data) {	2053	.hw.init = &(struct clk_init_data) {
1871	.name = "vclk2_div4_en",	2054	.name = "vclk2_div4_en",
1872	.ops = &clk_regmap_gate_ops,	2055	.ops = &clk_regmap_gate_ops,
1873	.parent_names = (const char *[]){ "vclk2" },	2056	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1874	.num_parents = 1,	2057	.num_parents = 1,
1875	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2058	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1876	},	2059	},
@@ -1884,7 +2067,7 @@ static struct clk_regmap gxbb_vclk2_div6_en = { · 7 unmodified lines
1884	.hw.init = &(struct clk_init_data) {	2067	.hw.init = &(struct clk_init_data) {
1885	.name = "vclk2_div6_en",	2068	.name = "vclk2_div6_en",
1886	.ops = &clk_regmap_gate_ops,	2069	.ops = &clk_regmap_gate_ops,
1887	.parent_names = (const char *[]){ "vclk2" },	2070	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1888	.num_parents = 1,	2071	.num_parents = 1,
1889	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2072	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1890	},	2073	},
@@ -1898,7 +2081,7 @@ static struct clk_regmap gxbb_vclk2_div12_en = { · 7 unmodified lines
1898	.hw.init = &(struct clk_init_data) {	2081	.hw.init = &(struct clk_init_data) {
1899	.name = "vclk2_div12_en",	2082	.name = "vclk2_div12_en",
1900	.ops = &clk_regmap_gate_ops,	2083	.ops = &clk_regmap_gate_ops,
1901	.parent_names = (const char *[]){ "vclk2" },	2084	.parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1902	.num_parents = 1,	2085	.num_parents = 1,
1903	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2086	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1904	},	2087	},
@@ -1910,7 +2093,9 @@ static struct clk_fixed_factor gxbb_vclk_div2 = { · 5 unmodified lines
1910	.hw.init = &(struct clk_init_data){	2093	.hw.init = &(struct clk_init_data){
1911	.name = "vclk_div2",	2094	.name = "vclk_div2",
1912	.ops = &clk_fixed_factor_ops,	2095	.ops = &clk_fixed_factor_ops,
1913	.parent_names = (const char *[]){ "vclk_div2_en" },	2096	.parent_hws = (const struct clk_hw *[]) {
		2097	&gxbb_vclk_div2_en.hw
		2098	},
1914	.num_parents = 1,	2099	.num_parents = 1,
1915	},	2100	},
1916	};	2101	};
@@ -1921,7 +2106,9 @@ static struct clk_fixed_factor gxbb_vclk_div4 = { · 4 unmodified lines
1921	.hw.init = &(struct clk_init_data){	2106	.hw.init = &(struct clk_init_data){
1922	.name = "vclk_div4",	2107	.name = "vclk_div4",
1923	.ops = &clk_fixed_factor_ops,	2108	.ops = &clk_fixed_factor_ops,
1924	.parent_names = (const char *[]){ "vclk_div4_en" },	2109	.parent_hws = (const struct clk_hw *[]) {
		2110	&gxbb_vclk_div4_en.hw
		2111	},
1925	.num_parents = 1,	2112	.num_parents = 1,
1926	},	2113	},
1927	};	2114	};
@@ -1932,7 +2119,9 @@ static struct clk_fixed_factor gxbb_vclk_div6 = { · 4 unmodified lines
1932	.hw.init = &(struct clk_init_data){	2119	.hw.init = &(struct clk_init_data){
1933	.name = "vclk_div6",	2120	.name = "vclk_div6",
1934	.ops = &clk_fixed_factor_ops,	2121	.ops = &clk_fixed_factor_ops,
1935	.parent_names = (const char *[]){ "vclk_div6_en" },	2122	.parent_hws = (const struct clk_hw *[]) {
		2123	&gxbb_vclk_div6_en.hw
		2124	},
1936	.num_parents = 1,	2125	.num_parents = 1,
1937	},	2126	},
1938	};	2127	};
@@ -1943,7 +2132,9 @@ static struct clk_fixed_factor gxbb_vclk_div12 = { · 4 unmodified lines
1943	.hw.init = &(struct clk_init_data){	2132	.hw.init = &(struct clk_init_data){
1944	.name = "vclk_div12",	2133	.name = "vclk_div12",
1945	.ops = &clk_fixed_factor_ops,	2134	.ops = &clk_fixed_factor_ops,
1946	.parent_names = (const char *[]){ "vclk_div12_en" },	2135	.parent_hws = (const struct clk_hw *[]) {
		2136	&gxbb_vclk_div12_en.hw
		2137	},
1947	.num_parents = 1,	2138	.num_parents = 1,
1948	},	2139	},
1949	};	2140	};
@@ -1954,7 +2145,9 @@ static struct clk_fixed_factor gxbb_vclk2_div2 = { · 4 unmodified lines
1954	.hw.init = &(struct clk_init_data){	2145	.hw.init = &(struct clk_init_data){
1955	.name = "vclk2_div2",	2146	.name = "vclk2_div2",
1956	.ops = &clk_fixed_factor_ops,	2147	.ops = &clk_fixed_factor_ops,
1957	.parent_names = (const char *[]){ "vclk2_div2_en" },	2148	.parent_hws = (const struct clk_hw *[]) {
		2149	&gxbb_vclk2_div2_en.hw
		2150	},
1958	.num_parents = 1,	2151	.num_parents = 1,
1959	},	2152	},
1960	};	2153	};
@@ -1965,7 +2158,9 @@ static struct clk_fixed_factor gxbb_vclk2_div4 = { · 4 unmodified lines
1965	.hw.init = &(struct clk_init_data){	2158	.hw.init = &(struct clk_init_data){
1966	.name = "vclk2_div4",	2159	.name = "vclk2_div4",
1967	.ops = &clk_fixed_factor_ops,	2160	.ops = &clk_fixed_factor_ops,
1968	.parent_names = (const char *[]){ "vclk2_div4_en" },	2161	.parent_hws = (const struct clk_hw *[]) {
		2162	&gxbb_vclk2_div4_en.hw
		2163	},
1969	.num_parents = 1,	2164	.num_parents = 1,
1970	},	2165	},
1971	};	2166	};
@@ -1976,7 +2171,9 @@ static struct clk_fixed_factor gxbb_vclk2_div6 = { · 4 unmodified lines
1976	.hw.init = &(struct clk_init_data){	2171	.hw.init = &(struct clk_init_data){
1977	.name = "vclk2_div6",	2172	.name = "vclk2_div6",
1978	.ops = &clk_fixed_factor_ops,	2173	.ops = &clk_fixed_factor_ops,
1979	.parent_names = (const char *[]){ "vclk2_div6_en" },	2174	.parent_hws = (const struct clk_hw *[]) {
		2175	&gxbb_vclk2_div6_en.hw
		2176	},
1980	.num_parents = 1,	2177	.num_parents = 1,
1981	},	2178	},
1982	};	2179	};
@@ -1987,16 +2184,25 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = { · 4 unmodified lines
1987	.hw.init = &(struct clk_init_data){	2184	.hw.init = &(struct clk_init_data){
1988	.name = "vclk2_div12",	2185	.name = "vclk2_div12",
1989	.ops = &clk_fixed_factor_ops,	2186	.ops = &clk_fixed_factor_ops,
1990	.parent_names = (const char *[]){ "vclk2_div12_en" },	2187	.parent_hws = (const struct clk_hw *[]) {
		2188	&gxbb_vclk2_div12_en.hw
		2189	},
1991	.num_parents = 1,	2190	.num_parents = 1,
1992	},	2191	},
1993	};	2192	};
1994		2193
1995	static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };	2194	static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1996	static const char * const gxbb_cts_parent_names[] = {	2195	static const struct clk_hw *gxbb_cts_parent_hws[] = {
1997	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",	2196	&gxbb_vclk_div1.hw,
1998	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",	2197	&gxbb_vclk_div2.hw,
1999	"vclk2_div6", "vclk2_div12"	2198	&gxbb_vclk_div4.hw,
		2199	&gxbb_vclk_div6.hw,
		2200	&gxbb_vclk_div12.hw,
		2201	&gxbb_vclk2_div1.hw,
		2202	&gxbb_vclk2_div2.hw,
		2203	&gxbb_vclk2_div4.hw,
		2204	&gxbb_vclk2_div6.hw,
		2205	&gxbb_vclk2_div12.hw,
2000	};	2206	};
2001		2207
2002	static struct clk_regmap gxbb_cts_enci_sel = {	2208	static struct clk_regmap gxbb_cts_enci_sel = {
@@ -2009,8 +2215,8 @@ static struct clk_regmap gxbb_cts_enci_sel = { · 6 unmodified lines
2009	.hw.init = &(struct clk_init_data){	2215	.hw.init = &(struct clk_init_data){
2010	.name = "cts_enci_sel",	2216	.name = "cts_enci_sel",
2011	.ops = &clk_regmap_mux_ops,	2217	.ops = &clk_regmap_mux_ops,
2012	.parent_names = gxbb_cts_parent_names,	2218	.parent_hws = gxbb_cts_parent_hws,
2013	.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),	2219	.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2014	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	2220	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2015	},	2221	},
2016	};	2222	};
@@ -2025,8 +2231,8 @@ static struct clk_regmap gxbb_cts_encp_sel = { · 8 unmodified lines
2025	.hw.init = &(struct clk_init_data){	2231	.hw.init = &(struct clk_init_data){
2026	.name = "cts_encp_sel",	2232	.name = "cts_encp_sel",
2027	.ops = &clk_regmap_mux_ops,	2233	.ops = &clk_regmap_mux_ops,
2028	.parent_names = gxbb_cts_parent_names,	2234	.parent_hws = gxbb_cts_parent_hws,
2029	.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),	2235	.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2030	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	2236	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2031	},	2237	},
2032	};	2238	};
@@ -2041,18 +2247,25 @@ static struct clk_regmap gxbb_cts_vdac_sel = { · 8 unmodified lines
2041	.hw.init = &(struct clk_init_data){	2247	.hw.init = &(struct clk_init_data){
2042	.name = "cts_vdac_sel",	2248	.name = "cts_vdac_sel",
2043	.ops = &clk_regmap_mux_ops,	2249	.ops = &clk_regmap_mux_ops,
2044	.parent_names = gxbb_cts_parent_names,	2250	.parent_hws = gxbb_cts_parent_hws,
2045	.num_parents = ARRAY_SIZE(gxbb_cts_parent_names),	2251	.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2046	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	2252	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2047	},	2253	},
2048	};	2254	};
2049		2255
2050	/* TOFIX: add support for cts_tcon */	2256	/* TOFIX: add support for cts_tcon */
2051	static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };	2257	static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2052	static const char * const gxbb_cts_hdmi_tx_parent_names[] = {	2258	static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2053	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",	2259	&gxbb_vclk_div1.hw,
2054	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",	2260	&gxbb_vclk_div2.hw,
2055	"vclk2_div6", "vclk2_div12"	2261	&gxbb_vclk_div4.hw,
		2262	&gxbb_vclk_div6.hw,
		2263	&gxbb_vclk_div12.hw,
		2264	&gxbb_vclk2_div1.hw,
		2265	&gxbb_vclk2_div2.hw,
		2266	&gxbb_vclk2_div4.hw,
		2267	&gxbb_vclk2_div6.hw,
		2268	&gxbb_vclk2_div12.hw,
2056	};	2269	};
2057		2270
2058	static struct clk_regmap gxbb_hdmi_tx_sel = {	2271	static struct clk_regmap gxbb_hdmi_tx_sel = {
@@ -2071,8 +2284,8 @@ static struct clk_regmap gxbb_hdmi_tx_sel = { · 12 unmodified lines
2071	* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,	2284	* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2072	* cts_tcon	2285	* cts_tcon
2073	*/	2286	*/
2074	.parent_names = gxbb_cts_hdmi_tx_parent_names,	2287	.parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2075	.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names),	2288	.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2076	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	2289	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2077	},	2290	},
2078	};	2291	};
@@ -2085,7 +2298,9 @@ static struct clk_regmap gxbb_cts_enci = { · 6 unmodified lines
2085	.hw.init = &(struct clk_init_data) {	2298	.hw.init = &(struct clk_init_data) {
2086	.name = "cts_enci",	2299	.name = "cts_enci",
2087	.ops = &clk_regmap_gate_ops,	2300	.ops = &clk_regmap_gate_ops,
2088	.parent_names = (const char *[]){ "cts_enci_sel" },	2301	.parent_hws = (const struct clk_hw *[]) {
		2302	&gxbb_cts_enci_sel.hw
		2303	},
2089	.num_parents = 1,	2304	.num_parents = 1,
2090	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2305	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2091	},	2306	},
@@ -2099,7 +2314,9 @@ static struct clk_regmap gxbb_cts_encp = { · 7 unmodified lines
2099	.hw.init = &(struct clk_init_data) {	2314	.hw.init = &(struct clk_init_data) {
2100	.name = "cts_encp",	2315	.name = "cts_encp",
2101	.ops = &clk_regmap_gate_ops,	2316	.ops = &clk_regmap_gate_ops,
2102	.parent_names = (const char *[]){ "cts_encp_sel" },	2317	.parent_hws = (const struct clk_hw *[]) {
		2318	&gxbb_cts_encp_sel.hw
		2319	},
2103	.num_parents = 1,	2320	.num_parents = 1,
2104	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2321	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2105	},	2322	},
@@ -2113,7 +2330,9 @@ static struct clk_regmap gxbb_cts_vdac = { · 7 unmodified lines
2113	.hw.init = &(struct clk_init_data) {	2330	.hw.init = &(struct clk_init_data) {
2114	.name = "cts_vdac",	2331	.name = "cts_vdac",
2115	.ops = &clk_regmap_gate_ops,	2332	.ops = &clk_regmap_gate_ops,
2116	.parent_names = (const char *[]){ "cts_vdac_sel" },	2333	.parent_hws = (const struct clk_hw *[]) {
		2334	&gxbb_cts_vdac_sel.hw
		2335	},
2117	.num_parents = 1,	2336	.num_parents = 1,
2118	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2337	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2119	},	2338	},
@@ -2127,7 +2346,9 @@ static struct clk_regmap gxbb_hdmi_tx = { · 7 unmodified lines
2127	.hw.init = &(struct clk_init_data) {	2346	.hw.init = &(struct clk_init_data) {
2128	.name = "hdmi_tx",	2347	.name = "hdmi_tx",
2129	.ops = &clk_regmap_gate_ops,	2348	.ops = &clk_regmap_gate_ops,
2130	.parent_names = (const char *[]){ "hdmi_tx_sel" },	2349	.parent_hws = (const struct clk_hw *[]) {
		2350	&gxbb_hdmi_tx_sel.hw
		2351	},
2131	.num_parents = 1,	2352	.num_parents = 1,
2132	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2353	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2133	},	2354	},
@@ -2135,8 +2356,11 @@ static struct clk_regmap gxbb_hdmi_tx = { · 1 unmodified line
2135		2356
2136	/* HDMI Clocks */	2357	/* HDMI Clocks */
2137		2358
2138	static const char * const gxbb_hdmi_parent_names[] = {	2359	static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2139	IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"	2360	{ .fw_name = "xtal", },
		2361	{ .hw = &gxbb_fclk_div4.hw },
		2362	{ .hw = &gxbb_fclk_div3.hw },
		2363	{ .hw = &gxbb_fclk_div5.hw },
2140	};	2364	};
2141		2365
2142	static struct clk_regmap gxbb_hdmi_sel = {	2366	static struct clk_regmap gxbb_hdmi_sel = {
@@ -2149,8 +2373,8 @@ static struct clk_regmap gxbb_hdmi_sel = { · 6 unmodified lines
2149	.hw.init = &(struct clk_init_data){	2373	.hw.init = &(struct clk_init_data){
2150	.name = "hdmi_sel",	2374	.name = "hdmi_sel",
2151	.ops = &clk_regmap_mux_ops,	2375	.ops = &clk_regmap_mux_ops,
2152	.parent_names = gxbb_hdmi_parent_names,	2376	.parent_data = gxbb_hdmi_parent_data,
2153	.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names),	2377	.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2154	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,	2378	.flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
2155	},	2379	},
2156	};	2380	};
@@ -2164,7 +2388,7 @@ static struct clk_regmap gxbb_hdmi_div = { · 7 unmodified lines
2164	.hw.init = &(struct clk_init_data){	2388	.hw.init = &(struct clk_init_data){
2165	.name = "hdmi_div",	2389	.name = "hdmi_div",
2166	.ops = &clk_regmap_divider_ops,	2390	.ops = &clk_regmap_divider_ops,
2167	.parent_names = (const char *[]){ "hdmi_sel" },	2391	.parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2168	.num_parents = 1,	2392	.num_parents = 1,
2169	.flags = CLK_GET_RATE_NOCACHE,	2393	.flags = CLK_GET_RATE_NOCACHE,
2170	},	2394	},
@@ -2178,7 +2402,7 @@ static struct clk_regmap gxbb_hdmi = { · 7 unmodified lines
2178	.hw.init = &(struct clk_init_data) {	2402	.hw.init = &(struct clk_init_data) {
2179	.name = "hdmi",	2403	.name = "hdmi",
2180	.ops = &clk_regmap_gate_ops,	2404	.ops = &clk_regmap_gate_ops,
2181	.parent_names = (const char *[]){ "hdmi_div" },	2405	.parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2182	.num_parents = 1,	2406	.num_parents = 1,
2183	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,	2407	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
2184	},	2408	},
@@ -2186,8 +2410,11 @@ static struct clk_regmap gxbb_hdmi = { · 1 unmodified line
2186		2410
2187	/* VDEC clocks */	2411	/* VDEC clocks */
2188		2412
2189	static const char * const gxbb_vdec_parent_names[] = {	2413	static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2190	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"	2414	&gxbb_fclk_div4.hw,
		2415	&gxbb_fclk_div3.hw,
		2416	&gxbb_fclk_div5.hw,
		2417	&gxbb_fclk_div7.hw,
2191	};	2418	};
2192		2419
2193	static struct clk_regmap gxbb_vdec_1_sel = {	2420	static struct clk_regmap gxbb_vdec_1_sel = {
@@ -2200,8 +2427,8 @@ static struct clk_regmap gxbb_vdec_1_sel = { · 6 unmodified lines
2200	.hw.init = &(struct clk_init_data){	2427	.hw.init = &(struct clk_init_data){
2201	.name = "vdec_1_sel",	2428	.name = "vdec_1_sel",
2202	.ops = &clk_regmap_mux_ops,	2429	.ops = &clk_regmap_mux_ops,
2203	.parent_names = gxbb_vdec_parent_names,	2430	.parent_hws = gxbb_vdec_parent_hws,
2204	.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),	2431	.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2205	.flags = CLK_SET_RATE_PARENT,	2432	.flags = CLK_SET_RATE_PARENT,
2206	},	2433	},
2207	};	2434	};
@@ -2216,7 +2443,9 @@ static struct clk_regmap gxbb_vdec_1_div = { · 8 unmodified lines
2216	.hw.init = &(struct clk_init_data){	2443	.hw.init = &(struct clk_init_data){
2217	.name = "vdec_1_div",	2444	.name = "vdec_1_div",
2218	.ops = &clk_regmap_divider_ops,	2445	.ops = &clk_regmap_divider_ops,
2219	.parent_names = (const char *[]){ "vdec_1_sel" },	2446	.parent_hws = (const struct clk_hw *[]) {
		2447	&gxbb_vdec_1_sel.hw
		2448	},
2220	.num_parents = 1,	2449	.num_parents = 1,
2221	.flags = CLK_SET_RATE_PARENT,	2450	.flags = CLK_SET_RATE_PARENT,
2222	},	2451	},
@@ -2230,7 +2459,9 @@ static struct clk_regmap gxbb_vdec_1 = { · 7 unmodified lines
2230	.hw.init = &(struct clk_init_data) {	2459	.hw.init = &(struct clk_init_data) {
2231	.name = "vdec_1",	2460	.name = "vdec_1",
2232	.ops = &clk_regmap_gate_ops,	2461	.ops = &clk_regmap_gate_ops,
2233	.parent_names = (const char *[]){ "vdec_1_div" },	2462	.parent_hws = (const struct clk_hw *[]) {
		2463	&gxbb_vdec_1_div.hw
		2464	},
2234	.num_parents = 1,	2465	.num_parents = 1,
2235	.flags = CLK_SET_RATE_PARENT,	2466	.flags = CLK_SET_RATE_PARENT,
2236	},	2467	},
@@ -2246,8 +2477,8 @@ static struct clk_regmap gxbb_vdec_hevc_sel = { · 9 unmodified lines
2246	.hw.init = &(struct clk_init_data){	2477	.hw.init = &(struct clk_init_data){
2247	.name = "vdec_hevc_sel",	2478	.name = "vdec_hevc_sel",
2248	.ops = &clk_regmap_mux_ops,	2479	.ops = &clk_regmap_mux_ops,
2249	.parent_names = gxbb_vdec_parent_names,	2480	.parent_hws = gxbb_vdec_parent_hws,
2250	.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),	2481	.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2251	.flags = CLK_SET_RATE_PARENT,	2482	.flags = CLK_SET_RATE_PARENT,
2252	},	2483	},
2253	};	2484	};
@@ -2262,7 +2493,9 @@ static struct clk_regmap gxbb_vdec_hevc_div = { · 8 unmodified lines
2262	.hw.init = &(struct clk_init_data){	2493	.hw.init = &(struct clk_init_data){
2263	.name = "vdec_hevc_div",	2494	.name = "vdec_hevc_div",
2264	.ops = &clk_regmap_divider_ops,	2495	.ops = &clk_regmap_divider_ops,
2265	.parent_names = (const char *[]){ "vdec_hevc_sel" },	2496	.parent_hws = (const struct clk_hw *[]) {
		2497	&gxbb_vdec_hevc_sel.hw
		2498	},
2266	.num_parents = 1,	2499	.num_parents = 1,
2267	.flags = CLK_SET_RATE_PARENT,	2500	.flags = CLK_SET_RATE_PARENT,
2268	},	2501	},
@@ -2276,7 +2509,9 @@ static struct clk_regmap gxbb_vdec_hevc = { · 7 unmodified lines
2276	.hw.init = &(struct clk_init_data) {	2509	.hw.init = &(struct clk_init_data) {
2277	.name = "vdec_hevc",	2510	.name = "vdec_hevc",
2278	.ops = &clk_regmap_gate_ops,	2511	.ops = &clk_regmap_gate_ops,
2279	.parent_names = (const char *[]){ "vdec_hevc_div" },	2512	.parent_hws = (const struct clk_hw *[]) {
		2513	&gxbb_vdec_hevc_div.hw
		2514	},
2280	.num_parents = 1,	2515	.num_parents = 1,
2281	.flags = CLK_SET_RATE_PARENT,	2516	.flags = CLK_SET_RATE_PARENT,
2282	},	2517	},
@@ -2284,9 +2519,18 @@ static struct clk_regmap gxbb_vdec_hevc = { · 1 unmodified line
2284		2519
2285	static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,	2520	static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
2286	9, 10, 11, 13, 14, };	2521	9, 10, 11, 13, 14, };
2287	static const char * const gen_clk_parent_names[] = {	2522	static const struct clk_parent_data gen_clk_parent_data[] = {
2288	IN_PREFIX "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",	2523	{ .fw_name = "xtal", },
2289	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",	2524	{ .hw = &gxbb_vdec_1.hw },
		2525	{ .hw = &gxbb_vdec_hevc.hw },
		2526	{ .hw = &gxbb_mpll0.hw },
		2527	{ .hw = &gxbb_mpll1.hw },
		2528	{ .hw = &gxbb_mpll2.hw },
		2529	{ .hw = &gxbb_fclk_div4.hw },
		2530	{ .hw = &gxbb_fclk_div3.hw },
		2531	{ .hw = &gxbb_fclk_div5.hw },
		2532	{ .hw = &gxbb_fclk_div7.hw },
		2533	{ .hw = &gxbb_gp0_pll.hw },
2290	};	2534	};
2291		2535
2292	static struct clk_regmap gxbb_gen_clk_sel = {	2536	static struct clk_regmap gxbb_gen_clk_sel = {
@@ -2305,8 +2549,8 @@ static struct clk_regmap gxbb_gen_clk_sel = { · 12 unmodified lines
2305	* vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,	2549	* vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2306	* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll	2550	* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2307	*/	2551	*/
2308	.parent_names = gen_clk_parent_names,	2552	.parent_data = gen_clk_parent_data,
2309	.num_parents = ARRAY_SIZE(gen_clk_parent_names),	2553	.num_parents = ARRAY_SIZE(gen_clk_parent_data),
2310	},	2554	},
2311	};	2555	};
2312		2556
@@ -2319,7 +2563,9 @@ static struct clk_regmap gxbb_gen_clk_div = { · 6 unmodified lines
2319	.hw.init = &(struct clk_init_data){	2563	.hw.init = &(struct clk_init_data){
2320	.name = "gen_clk_div",	2564	.name = "gen_clk_div",
2321	.ops = &clk_regmap_divider_ops,	2565	.ops = &clk_regmap_divider_ops,
2322	.parent_names = (const char *[]){ "gen_clk_sel" },	2566	.parent_hws = (const struct clk_hw *[]) {
		2567	&gxbb_gen_clk_sel.hw
		2568	},
2323	.num_parents = 1,	2569	.num_parents = 1,
2324	.flags = CLK_SET_RATE_PARENT,	2570	.flags = CLK_SET_RATE_PARENT,
2325	},	2571	},
@@ -2333,12 +2579,17 @@ static struct clk_regmap gxbb_gen_clk = { · 7 unmodified lines
2333	.hw.init = &(struct clk_init_data){	2579	.hw.init = &(struct clk_init_data){
2334	.name = "gen_clk",	2580	.name = "gen_clk",
2335	.ops = &clk_regmap_gate_ops,	2581	.ops = &clk_regmap_gate_ops,
2336	.parent_names = (const char *[]){ "gen_clk_div" },	2582	.parent_hws = (const struct clk_hw *[]) {
		2583	&gxbb_gen_clk_div.hw
		2584	},
2337	.num_parents = 1,	2585	.num_parents = 1,
2338	.flags = CLK_SET_RATE_PARENT,	2586	.flags = CLK_SET_RATE_PARENT,
2339	},	2587	},
2340	};	2588	};
2341		2589
		2590	#define MESON_GATE(_name, _reg, _bit) \
		2591	MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
		2592
2342	/* Everything Else (EE) domain gates */	2593	/* Everything Else (EE) domain gates */
2343	static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);	2594	static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2344	static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);	2595	static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);

drivers/clk/meson/meson-aoclk.c+0−37

@@ -17,8 +17,6 @@ · 16 unmodified lines
17	#include <linux/slab.h>	17	#include <linux/slab.h>
18	#include "meson-aoclk.h"	18	#include "meson-aoclk.h"
19		19
20	#include "clk-input.h"
21
22	static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,	20	static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
23	unsigned long id)	21	unsigned long id)
24	{	22	{
@@ -33,37 +31,6 @@ static const struct reset_control_ops meson_aoclk_reset_ops = { · 8 unmodified lines
33	.reset = meson_aoclk_do_reset,	31	.reset = meson_aoclk_do_reset,
34	};	32	};
35		33
36	static int meson_aoclkc_register_inputs(struct device *dev,
37	struct meson_aoclk_data *data)
38	{
39	struct clk_hw *hw;
40	char *str;
41	int i;
42
43	for (i = 0; i < data->num_inputs; i++) {
44	const struct meson_aoclk_input *in = &data->inputs[i];
45
46	str = kasprintf(GFP_KERNEL, "%s%s", data->input_prefix,
47	in->name);
48	if (!str)
49	return -ENOMEM;
50
51	hw = meson_clk_hw_register_input(dev, in->name, str, 0);
52	kfree(str);
53
54	if (IS_ERR(hw)) {
55	if (!in->required && PTR_ERR(hw) == -ENOENT)
56	continue;
57	else if (PTR_ERR(hw) != -EPROBE_DEFER)
58	dev_err(dev, "failed to register input %s\n",
59	in->name);
60	return PTR_ERR(hw);
61	}
62	}
63
64	return 0;
65	}
66
67	int meson_aoclkc_probe(struct platform_device *pdev)	34	int meson_aoclkc_probe(struct platform_device *pdev)
68	{	35	{
69	struct meson_aoclk_reset_controller *rstc;	36	struct meson_aoclk_reset_controller *rstc;
@@ -86,10 +53,6 @@ int meson_aoclkc_probe(struct platform_device *pdev) · 16 unmodified lines
86	return PTR_ERR(regmap);	53	return PTR_ERR(regmap);
87	}	54	}
88		55
89	ret = meson_aoclkc_register_inputs(dev, data);
90	if (ret)
91	return ret;
92
93	/* Reset Controller */	56	/* Reset Controller */
94	rstc->data = data;	57	rstc->data = data;
95	rstc->regmap = regmap;	58	rstc->regmap = regmap;

drivers/clk/meson/meson-aoclk.h+0−8

 #include "clk-regmap.h"
-struct meson_aoclk_input {
-	const char *name;
-	bool required;
-};
 struct meson_aoclk_data {
 	const unsigned int			reset_reg;
 	const int				num_reset;
 	const unsigned int			*reset;
 	const int				num_clks;
 	struct clk_regmap			**clks;
-	const int				num_inputs;
-	const struct meson_aoclk_input		*inputs;
-	const char				*input_prefix;
 	const struct clk_hw_onecell_data	*hw_data;
 };

drivers/clk/meson/meson-eeclk.c+0−10

 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
-#include "clk-input.h"
 #include "clk-regmap.h"
 #include "meson-eeclk.h"
 {
 	const struct meson_eeclkc_data *data;
 	struct device *dev = &pdev->dev;
-	struct clk_hw *input;
 	struct regmap *map;
 	int ret, i;
 	if (data->init_count)
 		regmap_multi_reg_write(map, data->init_regs, data->init_count);
-	input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
-	if (IS_ERR(input)) {
-		ret = PTR_ERR(input);
-		if (ret != -EPROBE_DEFER)
-			dev_err(dev, "failed to get input clock");
-		return ret;
-	}
 	/* Populate regmap for the regmap backed clocks */
 	for (i = 0; i < data->regmap_clk_num; i++)
 		data->regmap_clks[i]->map = map;

drivers/clk/meson/meson-eeclk.h+0−2

@@ -10,8 +10,6 @@ · 9 unmodified lines
10	#include <linux/clk-provider.h>	10	#include <linux/clk-provider.h>
11	#include "clk-regmap.h"	11	#include "clk-regmap.h"
12		12
13	#define IN_PREFIX "ee-in-"
14
15	struct platform_device;	13	struct platform_device;
16		14
17	struct meson_eeclkc_data {	15	struct meson_eeclkc_data {

drivers/clk/meson/meson8b.c+499−211

 	.hw.init = &(struct clk_init_data){
 		.name = "fixed_pll_dco",
 		.ops = &meson_clk_pll_ro_ops,
-		.parent_names = (const char *[]){ "xtal" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_xtal.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fixed_pll",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "fixed_pll_dco" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fixed_pll_dco.hw
+		},
 		.num_parents = 1,
 		/*
 		 * This clock won't ever change at runtime so
 		/* sometimes also called "HPLL" or "HPLL PLL" */
 		.name = "hdmi_pll_dco",
 		.ops = &meson_clk_pll_ro_ops,
-		.parent_names = (const char *[]){ "xtal" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_xtal.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll_lvds_out",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "hdmi_pll_dco" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_hdmi_pll_dco.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll_hdmi_out",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "hdmi_pll_dco" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_hdmi_pll_dco.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "sys_pll_dco",
 		.ops = &meson_clk_pll_ops,
-		.parent_names = (const char *[]){ "xtal" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_xtal.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "sys_pll",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "sys_pll_dco" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_sys_pll_dco.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div2_div",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "fixed_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fixed_pll.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div2",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "fclk_div2_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fclk_div2_div.hw
+		},
 		.num_parents = 1,
 		/*
 		 * FIXME: Ethernet with a RGMII PHYs is not working if
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div3_div",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "fixed_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fixed_pll.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div3",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "fclk_div3_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fclk_div3_div.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div4_div",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "fixed_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fixed_pll.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div4",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "fclk_div4_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fclk_div4_div.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div5_div",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "fixed_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fixed_pll.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div5",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "fclk_div5_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fclk_div5_div.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div7_div",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "fixed_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fixed_pll.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div7",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "fclk_div7_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fclk_div7_div.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll_prediv",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "fixed_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_fixed_pll.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0_div",
 		.ops = &meson_clk_mpll_ops,
-		.parent_names = (const char *[]){ "mpll_prediv" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpll_prediv.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "mpll0_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpll0_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1_div",
 		.ops = &meson_clk_mpll_ops,
-		.parent_names = (const char *[]){ "mpll_prediv" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpll_prediv.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "mpll1_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpll1_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2_div",
 		.ops = &meson_clk_mpll_ops,
-		.parent_names = (const char *[]){ "mpll_prediv" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpll_prediv.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "mpll2_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpll2_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 		 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 		 * fclk_div4, fclk_div3, fclk_div5
 		 */
-		.parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
+		.parent_hws = (const struct clk_hw *[]) {
-			"fclk_div5" },
+			&meson8b_fclk_div3.hw,
+			&meson8b_fclk_div4.hw,
+			&meson8b_fclk_div5.hw,
+		},
 		.num_parents = 3,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "mpeg_clk_div",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "mpeg_clk_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpeg_clk_sel.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "clk81",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "mpeg_clk_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mpeg_clk_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_IS_CRITICAL,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_in_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "xtal", "sys_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_xtal.hw,
+			&meson8b_sys_pll.hw,
+		},
 		.num_parents = 2,
 		.flags = (CLK_SET_RATE_PARENT |
 			  CLK_SET_RATE_NO_REPARENT),
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_in_div2",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_in_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_in_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_in_div3",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_in_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_in_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_scale_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "cpu_in_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_in_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 		.ops = &clk_regmap_mux_ops,
 		/*
 		 * NOTE: We are skipping the parent with value 0x2 (which is
-		 * "cpu_in_div3") because it results in a duty cycle of 33%
+		 * meson8b_cpu_in_div3) because it results in a duty cycle of
-		 * which makes the system unstable and can result in a lockup
+		 * 33% which makes the system unstable and can result in a
-		 * of the whole system.
+		 * lockup of the whole system.
 		 */
-		.parent_names = (const char *[]) { "cpu_in_sel",
+		.parent_hws = (const struct clk_hw *[]) {
-						   "cpu_in_div2",
+			&meson8b_cpu_in_sel.hw,
-						   "cpu_scale_div" },
+			&meson8b_cpu_in_div2.hw,
+			&meson8b_cpu_scale_div.hw,
+		},
 		.num_parents = 3,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "xtal",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "cpu_scale_out_sel" },
+			&meson8b_xtal.hw,
+			&meson8b_cpu_scale_out_sel.hw,
+		},
 		.num_parents = 2,
 		.flags = (CLK_SET_RATE_PARENT |
 			  CLK_SET_RATE_NO_REPARENT |
 		.name = "nand_clk_sel",
 		.ops = &clk_regmap_mux_ops,
 		/* FIXME all other parents are unknown: */
-		.parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
+		.parent_hws = (const struct clk_hw *[]) {
-			"fclk_div5", "fclk_div7", "xtal" },
+			&meson8b_fclk_div4.hw,
+			&meson8b_fclk_div3.hw,
+			&meson8b_fclk_div5.hw,
+			&meson8b_fclk_div7.hw,
+			&meson8b_xtal.hw,
+		},
 		.num_parents = 5,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "nand_clk_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "nand_clk_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_nand_clk_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "nand_clk_gate",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "nand_clk_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_nand_clk_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_div2",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_clk" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_clk.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_div3",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_clk" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_clk.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_div4",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_clk" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_clk.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_div5",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_clk" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_clk.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_div6",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_clk" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_clk.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_div7",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_clk" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_clk.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk_div8",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "cpu_clk" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cpu_clk.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "apb_clk_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "cpu_clk_div2",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "cpu_clk_div3",
+			&meson8b_cpu_clk_div2.hw,
-						  "cpu_clk_div4",
+			&meson8b_cpu_clk_div3.hw,
-						  "cpu_clk_div5",
+			&meson8b_cpu_clk_div4.hw,
-						  "cpu_clk_div6",
+			&meson8b_cpu_clk_div5.hw,
-						  "cpu_clk_div7",
+			&meson8b_cpu_clk_div6.hw,
-						  "cpu_clk_div8", },
+			&meson8b_cpu_clk_div7.hw,
+			&meson8b_cpu_clk_div8.hw,
+		},
 		.num_parents = 7,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "apb_clk_dis",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "apb_clk_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_apb_clk_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "periph_clk_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "cpu_clk_div2",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "cpu_clk_div3",
+			&meson8b_cpu_clk_div2.hw,
-						  "cpu_clk_div4",
+			&meson8b_cpu_clk_div3.hw,
-						  "cpu_clk_div5",
+			&meson8b_cpu_clk_div4.hw,
-						  "cpu_clk_div6",
+			&meson8b_cpu_clk_div5.hw,
-						  "cpu_clk_div7",
+			&meson8b_cpu_clk_div6.hw,
-						  "cpu_clk_div8", },
+			&meson8b_cpu_clk_div7.hw,
+			&meson8b_cpu_clk_div8.hw,
+		},
 		.num_parents = 7,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "periph_clk_dis",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "periph_clk_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_periph_clk_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "axi_clk_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "cpu_clk_div2",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "cpu_clk_div3",
+			&meson8b_cpu_clk_div2.hw,
-						  "cpu_clk_div4",
+			&meson8b_cpu_clk_div3.hw,
-						  "cpu_clk_div5",
+			&meson8b_cpu_clk_div4.hw,
-						  "cpu_clk_div6",
+			&meson8b_cpu_clk_div5.hw,
-						  "cpu_clk_div7",
+			&meson8b_cpu_clk_div6.hw,
-						  "cpu_clk_div8", },
+			&meson8b_cpu_clk_div7.hw,
+			&meson8b_cpu_clk_div8.hw,
+		},
 		.num_parents = 7,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "axi_clk_dis",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "axi_clk_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_axi_clk_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "l2_dram_clk_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "cpu_clk_div2",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "cpu_clk_div3",
+			&meson8b_cpu_clk_div2.hw,
-						  "cpu_clk_div4",
+			&meson8b_cpu_clk_div3.hw,
-						  "cpu_clk_div5",
+			&meson8b_cpu_clk_div4.hw,
-						  "cpu_clk_div6",
+			&meson8b_cpu_clk_div5.hw,
-						  "cpu_clk_div7",
+			&meson8b_cpu_clk_div6.hw,
-						  "cpu_clk_div8", },
+			&meson8b_cpu_clk_div7.hw,
+			&meson8b_cpu_clk_div8.hw,
+		},
 		.num_parents = 7,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "l2_dram_clk_dis",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "l2_dram_clk_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_l2_dram_clk_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 		 * Meson8b: hdmi_pll_dco
 		 * Meson8m2: vid2_pll
 		 */
-		.parent_names = (const char *[]){ "hdmi_pll_dco" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_hdmi_pll_dco.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vid_pll_in_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vid_pll_in_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vid_pll_in_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vid_pll_pre_div",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "vid_pll_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vid_pll_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vid_pll_post_div",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "vid_pll_pre_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vid_pll_pre_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 		.name = "vid_pll",
 		.ops = &clk_regmap_mux_ro_ops,
 		/* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
-		.parent_names = (const char *[]){ "vid_pll_pre_div",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "vid_pll_post_div" },
+			&meson8b_vid_pll_pre_div.hw,
+			&meson8b_vid_pll_post_div.hw,
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vid_pll_final_div",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "vid_pll" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vid_pll.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
-static const char * const meson8b_vclk_mux_parents[] = {
+static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
-	"vid_pll_final_div", "fclk_div4", "fclk_div3", "fclk_div5",
+	&meson8b_vid_pll_final_div.hw,
-	"vid_pll_final_div", "fclk_div7", "mpll1"
+	&meson8b_fclk_div4.hw,
+	&meson8b_fclk_div3.hw,
+	&meson8b_fclk_div5.hw,
+	&meson8b_vid_pll_final_div.hw,
+	&meson8b_fclk_div7.hw,
+	&meson8b_mpll1.hw,
 };
 static struct clk_regmap meson8b_vclk_in_sel = {
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_in_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk_mux_parents,
+		.parent_hws = meson8b_vclk_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_in_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk_in_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_in_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div1_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div2",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div2_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk_div2" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_div2_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div4",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div4_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk_div4" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_div4_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div6",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div6_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk_div6" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_div6_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div12",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk_div12_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk_div12" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk_div12_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_in_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk_mux_parents,
+		.parent_hws = meson8b_vclk_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_in_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk2_in_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_in_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div1_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk2_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_clk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div2",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk2_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_clk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div2_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk2_div2" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_div2_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div4",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk2_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_clk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div4_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk2_div4" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_div4_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div6",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk2_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_clk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div6_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk2_div6" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_div6_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div12",
 		.ops = &clk_fixed_factor_ops,
-		.parent_names = (const char *[]){ "vclk2_in_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_clk_in_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	}
 	.hw.init = &(struct clk_init_data){
 		.name = "vclk2_div12_en",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "vclk2_div12" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vclk2_div12_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
-static const char * const meson8b_vclk_enc_mux_parents[] = {
+static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
-	"vclk_div1_en", "vclk_div2_en", "vclk_div4_en", "vclk_div6_en",
+	&meson8b_vclk_div1_gate.hw,
-	"vclk_div12_en",
+	&meson8b_vclk_div2_div_gate.hw,
+	&meson8b_vclk_div4_div_gate.hw,
+	&meson8b_vclk_div6_div_gate.hw,
+	&meson8b_vclk_div12_div_gate.hw,
 };
 static struct clk_regmap meson8b_cts_enct_sel = {
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_enct_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk_enc_mux_parents,
+		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_enct",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "cts_enct_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_enct_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_encp_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk_enc_mux_parents,
+		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_encp",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "cts_encp_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_encp_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_enci_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk_enc_mux_parents,
+		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_enci",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "cts_enci_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_enci_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_tx_pixel_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk_enc_mux_parents,
+		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_tx_pixel",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "hdmi_tx_pixel_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_hdmi_tx_pixel_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
-static const char * const meson8b_vclk2_enc_mux_parents[] = {
+static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
-	"vclk2_div1_en", "vclk2_div2_en", "vclk2_div4_en", "vclk2_div6_en",
+	&meson8b_vclk2_div1_gate.hw,
-	"vclk2_div12_en",
+	&meson8b_vclk2_div2_div_gate.hw,
+	&meson8b_vclk2_div4_div_gate.hw,
+	&meson8b_vclk2_div6_div_gate.hw,
+	&meson8b_vclk2_div12_div_gate.hw,
 };
 static struct clk_regmap meson8b_cts_encl_sel = {
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_encl_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk2_enc_mux_parents,
+		.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_encl",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "cts_encl_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_encl_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_vdac0_sel",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = meson8b_vclk2_enc_mux_parents,
+		.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
+		.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_vdac0",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "cts_vdac0_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_vdac0_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 		.name = "hdmi_sys_sel",
 		.ops = &clk_regmap_mux_ro_ops,
 		/* FIXME: all other parents are unknown */
-		.parent_names = (const char *[]){ "xtal" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_xtal.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_NO_REPARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_sys_div",
 		.ops = &clk_regmap_divider_ro_ops,
-		.parent_names = (const char *[]){ "hdmi_sys_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_hdmi_sys_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "hdmi_sys",
 		.ops = &clk_regmap_gate_ro_ops,
-		.parent_names = (const char *[]){ "hdmi_sys_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_hdmi_sys_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
  * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
  * has mali_0 and no glitch-free mux.
  */
-static const char * const meson8b_mali_0_1_parent_names[] = {
+static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
-	"xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3",
+	&meson8b_xtal.hw,
-	"fclk_div5"
+	&meson8b_mpll2.hw,
+	&meson8b_mpll1.hw,
+	&meson8b_fclk_div7.hw,
+	&meson8b_fclk_div4.hw,
+	&meson8b_fclk_div3.hw,
+	&meson8b_fclk_div5.hw,
 };
 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
 	.hw.init = &(struct clk_init_data){
 		.name = "mali_0_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_mali_0_1_parent_names,
+		.parent_hws = meson8b_mali_0_1_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
 		/*
 		 * Don't propagate rate changes up because the only changeable
 		 * parents are mpll1 and mpll2 but we need those for audio and
 	.hw.init = &(struct clk_init_data){
 		.name = "mali_0_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "mali_0_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mali_0_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mali_0",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "mali_0_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mali_0_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mali_1_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_mali_0_1_parent_names,
+		.parent_hws = meson8b_mali_0_1_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
 		/*
 		 * Don't propagate rate changes up because the only changeable
 		 * parents are mpll1 and mpll2 but we need those for audio and
 	.hw.init = &(struct clk_init_data){
 		.name = "mali_1_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "mali_1_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mali_1_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mali_1",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "mali_1_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mali_1_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mali",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "mali_0", "mali_1" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_mali_0.hw,
+			&meson8b_mali_1.hw,
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "gp_pll_dco",
 		.ops = &meson_clk_pll_ops,
-		.parent_names = (const char *[]){ "xtal" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_xtal.hw
+		},
 		.num_parents = 1,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "gp_pll",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "gp_pll_dco" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8m2_gp_pll_dco.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
-static const char * const meson8b_vpu_0_1_parent_names[] = {
+static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
-	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+	&meson8b_fclk_div4.hw,
+	&meson8b_fclk_div3.hw,
+	&meson8b_fclk_div5.hw,
+	&meson8b_fclk_div7.hw,
 };
-static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
+static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
-	"fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
+	&meson8b_fclk_div4.hw,
+	&meson8b_fclk_div3.hw,
+	&meson8b_fclk_div5.hw,
+	&meson8m2_gp_pll.hw,
 };
 static struct clk_regmap meson8b_vpu_0_sel = {
 	.hw.init = &(struct clk_init_data){
 		.name = "vpu_0_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_vpu_0_1_parent_names,
+		.parent_hws = meson8b_vpu_0_1_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vpu_0_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = mmeson8m2_vpu_0_1_parent_names,
+		.parent_hws = mmeson8m2_vpu_0_1_parent_hws,
-		.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
+		.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vpu_0_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "vpu_0_sel" },
+		.parent_data = &(const struct clk_parent_data) {
+			/*
+			 * Note:
+			 * meson8b and meson8m2 have different vpu_0_sels (with
+			 * different struct clk_hw). We fallback to the global
+			 * naming string mechanism so vpu_0_div picks up the
+			 * appropriate one.
+			 */
+			.name = "vpu_0_sel",
+			.index = -1,
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "vpu_0",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "vpu_0_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vpu_0_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vpu_1_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_vpu_0_1_parent_names,
+		.parent_hws = meson8b_vpu_0_1_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vpu_1_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = mmeson8m2_vpu_0_1_parent_names,
+		.parent_hws = mmeson8m2_vpu_0_1_parent_hws,
-		.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
+		.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vpu_1_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "vpu_1_sel" },
+		.parent_data = &(const struct clk_parent_data) {
+			/*
+			 * Note:
+			 * meson8b and meson8m2 have different vpu_1_sels (with
+			 * different struct clk_hw). We fallback to the global
+			 * naming string mechanism so vpu_1_div picks up the
+			 * appropriate one.
+			 */
+			.name = "vpu_1_sel",
+			.index = -1,
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "vpu_1",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "vpu_1_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vpu_1_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vpu",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vpu_0.hw,
+			&meson8b_vpu_1.hw,
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_NO_REPARENT,
 	},
 };
-static const char * const meson8b_vdec_parent_names[] = {
+static const struct clk_hw *meson8b_vdec_parent_hws[] = {
-	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
+	&meson8b_fclk_div4.hw,
+	&meson8b_fclk_div3.hw,
+	&meson8b_fclk_div5.hw,
+	&meson8b_fclk_div7.hw,
+	&meson8b_mpll2.hw,
+	&meson8b_mpll1.hw,
 };
 static struct clk_regmap meson8b_vdec_1_sel = {
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_1_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_vdec_parent_names,
+		.parent_hws = meson8b_vdec_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_1_1_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "vdec_1_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_1_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "vdec_1_1",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "vdec_1_1_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_1_1_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_1_2_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "vdec_1_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_1_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "vdec_1_2",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "vdec_1_2_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_1_2_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_1",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_1_1.hw,
+			&meson8b_vdec_1_2.hw,
+		},
 		.num_parents = 2,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_hcodec_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_vdec_parent_names,
+		.parent_hws = meson8b_vdec_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_hcodec_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "vdec_hcodec_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_hcodec_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "vdec_hcodec",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "vdec_hcodec_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_hcodec_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_2_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_vdec_parent_names,
+		.parent_hws = meson8b_vdec_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_2_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "vdec_2_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_2_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "vdec_2",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "vdec_2_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_2_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_hevc_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_vdec_parent_names,
+		.parent_hws = meson8b_vdec_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "vdec_hevc_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "vdec_hevc_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_hevc_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data) {
 		.name = "vdec_hevc_en",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "vdec_hevc_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_hevc_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 		.name = "vdec_hevc",
 		.ops = &clk_regmap_mux_ops,
 		/* TODO: The second parent is currently unknown */
-		.parent_names = (const char *[]){ "vdec_hevc_en" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_vdec_hevc_en.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
-static const char * const meson8b_cts_amclk_parent_names[] = {
+static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
-	"mpll0", "mpll1", "mpll2"
+	&meson8b_mpll0.hw,
+	&meson8b_mpll1.hw,
+	&meson8b_mpll2.hw
 };
 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_amclk_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_cts_amclk_parent_names,
+		.parent_hws = meson8b_cts_amclk_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
 	},
 };
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_amclk_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "cts_amclk_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_amclk_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_amclk",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "cts_amclk_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_amclk_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
-static const char * const meson8b_cts_mclk_i958_parent_names[] = {
+static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
-	"mpll0", "mpll1", "mpll2"
+	&meson8b_mpll0.hw,
+	&meson8b_mpll1.hw,
+	&meson8b_mpll2.hw
 };
 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
 	.hw.init = &(struct clk_init_data) {
 		.name = "cts_mclk_i958_sel",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = meson8b_cts_mclk_i958_parent_names,
+		.parent_hws = meson8b_cts_mclk_i958_parent_hws,
-		.num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_names),
+		.num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
 	},
 };
 	.hw.init = &(struct clk_init_data) {
 		.name = "cts_mclk_i958_div",
 		.ops = &clk_regmap_divider_ops,
-		.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_mclk_i958_sel.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_mclk_i958",
 		.ops = &clk_regmap_gate_ops,
-		.parent_names = (const char *[]){ "cts_mclk_i958_div" },
+		.parent_hws = (const struct clk_hw *[]) {
+			&meson8b_cts_mclk_i958_div.hw
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "cts_i958",
 		.ops = &clk_regmap_mux_ops,
-		.parent_names = (const char *[]){ "cts_amclk",
+		.parent_hws = (const struct clk_hw *[]) {
-						  "cts_mclk_i958" },
+			&meson8b_cts_amclk.hw,
+			&meson8b_cts_mclk_i958.hw
+		},
 		.num_parents = 2,
 		/*
 		 * The parent is specific to origin of the audio data. Let the
 	},
 };
+#define MESON_GATE(_name, _reg, _bit) \
+	MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
 /* Everything Else (EE) domain gates */
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);

include/dt-bindings/clock/g12a-clkc.h+1−0

@@ -137,5 +137,6 @@ · 136 unmodified lines
137	#define CLKID_VDEC_HEVC 207	137	#define CLKID_VDEC_HEVC 207
138	#define CLKID_VDEC_HEVCF 210	138	#define CLKID_VDEC_HEVCF 210
139	#define CLKID_TS 212	139	#define CLKID_TS 212
		140	#define CLKID_CPUB_CLK 224
140		141
141	#endif /* __G12A_CLKC_H */	142	#endif /* __G12A_CLKC_H */

include/linux/clk-provider.h+1−0

@@ -817,6 +817,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); · 816 unmodified lines
817	struct clk_hw clk_hw_get_parent(const struct clk_hw hw);	817	struct clk_hw clk_hw_get_parent(const struct clk_hw hw);
818	struct clk_hw clk_hw_get_parent_by_index(const struct clk_hw hw,	818	struct clk_hw clk_hw_get_parent_by_index(const struct clk_hw hw,
819	unsigned int index);	819	unsigned int index);
		820	int clk_hw_set_parent(struct clk_hw hw, struct clk_hw new_parent);
820	unsigned int __clk_get_enable_count(struct clk *clk);	821	unsigned int __clk_get_enable_count(struct clk *clk);
821	unsigned long clk_hw_get_rate(const struct clk_hw *hw);	822	unsigned long clk_hw_get_rate(const struct clk_hw *hw);
822	unsigned long __clk_get_flags(struct clk *clk);	823	unsigned long __clk_get_flags(struct clk *clk);

Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

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