History

Merge tag 'drm-misc-next-2020-10-27' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for 5.11: UAPI Changes: - doc: rules for EBUSY on non-blocking commits; requirements for fourcc modifiers; on parsing EDID - fbdev/sbuslib: Remove unused FBIOSCURSOR32 - fourcc: deprecate DRM_FORMAT_MOD_NONE - virtio: Support blob resources for memory allocations; Expose host-visible and cross-device features Cross-subsystem Changes: - devicetree: Add vendor Prefix for Yes Optoelectronics, Shanghai Top Display Optoelectronics - dma-buf: Add struct dma_buf_map that stores DMA pointer and I/O-memory flag; dma_buf_vmap()/vunmap() return address in dma_buf_map; Use struct_size() macro Core Changes: - atomic: pass full state to CRTC atomic enable/disable; warn for EBUSY during non-blocking commits - dp: Prepare for DP 2.0 DPCD - dp_mst: Receive extended DPCD caps - dma-buf: Documentation - doc: Format modifiers; dma-buf-map; Cleanups - fbdev: Don't use compat_alloc_user_space(); mark as orphaned - fb-helper: Take lock in drm_fb_helper_restore_work_fb() - gem: Convert implementation and drivers to GEM object functions, remove GEM callbacks from struct drm_driver (expect gem_prime_mmap) - panel: Cleanups - pci: Add legacy infix to drm_irq_by_busid() - sched: Avoid infinite waits in drm_sched_entity_destroy() - switcheroo: Cleanups - ttm: Remove AGP support; Don't modify caching during swapout; Major refactoring of the implementation and API that affects all depending drivers; Add ttm_bo_wait_ctx(); Add ttm_bo_pin()/unpin() in favor of TTM_PL_FLAG_NO_EVICT; Remove ttm_bo_create(); Remove fault_reserve_notify() callback; Push move() implementation into drivers; Remove TTM_PAGE_FLAG_WRITE; Replace caching flags with init-time cache setting; Push ttm_tt_bind() into drivers; Replace move_notify() with delete_mem_notify(); No overlapping memcpy(); no more ttm_set_populated() - vram-helper: Fix BO top-down placement; TTM-related changes; Init GEM object functions with defaults; Default placement in system memory; Cleanups Driver Changes: - amdgpu: Use GEM object functions - armada: Use GEM object functions - aspeed: Configure output via sysfs; Init struct drm_driver with - ast: Reload LUT after FB format changes - bridge: Add driver and DT bindings for anx7625; Cleanups - bridge/dw-hdmi: Constify ops - bridge/ti-sn65dsi86: Add retries for link training - bridge/lvds-codec: Add support for regulator - bridge/tc358768: Restore connector support DRM_GEM_CMA_DRIVEROPS; Cleanups - display/ti,j721e-dss: Add DT properies assigned-clocks, assigned-clocks-parent and dma-coherent - display/ti,am65s-dss: Add DT properies assigned-clocks, assigned-clocks-parent and dma-coherent - etnaviv: Use GEM object functions - exynos: Use GEM object functions - fbdev: Cleanups and compiler fixes throughout framebuffer drivers - fbdev/cirrusfb: Avoid division by 0 - gma500: Use GEM object functions; Fix double-free of connector; Cleanups - hisilicon/hibmc: I2C-based DDC support; Use to_hibmc_drm_device(); Cleanups - i915: Use GEM object functions - imx/dcss: Init driver with DRM_GEM_CMA_DRIVER_OPS; Cleanups - ingenic: Reset pixel clock when parent clock changes; support reserved memory; Alloc F0 and F1 DMA channels at once; Support different pixel formats; Revert support for cached mmap buffers on F0/F1; support 30-bit/24-bit/8-bit-palette modes - komeda: Use DEFINE_SHOW_ATTRIBUTE - mcde: Detect platform_get_irq() errors - mediatek: Use GEM object functions - msm: Use GEM object functions - nouveau: Cleanups; TTM-related changes; Use GEM object functions - omapdrm: Use GEM object functions - panel: Add driver and DT bindings for Novatak nt36672a; Add driver and DT bindings for YTC700TLAG-05-201C; Add driver and DT bindings for TDO TL070WSH30; Cleanups - panel/mantix: Fix reset; Fix deref of NULL pointer in mantix_get_modes() - panel/otm8009a: Allow non-continuous dsi clock; Cleanups - panel/rm68200: Allow non-continuous dsi clock; Fix mode to 50 FPS - panfrost: Fix job timeout handling; Cleanups - pl111: Use GEM object functions - qxl: Cleanups; TTM-related changes; Pin new BOs with ttm_bo_init_reserved() - radeon: Cleanups; TTM-related changes; Use GEM object functions - rockchip: Use GEM object functions - shmobile: Cleanups - tegra: Use GEM object functions - tidss: Set drm_plane_helper_funcs.prepare_fb - tilcdc: Don't keep vblank interrupt enabled all the time - tve200: Detect platform_get_irq() errors - vc4: Use GEM object functions; Only register components once DSI is attached; Add Maxime as maintainer - vgem: Use GEM object functions - via: Simplify critical section in via_mem_alloc() - virtgpu: Use GEM object functions - virtio: Implement blob resources, host-visible and cross-device features; Support mapping of host-allocated resources; Use UUID APi; Cleanups - vkms: Use GEM object functions; Switch to SHMEM - vmwgfx: TTM-related changes; Inline ttm_bo_swapout_all() - xen: Use GEM object functions - xlnx: Use GEM object functions Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 6 years ago

Commit 1cd260a2 parents 3cea11c 4dfec0d291 files · +7523 −3257Browse files

Showing the changes to include/uapi (3 of 291 files). Show all

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3 files
  1. include/uapi/drm/drm_fourcc.h +40 −1
  2. include/uapi/drm/virtgpu_drm.h +38 −1
  3. include/uapi/linux/virtio_gpu.h +78 −0
include/uapi/drm/drm_fourcc.h+40−1
@@ -58,6 +58,30 @@ extern "C" { · 57 unmodified lines
58 * may preserve meaning - such as number of planes - from the fourcc code,58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.59 * whereas others may not.
60 *60 *
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
63 * another modifier. For instance, it's incorrect to encode pitch alignment in
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
65 * aligned modifier. That said, modifiers can have implicit minimal
66 * requirements.
67 *
68 * For modifiers where the combination of fourcc code and modifier can alias,
69 * a canonical pair needs to be defined and used by all drivers. Preferred
70 * combinations are also encouraged where all combinations might lead to
71 * confusion and unnecessarily reduced interoperability. An example for the
72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
73 *
74 * There are two kinds of modifier users:
75 *
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
77 * don't alias, otherwise two drivers might support the same format but use
78 * different aliases, preventing them from sharing buffers in an efficient
79 * format.
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81 * see modifiers as opaque tokens they can check for equality and intersect.
82 * These users musn't need to know to reason about the modifier value
83 * (i.e. they are not expected to extract information out of the modifier).
84 *
61 * Vendors should document their modifier usage in as much detail as85 * Vendors should document their modifier usage in as much detail as
62 * possible, to ensure maximum compatibility across devices, drivers and86 * possible, to ensure maximum compatibility across devices, drivers and
63 * applications.87 * applications.
@@ -155,6 +179,12 @@ extern "C" { · 91 unmodified lines
155#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */179#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
156#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */180#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
157 181
182/*
183 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
184 * of unused padding per component:
185 */
186#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
187
158/* packed YCbCr */188/* packed YCbCr */
159#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */189#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
160#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */190#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
@@ -320,7 +350,6 @@ extern "C" { · 159 unmodified lines
320 */350 */
321 351
322/* Vendor Ids: */352/* Vendor Ids: */
323#define DRM_FORMAT_MOD_NONE 0
324#define DRM_FORMAT_MOD_VENDOR_NONE 0353#define DRM_FORMAT_MOD_VENDOR_NONE 0
325#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01354#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
326#define DRM_FORMAT_MOD_VENDOR_AMD 0x02355#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
@@ -392,6 +421,16 @@ extern "C" { · 65 unmodified lines
392 */421 */
393#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)422#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
394 423
424/*
425 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
426 *
427 * The "none" format modifier doesn't actually mean that the modifier is
428 * implicit, instead it means that the layout is linear. Whether modifiers are
429 * used is out-of-band information carried in an API-specific way (e.g. in a
430 * flag for drm_mode_fb_cmd2).
431 */
432#define DRM_FORMAT_MOD_NONE 0
433
395/* Intel framebuffer modifiers */434/* Intel framebuffer modifiers */
396 435
397/*436/*
include/uapi/drm/virtgpu_drm.h+38−1
@@ -46,6 +46,7 @@ extern "C" { · 45 unmodified lines
46#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x0746#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
47#define DRM_VIRTGPU_WAIT 0x0847#define DRM_VIRTGPU_WAIT 0x08
48#define DRM_VIRTGPU_GET_CAPS 0x0948#define DRM_VIRTGPU_GET_CAPS 0x09
49#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
49 50
50#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x0151#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
51#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x0252#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
@@ -71,6 +72,9 @@ struct drm_virtgpu_execbuffer { · 19 unmodified lines
71 72
72#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */73#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
73#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */74#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
75#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
76#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
77#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
74 78
75struct drm_virtgpu_getparam {79struct drm_virtgpu_getparam {
76 __u64 param;80 __u64 param;
@@ -100,7 +104,7 @@ struct drm_virtgpu_resource_info { · 23 unmodified lines
100 __u32 bo_handle;104 __u32 bo_handle;
101 __u32 res_handle;105 __u32 res_handle;
102 __u32 size;106 __u32 size;
103 __u32 stride;107 __u32 blob_mem;
104};108};
105 109
106struct drm_virtgpu_3d_box {110struct drm_virtgpu_3d_box {
@@ -117,6 +121,8 @@ struct drm_virtgpu_3d_transfer_to_host { · 10 unmodified lines
117 struct drm_virtgpu_3d_box box;121 struct drm_virtgpu_3d_box box;
118 __u32 level;122 __u32 level;
119 __u32 offset;123 __u32 offset;
124 __u32 stride;
125 __u32 layer_stride;
120};126};
121 127
122struct drm_virtgpu_3d_transfer_from_host {128struct drm_virtgpu_3d_transfer_from_host {
@@ -124,6 +130,8 @@ struct drm_virtgpu_3d_transfer_from_host { · 1 unmodified line
124 struct drm_virtgpu_3d_box box;130 struct drm_virtgpu_3d_box box;
125 __u32 level;131 __u32 level;
126 __u32 offset;132 __u32 offset;
133 __u32 stride;
134 __u32 layer_stride;
127};135};
128 136
129#define VIRTGPU_WAIT_NOWAIT 1 /* like it */137#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
@@ -140,6 +148,31 @@ struct drm_virtgpu_get_caps { · 10 unmodified lines
140 __u32 pad;148 __u32 pad;
141};149};
142 150
151struct drm_virtgpu_resource_create_blob {
152#define VIRTGPU_BLOB_MEM_GUEST 0x0001
153#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
154#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
155
156#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
157#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
158#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
159 /* zero is invalid blob_mem */
160 __u32 blob_mem;
161 __u32 blob_flags;
162 __u32 bo_handle;
163 __u32 res_handle;
164 __u64 size;
165
166 /*
167 * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
168 * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
169 */
170 __u32 pad;
171 __u32 cmd_size;
172 __u64 cmd;
173 __u64 blob_id;
174};
175
143#define DRM_IOCTL_VIRTGPU_MAP \176#define DRM_IOCTL_VIRTGPU_MAP \
144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)177 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
145 178
@@ -175,6 +208,10 @@ struct drm_virtgpu_get_caps { · 29 unmodified lines
175 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \208 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
176 struct drm_virtgpu_get_caps)209 struct drm_virtgpu_get_caps)
177 210
211#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \
212 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
213 struct drm_virtgpu_resource_create_blob)
214
178#if defined(__cplusplus)215#if defined(__cplusplus)
179}216}
180#endif217#endif
include/uapi/linux/virtio_gpu.h+78−0
@@ -55,6 +55,11 @@ · 54 unmodified lines
55 */55 */
56#define VIRTIO_GPU_F_RESOURCE_UUID 256#define VIRTIO_GPU_F_RESOURCE_UUID 2
57 57
58/*
59 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
60 */
61#define VIRTIO_GPU_F_RESOURCE_BLOB 3
62
58enum virtio_gpu_ctrl_type {63enum virtio_gpu_ctrl_type {
59 VIRTIO_GPU_UNDEFINED = 0,64 VIRTIO_GPU_UNDEFINED = 0,
60 65
@@ -71,6 +76,8 @@ enum virtio_gpu_ctrl_type { · 10 unmodified lines
71 VIRTIO_GPU_CMD_GET_CAPSET,76 VIRTIO_GPU_CMD_GET_CAPSET,
72 VIRTIO_GPU_CMD_GET_EDID,77 VIRTIO_GPU_CMD_GET_EDID,
73 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,78 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
79 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
80 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
74 81
75 /* 3d commands */82 /* 3d commands */
76 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,83 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
@@ -81,6 +88,8 @@ enum virtio_gpu_ctrl_type { · 4 unmodified lines
81 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,88 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
82 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,89 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
83 VIRTIO_GPU_CMD_SUBMIT_3D,90 VIRTIO_GPU_CMD_SUBMIT_3D,
91 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
92 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
84 93
85 /* cursor commands */94 /* cursor commands */
86 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,95 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
@@ -93,6 +102,7 @@ enum virtio_gpu_ctrl_type { · 6 unmodified lines
93 VIRTIO_GPU_RESP_OK_CAPSET,102 VIRTIO_GPU_RESP_OK_CAPSET,
94 VIRTIO_GPU_RESP_OK_EDID,103 VIRTIO_GPU_RESP_OK_EDID,
95 VIRTIO_GPU_RESP_OK_RESOURCE_UUID,104 VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
105 VIRTIO_GPU_RESP_OK_MAP_INFO,
96 106
97 /* error responses */107 /* error responses */
98 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,108 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
@@ -103,6 +113,11 @@ enum virtio_gpu_ctrl_type { · 4 unmodified lines
103 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,113 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
104};114};
105 115
116enum virtio_gpu_shm_id {
117 VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
118 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
119};
120
106#define VIRTIO_GPU_FLAG_FENCE (1 << 0)121#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
107 122
108struct virtio_gpu_ctrl_hdr {123struct virtio_gpu_ctrl_hdr {
@@ -359,4 +374,67 @@ struct virtio_gpu_resp_resource_uuid { · 250 unmodified lines
359 __u8 uuid[16];374 __u8 uuid[16];
360};375};
361 376
377/* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
378struct virtio_gpu_resource_create_blob {
379 struct virtio_gpu_ctrl_hdr hdr;
380 __le32 resource_id;
381#define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
382#define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
383#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
384
385#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
386#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
387#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
388 /* zero is invalid blob mem */
389 __le32 blob_mem;
390 __le32 blob_flags;
391 __le32 nr_entries;
392 __le64 blob_id;
393 __le64 size;
394 /*
395 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
396 */
397};
398
399/* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
400struct virtio_gpu_set_scanout_blob {
401 struct virtio_gpu_ctrl_hdr hdr;
402 struct virtio_gpu_rect r;
403 __le32 scanout_id;
404 __le32 resource_id;
405 __le32 width;
406 __le32 height;
407 __le32 format;
408 __le32 padding;
409 __le32 strides[4];
410 __le32 offsets[4];
411};
412
413/* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
414struct virtio_gpu_resource_map_blob {
415 struct virtio_gpu_ctrl_hdr hdr;
416 __le32 resource_id;
417 __le32 padding;
418 __le64 offset;
419};
420
421/* VIRTIO_GPU_RESP_OK_MAP_INFO */
422#define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
423#define VIRTIO_GPU_MAP_CACHE_NONE 0x00
424#define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
425#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
426#define VIRTIO_GPU_MAP_CACHE_WC 0x03
427struct virtio_gpu_resp_map_info {
428 struct virtio_gpu_ctrl_hdr hdr;
429 __u32 map_info;
430 __u32 padding;
431};
432
433/* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
434struct virtio_gpu_resource_unmap_blob {
435 struct virtio_gpu_ctrl_hdr hdr;
436 __le32 resource_id;
437 __le32 padding;
438};
439
362#endif440#endif

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