Ariel Levkovich says: ==================== The series exposes the ICM address of the receive transport interface (TIR) of Raw Packet and RSS QPs to the user since they are required to properly create and insert steering rules that direct flows to these QPs. ==================== For dependencies this branch is based on mlx5-next from git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux * branch 'mlx5_tir_icm': IB/mlx5: Expose TIR ICM address to user space net/mlx5: Introduce new TIR creation core API net/mlx5: Expose TIR ICM address in command outbox
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| @@ -360,6 +360,7 @@ enum mlx5_ib_create_qp_resp_mask { · 359 unmodified lines | ||
| 360 | 360 | MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, |
| 361 | 361 | MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, |
| 362 | 362 | MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, |
| 363 | + MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4, | |
| 363 | 364 | }; |
| 364 | 365 | |
| 365 | 366 | struct mlx5_ib_create_qp_resp { |
| @@ -371,6 +372,7 @@ struct mlx5_ib_create_qp_resp { · 5 unmodified lines | ||
| 371 | 372 | __u32 rqn; |
| 372 | 373 | __u32 sqn; |
| 373 | 374 | __u32 reserved1; |
| 375 | + __u64 tir_icm_addr; | |
| 374 | 376 | }; |
| 375 | 377 | |
| 376 | 378 | struct mlx5_ib_alloc_mw { |