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Merge tag 'amd-drm-fixes-6.2-2023-01-25' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-6.2-2023-01-25: amdgpu: - GC11.x fixes - SMU13.0.0 fix - Freesync video fix - DP MST fixes drm: - DP MST kref fix

Dave Airlie committed 3 years ago

Commit 1d65bd62 parents af0af90 4b069558 files · +89 −21Browse files

Unified · Split

8 files
  1. drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +1 −0
  2. drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +2 −1
  3. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +31 −0
  4. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +39 −12
  5. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +0 −5
  6. drivers/gpu/drm/amd/display/dc/core/dc_link.c +12 −2
  7. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +1 −0
  8. drivers/gpu/drm/display/drm_dp_mst_topology.c +3 −1
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c+1−0
@@ -35,6 +35,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin"); · 34 unmodified lines
3535 MODULE_FIRMWARE("amdgpu/gc_11_0_1_imu.bin");
3636 MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin");
3737 MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");
38+MODULE_FIRMWARE("amdgpu/gc_11_0_4_imu.bin");
3839
3940 static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
4041 {
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c+2−1
@@ -40,6 +40,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); · 39 unmodified lines
4040 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
4141 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
4242 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
43+MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
44+MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
4345
4446 static int mes_v11_0_hw_fini(void *handle);
4547 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
@@ -196,7 +198,6 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, · 150 unmodified lines
196198 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
197199 mes_add_queue_pkt.tma_addr = input->tma_addr;
198200 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
199− mes_add_queue_pkt.trap_en = 1;
200201
201202 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
202203 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+31−0
@@ -8881,6 +8881,13 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, · 8880 unmodified lines
88818881 if (!dm_old_crtc_state->stream)
88828882 goto skip_modeset;
88838883
8884+ /* Unset freesync video if it was active before */
8885+ if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
8886+ dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
8887+ dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
8888+ }
8889+
8890+ /* Now check if we should set freesync video mode */
88848891 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
88858892 is_timing_unchanged_for_freesync(new_crtc_state,
88868893 old_crtc_state)) {
@@ -9490,6 +9497,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 603 unmodified lines
94909497 struct drm_connector_state *old_con_state, *new_con_state;
94919498 struct drm_crtc *crtc;
94929499 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9500+ struct drm_dp_mst_topology_mgr *mgr;
9501+ struct drm_dp_mst_topology_state *mst_state;
94939502 struct drm_plane *plane;
94949503 struct drm_plane_state *old_plane_state, *new_plane_state;
94959504 enum dc_status status;
@@ -9745,6 +9754,28 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 249 unmodified lines
97459754 lock_and_validation_needed = true;
97469755 }
97479756
9757+#if defined(CONFIG_DRM_AMD_DC_DCN)
9758+ /* set the slot info for each mst_state based on the link encoding format */
9759+ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
9760+ struct amdgpu_dm_connector *aconnector;
9761+ struct drm_connector *connector;
9762+ struct drm_connector_list_iter iter;
9763+ u8 link_coding_cap;
9764+
9765+ drm_connector_list_iter_begin(dev, &iter);
9766+ drm_for_each_connector_iter(connector, &iter) {
9767+ if (connector->index == mst_state->mgr->conn_base_id) {
9768+ aconnector = to_amdgpu_dm_connector(connector);
9769+ link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
9770+ drm_dp_mst_update_slots(mst_state, link_coding_cap);
9771+
9772+ break;
9773+ }
9774+ }
9775+ drm_connector_list_iter_end(&iter);
9776+ }
9777+#endif
9778+
97489779 /**
97499780 * Streams and planes are reset when there are changes that affect
97509781 * bandwidth. Anything that affects bandwidth needs to go through
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c+39−12
@@ -120,23 +120,50 @@ enum dc_edid_status dm_helpers_parse_edid_caps( · 119 unmodified lines
120120 }
121121
122122 static void
123−fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state,
124− struct amdgpu_dm_connector *aconnector,
123+fill_dc_mst_payload_table_from_drm(struct dc_link *link,
124+ bool enable,
125+ struct drm_dp_mst_atomic_payload *target_payload,
125126 struct dc_dp_mst_stream_allocation_table *table)
126127 {
127128 struct dc_dp_mst_stream_allocation_table new_table = { 0 };
128129 struct dc_dp_mst_stream_allocation *sa;
129− struct drm_dp_mst_atomic_payload *payload;
130+ struct link_mst_stream_allocation_table copy_of_link_table =
131+ link->mst_stream_alloc_table;
132+
133+ int i;
134+ int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
135+ struct link_mst_stream_allocation *dc_alloc;
136+
137+ /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
138+ if (enable) {
139+ dc_alloc =
140+ &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
141+ dc_alloc->vcp_id = target_payload->vcpi;
142+ dc_alloc->slot_count = target_payload->time_slots;
143+ } else {
144+ for (i = 0; i < copy_of_link_table.stream_count; i++) {
145+ dc_alloc =
146+ &copy_of_link_table.stream_allocations[i];
147+
148+ if (dc_alloc->vcp_id == target_payload->vcpi) {
149+ dc_alloc->vcp_id = 0;
150+ dc_alloc->slot_count = 0;
151+ break;
152+ }
153+ }
154+ ASSERT(i != copy_of_link_table.stream_count);
155+ }
130156
131157 /* Fill payload info*/
132− list_for_each_entry(payload, &mst_state->payloads, next) {
133− if (payload->delete)
134− continue;
135−
136− sa = &new_table.stream_allocations[new_table.stream_count];
137− sa->slot_count = payload->time_slots;
138− sa->vcp_id = payload->vcpi;
139− new_table.stream_count++;
158+ for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
159+ dc_alloc =
160+ &copy_of_link_table.stream_allocations[i];
161+ if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
162+ sa = &new_table.stream_allocations[new_table.stream_count];
163+ sa->slot_count = dc_alloc->slot_count;
164+ sa->vcp_id = dc_alloc->vcp_id;
165+ new_table.stream_count++;
166+ }
140167 }
141168
142169 /* Overwrite the old table */
@@ -185,7 +212,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( · 42 unmodified lines
185212 * AUX message. The sequence is slot 1-63 allocated sequence for each
186213 * stream. AMD ASIC stream slot allocation should follow the same
187214 * sequence. copy DRM MST allocation to dc */
188− fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table);
215+ fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table);
189216
190217 return true;
191218 }
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+0−5
@@ -903,11 +903,6 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, · 902 unmodified lines
903903 if (IS_ERR(mst_state))
904904 return PTR_ERR(mst_state);
905905
906− mst_state->pbn_div = dm_mst_get_pbn_divider(dc_link);
907−#if defined(CONFIG_DRM_AMD_DC_DCN)
908− drm_dp_mst_update_slots(mst_state, dc_link_dp_mst_decide_link_encoding_format(dc_link));
909−#endif
910−
911906 /* Set up params */
912907 for (i = 0; i < dc_state->stream_count; i++) {
913908 struct dc_dsc_policy dsc_policy = {0};
drivers/gpu/drm/amd/display/dc/core/dc_link.c+12−2
@@ -3995,10 +3995,13 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 3994 unmodified lines
39953995 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
39963996 int i;
39973997 bool mst_mode = (link->type == dc_connection_mst_branch);
3998+ /* adjust for drm changes*/
3999+ bool update_drm_mst_state = true;
39984000 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
39994001 const struct dc_link_settings empty_link_settings = {0};
40004002 DC_LOGGER_INIT(link->ctx->logger);
40014003
4004+
40024005 /* deallocate_mst_payload is called before disable link. When mode or
40034006 * disable/enable monitor, new stream is created which is not in link
40044007 * stream[] yet. For this, payload is not allocated yet, so de-alloc
@@ -4014,7 +4017,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 9 unmodified lines
40144017 &empty_link_settings,
40154018 avg_time_slots_per_mtp);
40164019
4017− if (mst_mode) {
4020+ if (mst_mode || update_drm_mst_state) {
40184021 /* when link is in mst mode, reply on mst manager to remove
40194022 * payload
40204023 */
@@ -4077,11 +4080,18 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 56 unmodified lines
40774080 stream->ctx,
40784081 stream);
40794082
4083+ if (!update_drm_mst_state)
4084+ dm_helpers_dp_mst_send_payload_allocation(
4085+ stream->ctx,
4086+ stream,
4087+ false);
4088+ }
4089+
4090+ if (update_drm_mst_state)
40804091 dm_helpers_dp_mst_send_payload_allocation(
40814092 stream->ctx,
40824093 stream,
40834094 false);
4084− }
40854095
40864096 return DC_OK;
40874097 }
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c+1−0
@@ -145,6 +145,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = · 144 unmodified lines
145145 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
146146 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
147147 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
148+ MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
148149 };
149150
150151 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
drivers/gpu/drm/display/drm_dp_mst_topology.c+3−1
@@ -3372,6 +3372,9 @@ void drm_dp_remove_payload(struct drm_dp_mst_topology_mgr *mgr, · 3371 unmodified lines
33723372
33733373 mgr->payload_count--;
33743374 mgr->next_start_slot -= payload->time_slots;
3375+
3376+ if (payload->delete)
3377+ drm_dp_mst_put_port_malloc(payload->port);
33753378 }
33763379 EXPORT_SYMBOL(drm_dp_remove_payload);
33773380
@@ -4327,7 +4330,6 @@ int drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, · 949 unmodified lines
43274330
43284331 drm_dbg_atomic(mgr->dev, "[MST PORT:%p] TU %d -> 0\n", port, payload->time_slots);
43294332 if (!payload->delete) {
4330− drm_dp_mst_put_port_malloc(port);
43314333 payload->pbn = 0;
43324334 payload->delete = true;
43334335 topology_state->payload_mask &= ~BIT(payload->vcpi - 1);