Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
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| @@ -723,6 +723,7 @@ · 722 unmodified lines | ||
| 723 | 723 | #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ |
| 724 | 724 | #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ |
| 725 | 725 | #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ |
| 726 | +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ | |
| 726 | 727 | #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ |
| 727 | 728 | #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ |
| 728 | 729 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT |
| @@ -1066,6 +1067,10 @@ · 337 unmodified lines | ||
| 1066 | 1067 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ |
| 1067 | 1068 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ |
| 1068 | 1069 | |
| 1070 | +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ | |
| 1071 | +#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ | |
| 1072 | +#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ | |
| 1073 | + | |
| 1069 | 1074 | /* Data Link Feature */ |
| 1070 | 1075 | #define PCI_DLF_CAP 0x04 /* Capabilities Register */ |
| 1071 | 1076 | #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ |