Pull VFIO updates from Alex Williamson: - Fix spapr iommu error case case (Alexey Kardashevskiy) - Consolidate region type definitions (Cornelia Huck) - Restore saved original PCI state on release (hexin) - Simplify mtty sample driver interrupt path (Parav Pandit) - Support for reporting valid IOVA regions to user (Shameer Kolothum) * tag 'vfio-v5.4-rc1' of git://github.com/awilliam/linux-vfio: vfio_pci: Restore original state on release vfio/type1: remove duplicate retrieval of reserved regions vfio/type1: Add IOVA range capability support vfio/type1: check dma map request is within a valid iova range vfio/spapr_tce: Fix incorrect tce_iommu_group memory free vfio-mdev/mtty: Simplify interrupt generation vfio: re-arrange vfio region definitions vfio/type1: Update iova list on detach vfio/type1: Check reserved region conflict and update iova list vfio/type1: Introduce iova list and add iommu aperture validity check
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| @@ -295,15 +295,38 @@ struct vfio_region_info_cap_type { · 294 unmodified lines | |||
| 295 | __u32 subtype; /* type specific */ | 295 | __u32 subtype; /* type specific */ |
| 296 | }; | 296 | }; |
| 297 | 297 | ||
| 298 | /* | ||
| 299 | * List of region types, global per bus driver. | ||
| 300 | * If you introduce a new type, please add it here. | ||
| 301 | */ | ||
| 302 | |||
| 303 | /* PCI region type containing a PCI vendor part */ | ||
| 298 | #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) | 304 | #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) |
| 299 | #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) | 305 | #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) |
| 306 | #define VFIO_REGION_TYPE_GFX (1) | ||
| 307 | #define VFIO_REGION_TYPE_CCW (2) | ||
| 308 | |||
| 309 | /* sub-types for VFIO_REGION_TYPE_PCI_* */ | ||
| 300 | 310 | ||
| 301 | /* 8086 Vendor sub-types */ | 311 | /* 8086 vendor PCI sub-types */ |
| 302 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) | 312 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) |
| 303 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) | 313 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) |
| 304 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) | 314 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) |
| 305 | 315 | ||
| 306 | #define VFIO_REGION_TYPE_GFX (1) | 316 | /* 10de vendor PCI sub-types */ |
| 317 | /* | ||
| 318 | * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | ||
| 319 | */ | ||
| 320 | #define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | ||
| 321 | |||
| 322 | /* 1014 vendor PCI sub-types */ | ||
| 323 | /* | ||
| 324 | * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | ||
| 325 | * to do TLB invalidation on a GPU. | ||
| 326 | */ | ||
| 327 | #define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | ||
| 328 | |||
| 329 | /* sub-types for VFIO_REGION_TYPE_GFX */ | ||
| 307 | #define VFIO_REGION_SUBTYPE_GFX_EDID (1) | 330 | #define VFIO_REGION_SUBTYPE_GFX_EDID (1) |
| 308 | 331 | ||
| 309 | /** | 332 | /** |
| @@ -353,25 +376,9 @@ struct vfio_region_gfx_edid { · 43 unmodified lines | |||
| 353 | #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 | 376 | #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 |
| 354 | }; | 377 | }; |
| 355 | 378 | ||
| 356 | #define VFIO_REGION_TYPE_CCW (2) | 379 | /* sub-types for VFIO_REGION_TYPE_CCW */ |
| 357 | /* ccw sub-types */ | ||
| 358 | #define VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD (1) | 380 | #define VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD (1) |
| 359 | 381 | ||
| 360 | /* | ||
| 361 | * 10de vendor sub-type | ||
| 362 | * | ||
| 363 | * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | ||
| 364 | */ | ||
| 365 | #define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | ||
| 366 | |||
| 367 | /* | ||
| 368 | * 1014 vendor sub-type | ||
| 369 | * | ||
| 370 | * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | ||
| 371 | * to do TLB invalidation on a GPU. | ||
| 372 | */ | ||
| 373 | #define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | ||
| 374 | |||
| 375 | /* | 382 | /* |
| 376 | * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped | 383 | * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped |
| 377 | * which allows direct access to non-MSIX registers which happened to be within | 384 | * which allows direct access to non-MSIX registers which happened to be within |
| @@ -714,7 +721,31 @@ struct vfio_iommu_type1_info { · 336 unmodified lines | |||
| 714 | __u32 argsz; | 721 | __u32 argsz; |
| 715 | __u32 flags; | 722 | __u32 flags; |
| 716 | #define VFIO_IOMMU_INFO_PGSIZES (1 << 0) /* supported page sizes info */ | 723 | #define VFIO_IOMMU_INFO_PGSIZES (1 << 0) /* supported page sizes info */ |
| 717 | __u64 iova_pgsizes; /* Bitmap of supported page sizes */ | 724 | #define VFIO_IOMMU_INFO_CAPS (1 << 1) /* Info supports caps */ |
| 725 | __u64 iova_pgsizes; /* Bitmap of supported page sizes */ | ||
| 726 | __u32 cap_offset; /* Offset within info struct of first cap */ | ||
| 727 | }; | ||
| 728 | |||
| 729 | /* | ||
| 730 | * The IOVA capability allows to report the valid IOVA range(s) | ||
| 731 | * excluding any non-relaxable reserved regions exposed by | ||
| 732 | * devices attached to the container. Any DMA map attempt | ||
| 733 | * outside the valid iova range will return error. | ||
| 734 | * | ||
| 735 | * The structures below define version 1 of this capability. | ||
| 736 | */ | ||
| 737 | #define VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE 1 | ||
| 738 | |||
| 739 | struct vfio_iova_range { | ||
| 740 | __u64 start; | ||
| 741 | __u64 end; | ||
| 742 | }; | ||
| 743 | |||
| 744 | struct vfio_iommu_type1_info_cap_iova_range { | ||
| 745 | struct vfio_info_cap_header header; | ||
| 746 | __u32 nr_iovas; | ||
| 747 | __u32 reserved; | ||
| 748 | struct vfio_iova_range iova_ranges[]; | ||
| 718 | }; | 749 | }; |
| 719 | 750 | ||
| 720 | #define VFIO_IOMMU_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) | 751 | #define VFIO_IOMMU_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) |