| @@ -114,6 +114,9 @@ union igp_info { · 113 unmodified lines |
| 114 | struct atom_integrated_system_info_v1_11 v11; | 114 | struct atom_integrated_system_info_v1_11 v11; |
| 115 | }; | 115 | }; |
| 116 | | 116 | |
| | 117 | union umc_info { |
| | 118 | struct atom_umc_info_v3_1 v31; |
| | 119 | }; |
| 117 | /* | 120 | /* |
| 118 | * Return vram width from integrated system info table, if available, | 121 | * Return vram width from integrated system info table, if available, |
| 119 | * or 0 if not. | 122 | * or 0 if not. |
| @@ -143,6 +146,94 @@ int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev) · 23 unmodified lines |
| 143 | return 0; | 146 | return 0; |
| 144 | } | 147 | } |
| 145 | | 148 | |
| | 149 | static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev, |
| | 150 | int atom_mem_type) |
| | 151 | { |
| | 152 | int vram_type; |
| | 153 | |
| | 154 | if (adev->flags & AMD_IS_APU) { |
| | 155 | switch (atom_mem_type) { |
| | 156 | case Ddr2MemType: |
| | 157 | case LpDdr2MemType: |
| | 158 | vram_type = AMDGPU_VRAM_TYPE_DDR2; |
| | 159 | break; |
| | 160 | case Ddr3MemType: |
| | 161 | case LpDdr3MemType: |
| | 162 | vram_type = AMDGPU_VRAM_TYPE_DDR3; |
| | 163 | break; |
| | 164 | case Ddr4MemType: |
| | 165 | case LpDdr4MemType: |
| | 166 | vram_type = AMDGPU_VRAM_TYPE_DDR4; |
| | 167 | break; |
| | 168 | default: |
| | 169 | vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; |
| | 170 | break; |
| | 171 | } |
| | 172 | } else { |
| | 173 | switch (atom_mem_type) { |
| | 174 | case ATOM_DGPU_VRAM_TYPE_GDDR5: |
| | 175 | vram_type = AMDGPU_VRAM_TYPE_GDDR5; |
| | 176 | break; |
| | 177 | case ATOM_DGPU_VRAM_TYPE_HBM: |
| | 178 | vram_type = AMDGPU_VRAM_TYPE_HBM; |
| | 179 | break; |
| | 180 | default: |
| | 181 | vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; |
| | 182 | break; |
| | 183 | } |
| | 184 | } |
| | 185 | |
| | 186 | return vram_type; |
| | 187 | } |
| | 188 | /* |
| | 189 | * Return vram type from either integrated system info table |
| | 190 | * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not |
| | 191 | */ |
| | 192 | int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev) |
| | 193 | { |
| | 194 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
| | 195 | int index; |
| | 196 | u16 data_offset, size; |
| | 197 | union igp_info *igp_info; |
| | 198 | union umc_info *umc_info; |
| | 199 | u8 frev, crev; |
| | 200 | u8 mem_type; |
| | 201 | |
| | 202 | if (adev->flags & AMD_IS_APU) |
| | 203 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, |
| | 204 | integratedsysteminfo); |
| | 205 | else |
| | 206 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, |
| | 207 | umc_info); |
| | 208 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, |
| | 209 | index, &size, |
| | 210 | &frev, &crev, &data_offset)) { |
| | 211 | if (adev->flags & AMD_IS_APU) { |
| | 212 | igp_info = (union igp_info *) |
| | 213 | (mode_info->atom_context->bios + data_offset); |
| | 214 | switch (crev) { |
| | 215 | case 11: |
| | 216 | mem_type = igp_info->v11.memorytype; |
| | 217 | return convert_atom_mem_type_to_vram_type(adev, mem_type); |
| | 218 | default: |
| | 219 | return 0; |
| | 220 | } |
| | 221 | } else { |
| | 222 | umc_info = (union umc_info *) |
| | 223 | (mode_info->atom_context->bios + data_offset); |
| | 224 | switch (crev) { |
| | 225 | case 1: |
| | 226 | mem_type = umc_info->v31.vram_type; |
| | 227 | return convert_atom_mem_type_to_vram_type(adev, mem_type); |
| | 228 | default: |
| | 229 | return 0; |
| | 230 | } |
| | 231 | } |
| | 232 | } |
| | 233 | |
| | 234 | return 0; |
| | 235 | } |
| | 236 | |
| 146 | union firmware_info { | 237 | union firmware_info { |
| 147 | struct atom_firmware_info_v3_1 v31; | 238 | struct atom_firmware_info_v3_1 v31; |
| 148 | }; | 239 | }; |
| @@ -151,10 +242,6 @@ union smu_info { · 2 unmodified lines |
| 151 | struct atom_smu_info_v3_1 v31; | 242 | struct atom_smu_info_v3_1 v31; |
| 152 | }; | 243 | }; |
| 153 | | 244 | |
| 154 | union umc_info { | | |
| 155 | struct atom_umc_info_v3_1 v31; | | |
| 156 | }; | | |
| 157 | | | |
| 158 | int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) | 245 | int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev) |
| 159 | { | 246 | { |
| 160 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | 247 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |