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drm/amdgpu: query vram type from atombios

The vram type for dGPU is stored in umc_info while sys mem type for APU is stored in integratedsysteminfo

Hawking Zhang committed 8 years ago

Commit 1e09b051 parent bc227cf4 files · +94 −7Browse files

Unified · Split

4 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +91 −4
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h +1 −0
  3. drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +1 −3
  4. include/uapi/drm/amdgpu_drm.h +1 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c+91−4
@@ -114,6 +114,9 @@ union igp_info { · 113 unmodified lines
114 struct atom_integrated_system_info_v1_11 v11;114 struct atom_integrated_system_info_v1_11 v11;
115};115};
116 116
117union umc_info {
118 struct atom_umc_info_v3_1 v31;
119};
117/*120/*
118 * Return vram width from integrated system info table, if available,121 * Return vram width from integrated system info table, if available,
119 * or 0 if not.122 * or 0 if not.
@@ -143,6 +146,94 @@ int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev) · 23 unmodified lines
143 return 0;146 return 0;
144}147}
145 148
149static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
150 int atom_mem_type)
151{
152 int vram_type;
153
154 if (adev->flags & AMD_IS_APU) {
155 switch (atom_mem_type) {
156 case Ddr2MemType:
157 case LpDdr2MemType:
158 vram_type = AMDGPU_VRAM_TYPE_DDR2;
159 break;
160 case Ddr3MemType:
161 case LpDdr3MemType:
162 vram_type = AMDGPU_VRAM_TYPE_DDR3;
163 break;
164 case Ddr4MemType:
165 case LpDdr4MemType:
166 vram_type = AMDGPU_VRAM_TYPE_DDR4;
167 break;
168 default:
169 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
170 break;
171 }
172 } else {
173 switch (atom_mem_type) {
174 case ATOM_DGPU_VRAM_TYPE_GDDR5:
175 vram_type = AMDGPU_VRAM_TYPE_GDDR5;
176 break;
177 case ATOM_DGPU_VRAM_TYPE_HBM:
178 vram_type = AMDGPU_VRAM_TYPE_HBM;
179 break;
180 default:
181 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
182 break;
183 }
184 }
185
186 return vram_type;
187}
188/*
189 * Return vram type from either integrated system info table
190 * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
191 */
192int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
193{
194 struct amdgpu_mode_info *mode_info = &adev->mode_info;
195 int index;
196 u16 data_offset, size;
197 union igp_info *igp_info;
198 union umc_info *umc_info;
199 u8 frev, crev;
200 u8 mem_type;
201
202 if (adev->flags & AMD_IS_APU)
203 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
204 integratedsysteminfo);
205 else
206 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
207 umc_info);
208 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
209 index, &size,
210 &frev, &crev, &data_offset)) {
211 if (adev->flags & AMD_IS_APU) {
212 igp_info = (union igp_info *)
213 (mode_info->atom_context->bios + data_offset);
214 switch (crev) {
215 case 11:
216 mem_type = igp_info->v11.memorytype;
217 return convert_atom_mem_type_to_vram_type(adev, mem_type);
218 default:
219 return 0;
220 }
221 } else {
222 umc_info = (union umc_info *)
223 (mode_info->atom_context->bios + data_offset);
224 switch (crev) {
225 case 1:
226 mem_type = umc_info->v31.vram_type;
227 return convert_atom_mem_type_to_vram_type(adev, mem_type);
228 default:
229 return 0;
230 }
231 }
232 }
233
234 return 0;
235}
236
146union firmware_info {237union firmware_info {
147 struct atom_firmware_info_v3_1 v31;238 struct atom_firmware_info_v3_1 v31;
148};239};
@@ -151,10 +242,6 @@ union smu_info { · 2 unmodified lines
151 struct atom_smu_info_v3_1 v31;242 struct atom_smu_info_v3_1 v31;
152};243};
153 244
154union umc_info {
155 struct atom_umc_info_v3_1 v31;
156};
157
158int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)245int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
159{246{
160 struct amdgpu_mode_info *mode_info = &adev->mode_info;247 struct amdgpu_mode_info *mode_info = &adev->mode_info;
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h+1−0
@@ -28,6 +28,7 @@ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev) · 27 unmodified lines
28void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);28void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
29int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);29int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
30int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);30int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
31int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
31int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);32int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
32 33
33#endif34#endif
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+1−3
@@ -836,9 +836,9 @@ static int gmc_v9_0_sw_init(void *handle) · 835 unmodified lines
836 836
837 spin_lock_init(&adev->gmc.invalidate_lock);837 spin_lock_init(&adev->gmc.invalidate_lock);
838 838
839 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
839 switch (adev->asic_type) {840 switch (adev->asic_type) {
840 case CHIP_RAVEN:841 case CHIP_RAVEN:
841 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
842 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {842 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
843 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);843 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
844 } else {844 } else {
@@ -849,8 +849,6 @@ static int gmc_v9_0_sw_init(void *handle) · 4 unmodified lines
849 }849 }
850 break;850 break;
851 case CHIP_VEGA10:851 case CHIP_VEGA10:
852 /* XXX Don't know how to get VRAM type yet. */
853 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
854 /*852 /*
855 * To fulfill 4-level page support,853 * To fulfill 4-level page support,
856 * vm size is 256TB (48bit), maximum size of Vega10,854 * vm size is 256TB (48bit), maximum size of Vega10,
include/uapi/drm/amdgpu_drm.h+1−0
@@ -806,6 +806,7 @@ struct drm_amdgpu_info_firmware { · 805 unmodified lines
806#define AMDGPU_VRAM_TYPE_GDDR5 5806#define AMDGPU_VRAM_TYPE_GDDR5 5
807#define AMDGPU_VRAM_TYPE_HBM 6807#define AMDGPU_VRAM_TYPE_HBM 6
808#define AMDGPU_VRAM_TYPE_DDR3 7808#define AMDGPU_VRAM_TYPE_DDR3 7
809#define AMDGPU_VRAM_TYPE_DDR4 8
809 810
810struct drm_amdgpu_info_device {811struct drm_amdgpu_info_device {
811 /** PCI Device ID */812 /** PCI Device ID */

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