Some archs defconfigs have CONFIG_FRAME_WARN set to 1024, which lead to this warning: drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c: warning: the frame size of 1184 bytes is larger than 1024 bytes
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| @@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) · 668 unmodified lines | |||
| 669 | }); | 669 | }); |
| 670 | } | 670 | } |
| 671 | 671 | ||
| 672 | void | 672 | int |
| 673 | nv40_grctx_init(struct nouveau_device *device, u32 *size) | 673 | nv40_grctx_init(struct nouveau_device *device, u32 *size) |
| 674 | { | 674 | { |
| 675 | u32 ctxprog[256], i; | 675 | u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; |
| 676 | struct nouveau_grctx ctx = { | 676 | struct nouveau_grctx ctx = { |
| 677 | .device = device, | 677 | .device = device, |
| 678 | .mode = NOUVEAU_GRCTX_PROG, | 678 | .mode = NOUVEAU_GRCTX_PROG, |
| 679 | .data = ctxprog, | 679 | .data = ctxprog, |
| 680 | .ctxprog_max = ARRAY_SIZE(ctxprog) | 680 | .ctxprog_max = 256, |
| 681 | }; | 681 | }; |
| 682 | 682 | ||
| 683 | if (!ctxprog) | ||
| 684 | return -ENOMEM; | ||
| 685 | |||
| 683 | nv40_grctx_generate(&ctx); | 686 | nv40_grctx_generate(&ctx); |
| 684 | 687 | ||
| 685 | nv_wr32(device, 0x400324, 0); | 688 | nv_wr32(device, 0x400324, 0); |
| 686 | for (i = 0; i < ctx.ctxprog_len; i++) | 689 | for (i = 0; i < ctx.ctxprog_len; i++) |
| 687 | nv_wr32(device, 0x400328, ctxprog[i]); | 690 | nv_wr32(device, 0x400328, ctxprog[i]); |
| 688 | *size = ctx.ctxvals_pos * 4; | 691 | *size = ctx.ctxvals_pos * 4; |
| 692 | |||
| 693 | kfree(ctxprog); | ||
| 694 | return 0; | ||
| 689 | } | 695 | } |
| @@ -346,7 +346,9 @@ nv40_graph_init(struct nouveau_object *object) · 345 unmodified lines | |||
| 346 | return ret; | 346 | return ret; |
| 347 | 347 | ||
| 348 | /* generate and upload context program */ | 348 | /* generate and upload context program */ |
| 349 | nv40_grctx_init(nv_device(priv), &priv->size); | 349 | ret = nv40_grctx_init(nv_device(priv), &priv->size); |
| 350 | if (ret) | ||
| 351 | return ret; | ||
| 350 | 352 | ||
| 351 | /* No context present currently */ | 353 | /* No context present currently */ |
| 352 | nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); | 354 | nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); |
| @@ -15,7 +15,7 @@ nv44_graph_class(void *priv) · 14 unmodified lines | |||
| 15 | return !(0x0baf & (1 << (device->chipset & 0x0f))); | 15 | return !(0x0baf & (1 << (device->chipset & 0x0f))); |
| 16 | } | 16 | } |
| 17 | 17 | ||
| 18 | void nv40_grctx_init(struct nouveau_device *, u32 *size); | 18 | int nv40_grctx_init(struct nouveau_device *, u32 *size); |
| 19 | void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); | 19 | void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); |
| 20 | 20 | ||
| 21 | #endif | 21 | #endif |