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Merge tag 'amd-drm-next-6.16-2025-05-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-6.16-2025-05-09: amdgpu: - IPS fixes - DSC cleanup - DC Scaling updates - DC FP fixes - Fused I2C-over-AUX updates - SubVP fixes - Freesync fix - DMUB AUX fixes - VCN fix - Hibernation fixes - HDP fixes - DCN 2.1 fixes - DPIA fixes - DMUB updates - Use drm_file_err in amdgpu - Enforce isolation updates - Use new dma_fence helpers - USERQ fixes - Documentation updates - Misc code cleanups - SR-IOV updates - RAS updates - PSP 12 cleanups amdkfd: - Update error messages for SDMA - Userptr updates drm: - Add drm_file_err function dma-buf: - Add a helper to sort and deduplicate dma_fence arrays

Dave Airlie committed 1 year ago

Commit 1faeeb32 parents f9fa012 afc6053338 files · +15952 −9761Browse files

Showing the changes to include/uapi (2 of 338 files). Show all

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2 files
  1. include/uapi/drm/amdgpu_drm.h +316 −0
  2. include/uapi/linux/kfd_ioctl.h +5 −0
include/uapi/drm/amdgpu_drm.h+316−0
@@ -54,6 +54,9 @@ extern "C" { · 53 unmodified lines
5454 #define DRM_AMDGPU_VM 0x13
5555 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
5656 #define DRM_AMDGPU_SCHED 0x15
57+#define DRM_AMDGPU_USERQ 0x16
58+#define DRM_AMDGPU_USERQ_SIGNAL 0x17
59+#define DRM_AMDGPU_USERQ_WAIT 0x18
5760
5861 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
5962 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -71,6 +74,9 @@ extern "C" { · 11 unmodified lines
7174 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
7275 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
7376 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
77+#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
78+#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
79+#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
7480
7581 /**
7682 * DOC: memory domains
@@ -319,6 +325,260 @@ union drm_amdgpu_ctx { · 242 unmodified lines
319325 union drm_amdgpu_ctx_out out;
320326 };
321327
328+/* user queue IOCTL operations */
329+#define AMDGPU_USERQ_OP_CREATE 1
330+#define AMDGPU_USERQ_OP_FREE 2
331+
332+/* queue priority levels */
333+/* low < normal low < normal high < high */
334+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3
335+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
336+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
337+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1
338+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2
339+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */
340+/* for queues that need access to protected content */
341+#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)
342+
343+/*
344+ * This structure is a container to pass input configuration
345+ * info for all supported userqueue related operations.
346+ * For operation AMDGPU_USERQ_OP_CREATE: user is expected
347+ * to set all fields, excep the parameter 'queue_id'.
348+ * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
349+ * to be set is 'queue_id', eveything else is ignored.
350+ */
351+struct drm_amdgpu_userq_in {
352+ /** AMDGPU_USERQ_OP_* */
353+ __u32 op;
354+ /** Queue id passed for operation USERQ_OP_FREE */
355+ __u32 queue_id;
356+ /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
357+ __u32 ip_type;
358+ /**
359+ * @doorbell_handle: the handle of doorbell GEM object
360+ * associated with this userqueue client.
361+ */
362+ __u32 doorbell_handle;
363+ /**
364+ * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
365+ * Kernel will generate absolute doorbell offset using doorbell_handle
366+ * and doorbell_offset in the doorbell bo.
367+ */
368+ __u32 doorbell_offset;
369+ /**
370+ * @flags: flags used for queue parameters
371+ */
372+ __u32 flags;
373+ /**
374+ * @queue_va: Virtual address of the GPU memory which holds the queue
375+ * object. The queue holds the workload packets.
376+ */
377+ __u64 queue_va;
378+ /**
379+ * @queue_size: Size of the queue in bytes, this needs to be 256-byte
380+ * aligned.
381+ */
382+ __u64 queue_size;
383+ /**
384+ * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
385+ * This object must be at least 8 byte in size and aligned to 8-byte offset.
386+ */
387+ __u64 rptr_va;
388+ /**
389+ * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
390+ * This object must be at least 8 byte in size and aligned to 8-byte offset.
391+ *
392+ * Queue, RPTR and WPTR can come from the same object, as long as the size
393+ * and alignment related requirements are met.
394+ */
395+ __u64 wptr_va;
396+ /**
397+ * @mqd: MQD (memory queue descriptor) is a set of parameters which allow
398+ * the GPU to uniquely define and identify a usermode queue.
399+ *
400+ * MQD data can be of different size for different GPU IP/engine and
401+ * their respective versions/revisions, so this points to a __u64 *
402+ * which holds IP specific MQD of this usermode queue.
403+ */
404+ __u64 mqd;
405+ /**
406+ * @size: size of MQD data in bytes, it must match the MQD structure
407+ * size of the respective engine/revision defined in UAPI for ex, for
408+ * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
409+ */
410+ __u64 mqd_size;
411+};
412+
413+/* The structure to carry output of userqueue ops */
414+struct drm_amdgpu_userq_out {
415+ /**
416+ * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
417+ * queue ID to represent the newly created userqueue in the system, otherwise
418+ * it should be ignored.
419+ */
420+ __u32 queue_id;
421+ __u32 _pad;
422+};
423+
424+union drm_amdgpu_userq {
425+ struct drm_amdgpu_userq_in in;
426+ struct drm_amdgpu_userq_out out;
427+};
428+
429+/* GFX V11 IP specific MQD parameters */
430+struct drm_amdgpu_userq_mqd_gfx11 {
431+ /**
432+ * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
433+ * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
434+ */
435+ __u64 shadow_va;
436+ /**
437+ * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
438+ * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
439+ */
440+ __u64 csa_va;
441+};
442+
443+/* GFX V11 SDMA IP specific MQD parameters */
444+struct drm_amdgpu_userq_mqd_sdma_gfx11 {
445+ /**
446+ * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
447+ * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
448+ * to get the size.
449+ */
450+ __u64 csa_va;
451+};
452+
453+/* GFX V11 Compute IP specific MQD parameters */
454+struct drm_amdgpu_userq_mqd_compute_gfx11 {
455+ /**
456+ * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
457+ * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
458+ * to get the size.
459+ */
460+ __u64 eop_va;
461+};
462+
463+/* userq signal/wait ioctl */
464+struct drm_amdgpu_userq_signal {
465+ /**
466+ * @queue_id: Queue handle used by the userq fence creation function
467+ * to retrieve the WPTR.
468+ */
469+ __u32 queue_id;
470+ __u32 pad;
471+ /**
472+ * @syncobj_handles: The list of syncobj handles submitted by the user queue
473+ * job to be signaled.
474+ */
475+ __u64 syncobj_handles;
476+ /**
477+ * @num_syncobj_handles: A count that represents the number of syncobj handles in
478+ * @syncobj_handles.
479+ */
480+ __u64 num_syncobj_handles;
481+ /**
482+ * @bo_read_handles: The list of BO handles that the submitted user queue job
483+ * is using for read only. This will update BO fences in the kernel.
484+ */
485+ __u64 bo_read_handles;
486+ /**
487+ * @bo_write_handles: The list of BO handles that the submitted user queue job
488+ * is using for write only. This will update BO fences in the kernel.
489+ */
490+ __u64 bo_write_handles;
491+ /**
492+ * @num_bo_read_handles: A count that represents the number of read BO handles in
493+ * @bo_read_handles.
494+ */
495+ __u32 num_bo_read_handles;
496+ /**
497+ * @num_bo_write_handles: A count that represents the number of write BO handles in
498+ * @bo_write_handles.
499+ */
500+ __u32 num_bo_write_handles;
501+};
502+
503+struct drm_amdgpu_userq_fence_info {
504+ /**
505+ * @va: A gpu address allocated for each queue which stores the
506+ * read pointer (RPTR) value.
507+ */
508+ __u64 va;
509+ /**
510+ * @value: A 64 bit value represents the write pointer (WPTR) of the
511+ * queue commands which compared with the RPTR value to signal the
512+ * fences.
513+ */
514+ __u64 value;
515+};
516+
517+struct drm_amdgpu_userq_wait {
518+ /**
519+ * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the
520+ * wait queue and maintain the fence driver references in it.
521+ */
522+ __u32 waitq_id;
523+ __u32 pad;
524+ /**
525+ * @syncobj_handles: The list of syncobj handles submitted by the user queue
526+ * job to get the va/value pairs.
527+ */
528+ __u64 syncobj_handles;
529+ /**
530+ * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
531+ * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
532+ */
533+ __u64 syncobj_timeline_handles;
534+ /**
535+ * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
536+ * user queue job for the corresponding @syncobj_timeline_handles.
537+ */
538+ __u64 syncobj_timeline_points;
539+ /**
540+ * @bo_read_handles: The list of read BO handles submitted by the user queue
541+ * job to get the va/value pairs.
542+ */
543+ __u64 bo_read_handles;
544+ /**
545+ * @bo_write_handles: The list of write BO handles submitted by the user queue
546+ * job to get the va/value pairs.
547+ */
548+ __u64 bo_write_handles;
549+ /**
550+ * @num_syncobj_timeline_handles: A count that represents the number of timeline
551+ * syncobj handles in @syncobj_timeline_handles.
552+ */
553+ __u16 num_syncobj_timeline_handles;
554+ /**
555+ * @num_fences: This field can be used both as input and output. As input it defines
556+ * the maximum number of fences that can be returned and as output it will specify
557+ * how many fences were actually returned from the ioctl.
558+ */
559+ __u16 num_fences;
560+ /**
561+ * @num_syncobj_handles: A count that represents the number of syncobj handles in
562+ * @syncobj_handles.
563+ */
564+ __u32 num_syncobj_handles;
565+ /**
566+ * @num_bo_read_handles: A count that represents the number of read BO handles in
567+ * @bo_read_handles.
568+ */
569+ __u32 num_bo_read_handles;
570+ /**
571+ * @num_bo_write_handles: A count that represents the number of write BO handles in
572+ * @bo_write_handles.
573+ */
574+ __u32 num_bo_write_handles;
575+ /**
576+ * @out_fences: The field is a return value from the ioctl containing the list of
577+ * address/value pairs to wait for.
578+ */
579+ __u64 out_fences;
580+};
581+
322582 /* vm ioctl */
323583 #define AMDGPU_VM_OP_RESERVE_VMID 1
324584 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
@@ -599,6 +859,19 @@ struct drm_amdgpu_gem_va { · 274 unmodified lines
599859 __u64 offset_in_bo;
600860 /** Specify mapping size. Must be correctly aligned. */
601861 __u64 map_size;
862+ /**
863+ * vm_timeline_point is a sequence number used to add new timeline point.
864+ */
865+ __u64 vm_timeline_point;
866+ /**
867+ * The vm page table update fence is installed in given vm_timeline_syncobj_out
868+ * at vm_timeline_point.
869+ */
870+ __u32 vm_timeline_syncobj_out;
871+ /** the number of syncobj handles in @input_fence_syncobj_handles */
872+ __u32 num_syncobj_handles;
873+ /** Array of sync object handle to wait for given input fences */
874+ __u64 input_fence_syncobj_handles;
602875 };
603876
604877 #define AMDGPU_HW_IP_GFX 0
@@ -940,6 +1213,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { · 335 unmodified lines
9401213 #define AMDGPU_INFO_MAX_IBS 0x22
9411214 /* query last page fault info */
9421215 #define AMDGPU_INFO_GPUVM_FAULT 0x23
1216+/* query FW object size and alignment */
1217+#define AMDGPU_INFO_UQ_FW_AREAS 0x24
9431218
9441219 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
9451220 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -1198,6 +1473,9 @@ struct drm_amdgpu_info_device { · 252 unmodified lines
11981473 __u32 csa_size;
11991474 /* context save area base virtual alignment for gfx11 */
12001475 __u32 csa_alignment;
1476+ /* Userq IP mask (1 << AMDGPU_HW_IP_*) */
1477+ __u32 userq_ip_mask;
1478+ __u32 pad;
12011479 };
12021480
12031481 struct drm_amdgpu_info_hw_ip {
@@ -1216,6 +1494,27 @@ struct drm_amdgpu_info_hw_ip { · 12 unmodified lines
12161494 __u32 ip_discovery_version;
12171495 };
12181496
1497+/* GFX metadata BO sizes and alignment info (in bytes) */
1498+struct drm_amdgpu_info_uq_fw_areas_gfx {
1499+ /* shadow area size */
1500+ __u32 shadow_size;
1501+ /* shadow area base virtual mem alignment */
1502+ __u32 shadow_alignment;
1503+ /* context save area size */
1504+ __u32 csa_size;
1505+ /* context save area base virtual mem alignment */
1506+ __u32 csa_alignment;
1507+};
1508+
1509+/* IP specific fw related information used in the
1510+ * subquery AMDGPU_INFO_UQ_FW_AREAS
1511+ */
1512+struct drm_amdgpu_info_uq_fw_areas {
1513+ union {
1514+ struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
1515+ };
1516+};
1517+
12191518 struct drm_amdgpu_info_num_handles {
12201519 /** Max handles as supported by firmware for UVD */
12211520 __u32 uvd_max_handles;
@@ -1279,6 +1578,23 @@ struct drm_amdgpu_info_gpuvm_fault { · 57 unmodified lines
12791578 __u32 vmhub;
12801579 };
12811580
1581+struct drm_amdgpu_info_uq_metadata_gfx {
1582+ /* shadow area size for gfx11 */
1583+ __u32 shadow_size;
1584+ /* shadow area base virtual alignment for gfx11 */
1585+ __u32 shadow_alignment;
1586+ /* context save area size for gfx11 */
1587+ __u32 csa_size;
1588+ /* context save area base virtual alignment for gfx11 */
1589+ __u32 csa_alignment;
1590+};
1591+
1592+struct drm_amdgpu_info_uq_metadata {
1593+ union {
1594+ struct drm_amdgpu_info_uq_metadata_gfx gfx;
1595+ };
1596+};
1597+
12821598 /*
12831599 * Supported GPU families
12841600 */
include/uapi/linux/kfd_ioctl.h+5−0
@@ -536,6 +536,8 @@ enum kfd_smi_event { · 535 unmodified lines
536536 KFD_SMI_EVENT_QUEUE_EVICTION = 9,
537537 KFD_SMI_EVENT_QUEUE_RESTORE = 10,
538538 KFD_SMI_EVENT_UNMAP_FROM_GPU = 11,
539+ KFD_SMI_EVENT_PROCESS_START = 12,
540+ KFD_SMI_EVENT_PROCESS_END = 13,
539541
540542 /*
541543 * max event number, as a flag bit to get events from all processes,
@@ -651,6 +653,9 @@ struct kfd_ioctl_smi_events_args { · 109 unmodified lines
651653 "%lld -%d @%lx(%lx) %x %d\n", (ns), (pid), (addr), (size),\
652654 (node), (unmap_trigger)
653655
656+#define KFD_EVENT_FMT_PROCESS(pid, task_name)\
657+ "%x %s\n", (pid), (task_name)
658+
654659 /**************************************************************************************************
655660 * CRIU IOCTLs (Checkpoint Restore In Userspace)
656661 *