The V4L2_MBUS_CSI2_*_LANE flags are a legacy API and are unused. Drop them.
Unified · Split
| @@ -21,8 +21,6 @@ · 20 unmodified lines | |||
| 21 | * clear both the V4L2_MBUS_HSYNC_ACTIVE_HIGH and the | 21 | * clear both the V4L2_MBUS_HSYNC_ACTIVE_HIGH and the |
| 22 | * V4L2_MBUS_HSYNC_ACTIVE_LOW flag at the same time. Instead either flag | 22 | * V4L2_MBUS_HSYNC_ACTIVE_LOW flag at the same time. Instead either flag |
| 23 | * V4L2_MBUS_HSYNC_ACTIVE_HIGH or flag V4L2_MBUS_HSYNC_ACTIVE_LOW shall be set. | 23 | * V4L2_MBUS_HSYNC_ACTIVE_HIGH or flag V4L2_MBUS_HSYNC_ACTIVE_LOW shall be set. |
| 24 | * The same is true for the V4L2_MBUS_CSI2_1/2/3/4_LANE flags group: only one | ||
| 25 | * of these four bits shall be set. | ||
| 26 | * | 24 | * |
| 27 | * TODO: replace the existing V4L2_MBUS_* flags with structures of fields | 25 | * TODO: replace the existing V4L2_MBUS_* flags with structures of fields |
| 28 | * to avoid conflicting settings. | 26 | * to avoid conflicting settings. |
| @@ -69,11 +67,6 @@ · 40 unmodified lines | |||
| 69 | #define V4L2_MBUS_DATA_ENABLE_LOW BIT(15) | 67 | #define V4L2_MBUS_DATA_ENABLE_LOW BIT(15) |
| 70 | 68 | ||
| 71 | /* Serial flags */ | 69 | /* Serial flags */ |
| 72 | /* CSI-2 D-PHY number of data lanes. */ | ||
| 73 | #define V4L2_MBUS_CSI2_1_LANE BIT(0) | ||
| 74 | #define V4L2_MBUS_CSI2_2_LANE BIT(1) | ||
| 75 | #define V4L2_MBUS_CSI2_3_LANE BIT(2) | ||
| 76 | #define V4L2_MBUS_CSI2_4_LANE BIT(3) | ||
| 77 | /* CSI-2 Virtual Channel identifiers. */ | 70 | /* CSI-2 Virtual Channel identifiers. */ |
| 78 | #define V4L2_MBUS_CSI2_CHANNEL_0 BIT(4) | 71 | #define V4L2_MBUS_CSI2_CHANNEL_0 BIT(4) |
| 79 | #define V4L2_MBUS_CSI2_CHANNEL_1 BIT(5) | 72 | #define V4L2_MBUS_CSI2_CHANNEL_1 BIT(5) |
| @@ -83,10 +76,6 @@ · 3 unmodified lines | |||
| 83 | #define V4L2_MBUS_CSI2_CONTINUOUS_CLOCK BIT(8) | 76 | #define V4L2_MBUS_CSI2_CONTINUOUS_CLOCK BIT(8) |
| 84 | #define V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK BIT(9) | 77 | #define V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK BIT(9) |
| 85 | 78 | ||
| 86 | #define V4L2_MBUS_CSI2_LANES (V4L2_MBUS_CSI2_1_LANE | \ | ||
| 87 | V4L2_MBUS_CSI2_2_LANE | \ | ||
| 88 | V4L2_MBUS_CSI2_3_LANE | \ | ||
| 89 | V4L2_MBUS_CSI2_4_LANE) | ||
| 90 | #define V4L2_MBUS_CSI2_CHANNELS (V4L2_MBUS_CSI2_CHANNEL_0 | \ | 79 | #define V4L2_MBUS_CSI2_CHANNELS (V4L2_MBUS_CSI2_CHANNEL_0 | \ |
| 91 | V4L2_MBUS_CSI2_CHANNEL_1 | \ | 80 | V4L2_MBUS_CSI2_CHANNEL_1 | \ |
| 92 | V4L2_MBUS_CSI2_CHANNEL_2 | \ | 81 | V4L2_MBUS_CSI2_CHANNEL_2 | \ |