Add the required support for the ESPI range, which behave exactly like the SPIs of old, only with new funky INTIDs.
Showing the changes to include/linux (1 of 2 files). Show all
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| @@ -30,10 +30,22 @@ · 29 unmodified lines | ||
| 30 | 30 | #define GICD_ICFGR 0x0C00 |
| 31 | 31 | #define GICD_IGRPMODR 0x0D00 |
| 32 | 32 | #define GICD_NSACR 0x0E00 |
| 33 | +#define GICD_IGROUPRnE 0x1000 | |
| 34 | +#define GICD_ISENABLERnE 0x1200 | |
| 35 | +#define GICD_ICENABLERnE 0x1400 | |
| 36 | +#define GICD_ISPENDRnE 0x1600 | |
| 37 | +#define GICD_ICPENDRnE 0x1800 | |
| 38 | +#define GICD_ISACTIVERnE 0x1A00 | |
| 39 | +#define GICD_ICACTIVERnE 0x1C00 | |
| 40 | +#define GICD_IPRIORITYRnE 0x2000 | |
| 41 | +#define GICD_ICFGRnE 0x3000 | |
| 33 | 42 | #define GICD_IROUTER 0x6000 |
| 43 | +#define GICD_IROUTERnE 0x8000 | |
| 34 | 44 | #define GICD_IDREGS 0xFFD0 |
| 35 | 45 | #define GICD_PIDR2 0xFFE8 |
| 36 | 46 | |
| 47 | +#define ESPI_BASE_INTID 4096 | |
| 48 | + | |
| 37 | 49 | /* |
| 38 | 50 | * Those registers are actually from GICv2, but the spec demands that they |
| 39 | 51 | * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). |
| @@ -69,10 +81,13 @@ · 29 unmodified lines | ||
| 69 | 81 | #define GICD_TYPER_RSS (1U << 26) |
| 70 | 82 | #define GICD_TYPER_LPIS (1U << 17) |
| 71 | 83 | #define GICD_TYPER_MBIS (1U << 16) |
| 84 | +#define GICD_TYPER_ESPI (1U << 8) | |
| 72 | 85 | |
| 73 | 86 | #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) |
| 74 | 87 | #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) |
| 75 | −#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) | |
| 88 | +#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) | |
| 89 | +#define GICD_TYPER_ESPIS(typer) \ | |
| 90 | + (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) | |
| 76 | 91 | |
| 77 | 92 | #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) |
| 78 | 93 | #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) |