History

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas: - Errata workarounds for Cortex-A510: broken hardware dirty bit management, detection code for the TRBE (tracing) bugs with the actual fixes going in via the CoreSight tree. - Cortex-X2 errata handling for TRBE (inheriting the workarounds from Cortex-A710). - Fix ex_handler_load_unaligned_zeropad() to use the correct struct members. - A couple of kselftest fixes for FPSIMD. - Silence the vdso "no previous prototype" warning. - Mark start_backtrace() notrace and NOKPROBE_SYMBOL. * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: cpufeature: List early Cortex-A510 parts as having broken dbm kselftest/arm64: Correct logging of FPSIMD register read via ptrace kselftest/arm64: Skip VL_INHERIT tests for unsupported vector types arm64: errata: Add detection for TRBE trace data corruption arm64: errata: Add detection for TRBE invalid prohibited states arm64: errata: Add detection for TRBE ignored system register writes arm64: Add Cortex-A510 CPU part definition arm64: extable: fix load_unaligned_zeropad() reg indices arm64: Mark start_backtrace() notrace and NOKPROBE_SYMBOL arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges arm64: Add Cortex-X2 CPU part definition arm64: vdso: Fix "no previous prototype" warning

Linus Torvalds committed 4 years ago

Commit 216e2ae2 parents d1e7f09 297ae1e10 files · +144 −13Browse files

Unified · Split

10 files
  1. Documentation/arm64/silicon-errata.rst +12 −0
  2. arch/arm64/Kconfig +75 −6
  3. arch/arm64/include/asm/cputype.h +4 −0
  4. arch/arm64/kernel/cpu_errata.c +29 −0
  5. arch/arm64/kernel/cpufeature.c +3 −0
  6. arch/arm64/kernel/stacktrace.c +3 −2
  7. arch/arm64/kernel/vdso/Makefile +4 −1
  8. arch/arm64/mm/extable.c +2 −2
  9. arch/arm64/tools/cpucaps +3 −0
  10. tools/testing/selftests/arm64/fp/sve-ptrace.c +9 −2
Documentation/arm64/silicon-errata.rst+12−0
@@ -52,6 +52,12 @@ stable kernels. · 51 unmodified lines
52| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |52| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
53+----------------+-----------------+-----------------+-----------------------------+53+----------------+-----------------+-----------------+-----------------------------+
54+----------------+-----------------+-----------------+-----------------------------+54+----------------+-----------------+-----------------+-----------------------------+
55| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
56+----------------+-----------------+-----------------+-----------------------------+
57| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
58+----------------+-----------------+-----------------+-----------------------------+
59| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
60+----------------+-----------------+-----------------+-----------------------------+
55| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |61| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
56+----------------+-----------------+-----------------+-----------------------------+62+----------------+-----------------+-----------------+-----------------------------+
57| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |63| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
@@ -92,12 +98,18 @@ stable kernels. · 34 unmodified lines
92+----------------+-----------------+-----------------+-----------------------------+98+----------------+-----------------+-----------------+-----------------------------+
93| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |99| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
94+----------------+-----------------+-----------------+-----------------------------+100+----------------+-----------------+-----------------+-----------------------------+
101| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
102+----------------+-----------------+-----------------+-----------------------------+
95| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |103| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
96+----------------+-----------------+-----------------+-----------------------------+104+----------------+-----------------+-----------------+-----------------------------+
97| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |105| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
98+----------------+-----------------+-----------------+-----------------------------+106+----------------+-----------------+-----------------+-----------------------------+
99| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |107| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
100+----------------+-----------------+-----------------+-----------------------------+108+----------------+-----------------+-----------------+-----------------------------+
109| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
110+----------------+-----------------+-----------------+-----------------------------+
111| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
112+----------------+-----------------+-----------------+-----------------------------+
101| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |113| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
102+----------------+-----------------+-----------------+-----------------------------+114+----------------+-----------------+-----------------+-----------------------------+
103| ARM | Neoverse-N1 | #1349291 | N/A |115| ARM | Neoverse-N1 | #1349291 | N/A |
arch/arm64/Kconfig+75−6
@@ -670,15 +670,25 @@ config ARM64_ERRATUM_1508412 · 669 unmodified lines
670config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE670config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
671 bool671 bool
672 672
673config ARM64_ERRATUM_2051678
674 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
675 help
676 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
677 Affected Coretex-A510 might not respect the ordering rules for
678 hardware update of the page table's dirty bit. The workaround
679 is to not enable the feature on affected CPUs.
680
681 If unsure, say Y.
682
673config ARM64_ERRATUM_2119858683config ARM64_ERRATUM_2119858
674 bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"684 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
675 default y685 default y
676 depends on CORESIGHT_TRBE686 depends on CORESIGHT_TRBE
677 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE687 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
678 help688 help
679 This option adds the workaround for ARM Cortex-A710 erratum 2119858.689 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
680 690
681 Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace691 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
682 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in692 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
683 the event of a WRAP event.693 the event of a WRAP event.
684 694
@@ -761,14 +771,14 @@ config ARM64_ERRATUM_2253138 · 76 unmodified lines
761 If unsure, say Y.771 If unsure, say Y.
762 772
763config ARM64_ERRATUM_2224489773config ARM64_ERRATUM_2224489
764 bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"774 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
765 depends on CORESIGHT_TRBE775 depends on CORESIGHT_TRBE
766 default y776 default y
767 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE777 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
768 help778 help
769 This option adds the workaround for ARM Cortex-A710 erratum 2224489.779 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
770 780
771 Affected Cortex-A710 cores might write to an out-of-range address, not reserved781 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
772 for TRBE. Under some conditions, the TRBE might generate a write to the next782 for TRBE. Under some conditions, the TRBE might generate a write to the next
773 virtually addressed page following the last page of the TRBE address space783 virtually addressed page following the last page of the TRBE address space
774 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.784 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
@@ -778,6 +788,65 @@ config ARM64_ERRATUM_2224489 · 3 unmodified lines
778 788
779 If unsure, say Y.789 If unsure, say Y.
780 790
791config ARM64_ERRATUM_2064142
792 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
793 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
794 default y
795 help
796 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
797
798 Affected Cortex-A510 core might fail to write into system registers after the
799 TRBE has been disabled. Under some conditions after the TRBE has been disabled
800 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
801 and TRBTRG_EL1 will be ignored and will not be effected.
802
803 Work around this in the driver by executing TSB CSYNC and DSB after collection
804 is stopped and before performing a system register write to one of the affected
805 registers.
806
807 If unsure, say Y.
808
809config ARM64_ERRATUM_2038923
810 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
811 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
812 default y
813 help
814 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
815
816 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
817 prohibited within the CPU. As a result, the trace buffer or trace buffer state
818 might be corrupted. This happens after TRBE buffer has been enabled by setting
819 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
820 execution changes from a context, in which trace is prohibited to one where it
821 isn't, or vice versa. In these mentioned conditions, the view of whether trace
822 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
823 the trace buffer state might be corrupted.
824
825 Work around this in the driver by preventing an inconsistent view of whether the
826 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
827 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
828 two ISB instructions if no ERET is to take place.
829
830 If unsure, say Y.
831
832config ARM64_ERRATUM_1902691
833 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
834 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
835 default y
836 help
837 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
838
839 Affected Cortex-A510 core might cause trace data corruption, when being written
840 into the memory. Effectively TRBE is broken and hence cannot be used to capture
841 trace data.
842
843 Work around this problem in the driver by just preventing TRBE initialization on
844 affected cpus. The firmware must have disabled the access to TRBE for the kernel
845 on such implementations. This will cover the kernel for any firmware that doesn't
846 do this already.
847
848 If unsure, say Y.
849
781config CAVIUM_ERRATUM_22375850config CAVIUM_ERRATUM_22375
782 bool "Cavium erratum 22375, 24313"851 bool "Cavium erratum 22375, 24313"
783 default y852 default y
arch/arm64/include/asm/cputype.h+4−0
@@ -73,7 +73,9 @@ · 72 unmodified lines
73#define ARM_CPU_PART_CORTEX_A76 0xD0B73#define ARM_CPU_PART_CORTEX_A76 0xD0B
74#define ARM_CPU_PART_NEOVERSE_N1 0xD0C74#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
75#define ARM_CPU_PART_CORTEX_A77 0xD0D75#define ARM_CPU_PART_CORTEX_A77 0xD0D
76#define ARM_CPU_PART_CORTEX_A510 0xD46
76#define ARM_CPU_PART_CORTEX_A710 0xD4777#define ARM_CPU_PART_CORTEX_A710 0xD47
78#define ARM_CPU_PART_CORTEX_X2 0xD48
77#define ARM_CPU_PART_NEOVERSE_N2 0xD4979#define ARM_CPU_PART_NEOVERSE_N2 0xD49
78 80
79#define APM_CPU_PART_POTENZA 0x00081#define APM_CPU_PART_POTENZA 0x000
@@ -115,7 +117,9 @@ · 35 unmodified lines
115#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)117#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
116#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)118#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
117#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)119#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
120#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
118#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)121#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
122#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
119#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)123#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
120#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)124#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
121#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)125#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
arch/arm64/kernel/cpu_errata.c+29−0
@@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { · 346 unmodified lines
347#endif347#endif
348#ifdef CONFIG_ARM64_ERRATUM_2119858348#ifdef CONFIG_ARM64_ERRATUM_2119858
349 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),349 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
350 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
350#endif351#endif
351 {},352 {},
352};353};
@@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { · 18 unmodified lines
371#endif372#endif
372#ifdef CONFIG_ARM64_ERRATUM_2224489373#ifdef CONFIG_ARM64_ERRATUM_2224489
373 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),374 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
375 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
374#endif376#endif
375 {},377 {},
376};378};
@@ -597,6 +599,33 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 220 unmodified lines
597 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,599 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
598 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),600 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
599 },601 },
602#endif
603#ifdef CONFIG_ARM64_ERRATUM_2064142
604 {
605 .desc = "ARM erratum 2064142",
606 .capability = ARM64_WORKAROUND_2064142,
607
608 /* Cortex-A510 r0p0 - r0p2 */
609 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
610 },
611#endif
612#ifdef CONFIG_ARM64_ERRATUM_2038923
613 {
614 .desc = "ARM erratum 2038923",
615 .capability = ARM64_WORKAROUND_2038923,
616
617 /* Cortex-A510 r0p0 - r0p2 */
618 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
619 },
620#endif
621#ifdef CONFIG_ARM64_ERRATUM_1902691
622 {
623 .desc = "ARM erratum 1902691",
624 .capability = ARM64_WORKAROUND_1902691,
625
626 /* Cortex-A510 r0p0 - r0p1 */
627 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
628 },
600#endif629#endif
601 {630 {
602 }631 }
arch/arm64/kernel/cpufeature.c+3−0
@@ -1645,6 +1645,9 @@ static bool cpu_has_broken_dbm(void) · 1644 unmodified lines
1645 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),1645 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1646 /* Kryo4xx Silver (rdpe => r1p0) */1646 /* Kryo4xx Silver (rdpe => r1p0) */
1647 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),1647 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1648#endif
1649#ifdef CONFIG_ARM64_ERRATUM_2051678
1650 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1648#endif1651#endif
1649 {},1652 {},
1650 };1653 };
arch/arm64/kernel/stacktrace.c+3−2
@@ -33,8 +33,8 @@ · 32 unmodified lines
33 */33 */
34 34
35 35
36static void start_backtrace(struct stackframe *frame, unsigned long fp,36static notrace void start_backtrace(struct stackframe *frame, unsigned long fp,
37 unsigned long pc)37 unsigned long pc)
38{38{
39 frame->fp = fp;39 frame->fp = fp;
40 frame->pc = pc;40 frame->pc = pc;
@@ -55,6 +55,7 @@ static void start_backtrace(struct stackframe *frame, unsigned long fp, · 14 unmodified lines
55 frame->prev_fp = 0;55 frame->prev_fp = 0;
56 frame->prev_type = STACK_TYPE_UNKNOWN;56 frame->prev_type = STACK_TYPE_UNKNOWN;
57}57}
58NOKPROBE_SYMBOL(start_backtrace);
58 59
59/*60/*
60 * Unwind from one frame record (A) to the next frame record (B).61 * Unwind from one frame record (A) to the next frame record (B).
arch/arm64/kernel/vdso/Makefile+4−1
@@ -29,8 +29,11 @@ ldflags-y := -shared -soname=linux-vdso.so.1 --hash-style=sysv \ · 28 unmodified lines
29ccflags-y := -fno-common -fno-builtin -fno-stack-protector -ffixed-x1829ccflags-y := -fno-common -fno-builtin -fno-stack-protector -ffixed-x18
30ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO30ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO
31 31
32# -Wmissing-prototypes and -Wmissing-declarations are removed from
33# the CFLAGS of vgettimeofday.c to make possible to build the
34# kernel with CONFIG_WERROR enabled.
32CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) -Os $(CC_FLAGS_SCS) $(GCC_PLUGINS_CFLAGS) \35CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) -Os $(CC_FLAGS_SCS) $(GCC_PLUGINS_CFLAGS) \
33 $(CC_FLAGS_LTO)36 $(CC_FLAGS_LTO) -Wmissing-prototypes -Wmissing-declarations
34KASAN_SANITIZE := n37KASAN_SANITIZE := n
35KCSAN_SANITIZE := n38KCSAN_SANITIZE := n
36UBSAN_SANITIZE := n39UBSAN_SANITIZE := n
arch/arm64/mm/extable.c+2−2
@@ -40,8 +40,8 @@ static bool · 39 unmodified lines
40ex_handler_load_unaligned_zeropad(const struct exception_table_entry *ex,40ex_handler_load_unaligned_zeropad(const struct exception_table_entry *ex,
41 struct pt_regs *regs)41 struct pt_regs *regs)
42{42{
43 int reg_data = FIELD_GET(EX_DATA_REG_DATA, ex->type);43 int reg_data = FIELD_GET(EX_DATA_REG_DATA, ex->data);
44 int reg_addr = FIELD_GET(EX_DATA_REG_ADDR, ex->type);44 int reg_addr = FIELD_GET(EX_DATA_REG_ADDR, ex->data);
45 unsigned long data, addr, offset;45 unsigned long data, addr, offset;
46 46
47 addr = pt_regs_read_reg(regs, reg_addr);47 addr = pt_regs_read_reg(regs, reg_addr);
arch/arm64/tools/cpucaps+3−0
@@ -55,6 +55,9 @@ WORKAROUND_1418040 · 54 unmodified lines
55WORKAROUND_146322555WORKAROUND_1463225
56WORKAROUND_150841256WORKAROUND_1508412
57WORKAROUND_154241957WORKAROUND_1542419
58WORKAROUND_2064142
59WORKAROUND_2038923
60WORKAROUND_1902691
58WORKAROUND_TRBE_OVERWRITE_FILL_MODE61WORKAROUND_TRBE_OVERWRITE_FILL_MODE
59WORKAROUND_TSB_FLUSH_FAILURE62WORKAROUND_TSB_FLUSH_FAILURE
60WORKAROUND_TRBE_WRITE_OUT_OF_RANGE63WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
tools/testing/selftests/arm64/fp/sve-ptrace.c+9−2
@@ -261,7 +261,7 @@ static void ptrace_sve_fpsimd(pid_t child, const struct vec_type *type) · 260 unmodified lines
261 }261 }
262 262
263 ksft_test_result((sve->flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD,263 ksft_test_result((sve->flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD,
264 "Set FPSIMD registers via %s\n", type->name);264 "Got FPSIMD registers via %s\n", type->name);
265 if ((sve->flags & SVE_PT_REGS_MASK) != SVE_PT_REGS_FPSIMD)265 if ((sve->flags & SVE_PT_REGS_MASK) != SVE_PT_REGS_FPSIMD)
266 goto out;266 goto out;
267 267
@@ -557,7 +557,14 @@ static int do_parent(pid_t child) · 289 unmodified lines
557 }557 }
558 558
559 /* prctl() flags */559 /* prctl() flags */
560 ptrace_set_get_inherit(child, &vec_types[i]);560 if (getauxval(vec_types[i].hwcap_type) & vec_types[i].hwcap) {
561 ptrace_set_get_inherit(child, &vec_types[i]);
562 } else {
563 ksft_test_result_skip("%s SVE_PT_VL_INHERIT set\n",
564 vec_types[i].name);
565 ksft_test_result_skip("%s SVE_PT_VL_INHERIT cleared\n",
566 vec_types[i].name);
567 }
561 568
562 /* Step through every possible VQ */569 /* Step through every possible VQ */
563 for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; vq++) {570 for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; vq++) {