History

Merge tag 'drm-fixes-2019-08-09' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "Usual fixes roundup. Nothing too crazy or serious, one non-released ioctl is removed in the amdkfd driver. core: - mode parser strncpy fix i915: - GLK DSI escape clock setting - HDCP memleak fix tegra: - one gpiod/of regression fix amdgpu: - fix VCN to handle the latest navi10 firmware - fix for fan control on navi10 - properly handle SMU metrics table on navi10 - fix a resume regression on Stoney - kfd revert a GWS ioctl vmwgfx: - memory leak fix rockchip: - suspend fix" * tag 'drm-fixes-2019-08-09' of git://anongit.freedesktop.org/drm/drm: drm/vmwgfx: fix memory leak when too many retries have occurred Revert "drm/amdkfd: New IOCTL to allocate queue GWS" Revert "drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)" drm/amdgpu: pin the csb buffer on hw init for gfx v8 drm/rockchip: Suspend DP late drm/i915: Fix wrong escape clock divisor init for GLK drm/i915: fix possible memory leak in intel_hdcp_auth_downstream() drm/modes: Fix unterminated strncpy drm/amd/powerplay: correct navi10 vcn powergate drm/amd/powerplay: honor hw limit on fetching metrics data for navi10 drm/amd/powerplay: Allow changing of fan_control in smu_v11_0 drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0 drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands drm/tegra: Fix gpiod_get_from_of_node() regression

Linus Torvalds committed 7 years ago

Commit 2226fb52 parents 15a555a a111ef617 files · +155 −102Browse files

Unified · Split

17 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h +0 −1
  2. drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +1 −0
  3. drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +1 −11
  4. drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +40 −0
  5. drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +37 −7
  6. drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +0 −28
  7. drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +3 −1
  8. drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +1 −0
  9. drivers/gpu/drm/amd/powerplay/navi10_ppt.c +53 −26
  10. drivers/gpu/drm/amd/powerplay/smu_v11_0.c +1 −1
  11. drivers/gpu/drm/drm_modes.c +3 −1
  12. drivers/gpu/drm/i915/display/intel_hdcp.c +2 −1
  13. drivers/gpu/drm/i915/display/vlv_dsi_pll.c +2 −2
  14. drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +1 −1
  15. drivers/gpu/drm/tegra/output.c +6 −2
  16. drivers/gpu/drm/vmwgfx/vmwgfx_msg.c +3 −1
  17. include/uapi/linux/kfd_ioctl.h +1 −19
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h+0−1
@@ -32,7 +32,6 @@ struct amdgpu_gds { · 31 unmodified lines
32 uint32_t gws_size;32 uint32_t gws_size;
33 uint32_t oa_size;33 uint32_t oa_size;
34 uint32_t gds_compute_max_wave_id;34 uint32_t gds_compute_max_wave_id;
35 uint32_t vgt_gs_max_wave_id;
36};35};
37 36
38struct amdgpu_gds_reg_offset {37struct amdgpu_gds_reg_offset {
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h+1−0
@@ -30,6 +30,7 @@ · 29 unmodified lines
30#define AMDGPU_VCN_FIRMWARE_OFFSET 25630#define AMDGPU_VCN_FIRMWARE_OFFSET 256
31#define AMDGPU_VCN_MAX_ENC_RINGS 331#define AMDGPU_VCN_MAX_ENC_RINGS 3
32 32
33#define VCN_DEC_KMD_CMD 0x80000000
33#define VCN_DEC_CMD_FENCE 0x0000000034#define VCN_DEC_CMD_FENCE 0x00000000
34#define VCN_DEC_CMD_TRAP 0x0000000135#define VCN_DEC_CMD_TRAP 0x00000001
35#define VCN_DEC_CMD_WRITE_REG 0x0000000436#define VCN_DEC_CMD_WRITE_REG 0x00000004
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+1−11
@@ -4206,15 +4206,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, · 4205 unmodified lines
4206 unsigned vmid = AMDGPU_JOB_GET_VMID(job);4206 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4207 u32 header, control = 0;4207 u32 header, control = 0;
4208 4208
4209 /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
4210 * This resets the wave ID counters. (needed by transform feedback)
4211 * TODO: This might only be needed on a VMID switch when we change
4212 * the GDS OA mapping, not sure.
4213 */
4214 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4215 amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
4216 amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
4217
4218 if (ib->flags & AMDGPU_IB_FLAG_CE)4209 if (ib->flags & AMDGPU_IB_FLAG_CE)
4219 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);4210 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4220 else4211 else
@@ -4961,7 +4952,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { · 740 unmodified lines
4961 5 + /* HDP_INVL */4952 5 + /* HDP_INVL */
4962 8 + 8 + /* FENCE x2 */4953 8 + 8 + /* FENCE x2 */
4963 2, /* SWITCH_BUFFER */4954 2, /* SWITCH_BUFFER */
4964 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */4955 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
4965 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,4956 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
4966 .emit_fence = gfx_v10_0_ring_emit_fence,4957 .emit_fence = gfx_v10_0_ring_emit_fence,
4967 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,4958 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
@@ -5112,7 +5103,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) · 144 unmodified lines
5112 default:5103 default:
5113 adev->gds.gds_size = 0x10000;5104 adev->gds.gds_size = 0x10000;
5114 adev->gds.gds_compute_max_wave_id = 0x4ff;5105 adev->gds.gds_compute_max_wave_id = 0x4ff;
5115 adev->gds.vgt_gs_max_wave_id = 0x3ff;
5116 break;5106 break;
5117 }5107 }
5118 5108
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+40−0
@@ -1321,6 +1321,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) · 1320 unmodified lines
1321 return 0;1321 return 0;
1322}1322}
1323 1323
1324static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
1325{
1326 int r;
1327
1328 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1329 if (unlikely(r != 0))
1330 return r;
1331
1332 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1333 AMDGPU_GEM_DOMAIN_VRAM);
1334 if (!r)
1335 adev->gfx.rlc.clear_state_gpu_addr =
1336 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1337
1338 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1339
1340 return r;
1341}
1342
1343static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
1344{
1345 int r;
1346
1347 if (!adev->gfx.rlc.clear_state_obj)
1348 return;
1349
1350 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1351 if (likely(r == 0)) {
1352 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1353 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1354 }
1355}
1356
1324static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)1357static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1325{1358{
1326 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);1359 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -4785,6 +4818,10 @@ static int gfx_v8_0_hw_init(void *handle) · 3458 unmodified lines
4785 gfx_v8_0_init_golden_registers(adev);4818 gfx_v8_0_init_golden_registers(adev);
4786 gfx_v8_0_constants_init(adev);4819 gfx_v8_0_constants_init(adev);
4787 4820
4821 r = gfx_v8_0_csb_vram_pin(adev);
4822 if (r)
4823 return r;
4824
4788 r = adev->gfx.rlc.funcs->resume(adev);4825 r = adev->gfx.rlc.funcs->resume(adev);
4789 if (r)4826 if (r)
4790 return r;4827 return r;
@@ -4901,6 +4938,9 @@ static int gfx_v8_0_hw_fini(void *handle) · 110 unmodified lines
4901 else4938 else
4902 pr_err("rlc is busy, skip halt rlc\n");4939 pr_err("rlc is busy, skip halt rlc\n");
4903 amdgpu_gfx_rlc_exit_safe_mode(adev);4940 amdgpu_gfx_rlc_exit_safe_mode(adev);
4941
4942 gfx_v8_0_csb_vram_unpin(adev);
4943
4904 return 0;4944 return 0;
4905}4945}
4906 4946
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c+37−7
@@ -1485,7 +1485,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) · 1484 unmodified lines
1485 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));1485 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
1486 amdgpu_ring_write(ring, 0);1486 amdgpu_ring_write(ring, 0);
1487 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));1487 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1488 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);1488 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1489}1489}
1490 1490
1491/**1491/**
@@ -1498,7 +1498,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) · 6 unmodified lines
1498static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)1498static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1499{1499{
1500 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));1500 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1501 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);1501 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1502}1502}
1503 1503
1504/**1504/**
@@ -1543,7 +1543,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 · 38 unmodified lines
1543 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);1543 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1544 1544
1545 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));1545 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1546 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);1546 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1547 1547
1548 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));1548 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
1549 amdgpu_ring_write(ring, 0);1549 amdgpu_ring_write(ring, 0);
@@ -1553,7 +1553,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 · 3 unmodified lines
1553 1553
1554 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));1554 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1555 1555
1556 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);1556 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1557}1557}
1558 1558
1559/**1559/**
@@ -1597,7 +1597,7 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, · 37 unmodified lines
1597 1597
1598 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));1598 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1599 1599
1600 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);1600 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1601}1601}
1602 1602
1603static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,1603static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
@@ -1626,7 +1626,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, · 22 unmodified lines
1626 1626
1627 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));1627 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
1628 1628
1629 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);1629 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1630}1630}
1631 1631
1632/**1632/**
@@ -2079,6 +2079,36 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, · 446 unmodified lines
2079 return 0;2079 return 0;
2080}2080}
2081 2081
2082static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
2083{
2084 struct amdgpu_device *adev = ring->adev;
2085 uint32_t tmp = 0;
2086 unsigned i;
2087 int r;
2088
2089 WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
2090 r = amdgpu_ring_alloc(ring, 4);
2091 if (r)
2092 return r;
2093 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
2094 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
2095 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
2096 amdgpu_ring_write(ring, 0xDEADBEEF);
2097 amdgpu_ring_commit(ring);
2098 for (i = 0; i < adev->usec_timeout; i++) {
2099 tmp = RREG32(adev->vcn.external.scratch9);
2100 if (tmp == 0xDEADBEEF)
2101 break;
2102 DRM_UDELAY(1);
2103 }
2104
2105 if (i >= adev->usec_timeout)
2106 r = -ETIMEDOUT;
2107
2108 return r;
2109}
2110
2111
2082static int vcn_v2_0_set_powergating_state(void *handle,2112static int vcn_v2_0_set_powergating_state(void *handle,
2083 enum amd_powergating_state state)2113 enum amd_powergating_state state)
2084{2114{
@@ -2142,7 +2172,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { · 57 unmodified lines
2142 .emit_ib = vcn_v2_0_dec_ring_emit_ib,2172 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2143 .emit_fence = vcn_v2_0_dec_ring_emit_fence,2173 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2144 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,2174 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2145 .test_ring = amdgpu_vcn_dec_ring_test_ring,2175 .test_ring = vcn_v2_0_dec_ring_test_ring,
2146 .test_ib = amdgpu_vcn_dec_ring_test_ib,2176 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2147 .insert_nop = vcn_v2_0_dec_ring_insert_nop,2177 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2148 .insert_start = vcn_v2_0_dec_ring_insert_start,2178 .insert_start = vcn_v2_0_dec_ring_insert_start,
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+0−28
@@ -1567,32 +1567,6 @@ copy_from_user_failed: · 1566 unmodified lines
1567 return err;1567 return err;
1568}1568}
1569 1569
1570static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1571 struct kfd_process *p, void *data)
1572{
1573 int retval;
1574 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1575 struct kfd_dev *dev;
1576
1577 if (!hws_gws_support)
1578 return -ENODEV;
1579
1580 dev = kfd_device_by_id(args->gpu_id);
1581 if (!dev) {
1582 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
1583 return -ENODEV;
1584 }
1585 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
1586 return -ENODEV;
1587
1588 mutex_lock(&p->mutex);
1589 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1590 mutex_unlock(&p->mutex);
1591
1592 args->first_gws = 0;
1593 return retval;
1594}
1595
1596static int kfd_ioctl_get_dmabuf_info(struct file *filep,1570static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1597 struct kfd_process *p, void *data)1571 struct kfd_process *p, void *data)
1598{1572{
@@ -1795,8 +1769,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { · 196 unmodified lines
1795 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,1769 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
1796 kfd_ioctl_import_dmabuf, 0),1770 kfd_ioctl_import_dmabuf, 0),
1797 1771
1798 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
1799 kfd_ioctl_alloc_queue_gws, 0),
1800};1772};
1801 1773
1802#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)1774#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c+3−1
@@ -315,6 +315,8 @@ int smu_get_power_num_states(struct smu_context *smu, · 314 unmodified lines
315int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,315int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
316 void *data, uint32_t *size)316 void *data, uint32_t *size)
317{317{
318 struct smu_power_context *smu_power = &smu->smu_power;
319 struct smu_power_gate *power_gate = &smu_power->power_gate;
318 int ret = 0;320 int ret = 0;
319 321
320 switch (sensor) {322 switch (sensor) {
@@ -339,7 +341,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, · 18 unmodified lines
339 *size = 4;341 *size = 4;
340 break;342 break;
341 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:343 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
342 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0;344 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
343 *size = 4;345 *size = 4;
344 break;346 break;
345 default:347 default:
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h+1−0
@@ -451,6 +451,7 @@ struct smu_dpm_context { · 450 unmodified lines
451struct smu_power_gate {451struct smu_power_gate {
452 bool uvd_gated;452 bool uvd_gated;
453 bool vce_gated;453 bool vce_gated;
454 bool vcn_gated;
454};455};
455 456
456struct smu_power_context {457struct smu_power_context {
drivers/gpu/drm/amd/powerplay/navi10_ppt.c+53−26
@@ -502,6 +502,8 @@ static int navi10_store_powerplay_table(struct smu_context *smu) · 501 unmodified lines
502 502
503static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)503static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
504{504{
505 struct smu_table_context *smu_table = &smu->smu_table;
506
505 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),507 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
507 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),509 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
@@ -516,9 +518,35 @@ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables) · 8 unmodified lines
516 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,518 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
517 AMDGPU_GEM_DOMAIN_VRAM);519 AMDGPU_GEM_DOMAIN_VRAM);
518 520
521 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
522 if (!smu_table->metrics_table)
523 return -ENOMEM;
524 smu_table->metrics_time = 0;
525
519 return 0;526 return 0;
520}527}
521 528
529static int navi10_get_metrics_table(struct smu_context *smu,
530 SmuMetrics_t *metrics_table)
531{
532 struct smu_table_context *smu_table= &smu->smu_table;
533 int ret = 0;
534
535 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
536 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
537 (void *)smu_table->metrics_table, false);
538 if (ret) {
539 pr_info("Failed to export SMU metrics table!\n");
540 return ret;
541 }
542 smu_table->metrics_time = jiffies;
543 }
544
545 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
546
547 return ret;
548}
549
522static int navi10_allocate_dpm_context(struct smu_context *smu)550static int navi10_allocate_dpm_context(struct smu_context *smu)
523{551{
524 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;552 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
@@ -577,20 +605,27 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) · 52 unmodified lines
577 605
578static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)606static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
579{607{
608 struct smu_power_context *smu_power = &smu->smu_power;
609 struct smu_power_gate *power_gate = &smu_power->power_gate;
580 int ret = 0;610 int ret = 0;
581 611
582 if (enable) {612 if (enable) {
583 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);613 /* vcn dpm on is a prerequisite for vcn power gate messages */
584 if (ret)614 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
585 return ret;615 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
616 if (ret)
617 return ret;
618 }
619 power_gate->vcn_gated = false;
586 } else {620 } else {
587 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);621 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
588 if (ret)622 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
589 return ret;623 if (ret)
624 return ret;
625 }
626 power_gate->vcn_gated = true;
590 }627 }
591 628
592 ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
593
594 return ret;629 return ret;
595}630}
596 631
@@ -598,15 +633,10 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, · 1 unmodified line
598 enum smu_clk_type clk_type,633 enum smu_clk_type clk_type,
599 uint32_t *value)634 uint32_t *value)
600{635{
601 static SmuMetrics_t metrics;
602 int ret = 0, clk_id = 0;636 int ret = 0, clk_id = 0;
637 SmuMetrics_t metrics;
603 638
604 if (!value)639 ret = navi10_get_metrics_table(smu, &metrics);
605 return -EINVAL;
606
607 memset(&metrics, 0, sizeof(metrics));
608
609 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
610 if (ret)640 if (ret)
611 return ret;641 return ret;
612 642
@@ -894,8 +924,9 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value) · 281 unmodified lines
894 if (!value)924 if (!value)
895 return -EINVAL;925 return -EINVAL;
896 926
897 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,927 ret = navi10_get_metrics_table(smu, &metrics);
898 false);928 if (ret)
929 return ret;
899 if (ret)930 if (ret)
900 return ret;931 return ret;
901 932
@@ -914,10 +945,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu, · 12 unmodified lines
914 if (!value)945 if (!value)
915 return -EINVAL;946 return -EINVAL;
916 947
917 msleep(1);948 ret = navi10_get_metrics_table(smu, &metrics);
918
919 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
920 (void *)&metrics, false);
921 if (ret)949 if (ret)
922 return ret;950 return ret;
923 951
@@ -956,10 +984,9 @@ static int navi10_get_fan_speed_rpm(struct smu_context *smu, · 32 unmodified lines
956 if (!speed)984 if (!speed)
957 return -EINVAL;985 return -EINVAL;
958 986
959 memset(&metrics, 0, sizeof(metrics));987 ret = navi10_get_metrics_table(smu, &metrics);
960 988 if (ret)
961 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,989 return ret;
962 (void *)&metrics, false);
963 if (ret)990 if (ret)
964 return ret;991 return ret;
965 992
@@ -1307,7 +1334,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu, · 341 unmodified lines
1307 if (!value)1334 if (!value)
1308 return -EINVAL;1335 return -EINVAL;
1309 1336
1310 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);1337 ret = navi10_get_metrics_table(smu, &metrics);
1311 if (ret)1338 if (ret)
1312 return ret;1339 return ret;
1313 1340
drivers/gpu/drm/amd/powerplay/smu_v11_0.c+1−1
@@ -1391,7 +1391,7 @@ smu_v11_0_smc_fan_control(struct smu_context *smu, bool start) · 1390 unmodified lines
1391{1391{
1392 int ret = 0;1392 int ret = 0;
1393 1393
1394 if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))1394 if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1395 return 0;1395 return 0;
1396 1396
1397 ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);1397 ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
drivers/gpu/drm/drm_modes.c+3−1
@@ -1770,7 +1770,9 @@ bool drm_mode_parse_command_line_for_connector(const char *mode_option, · 1769 unmodified lines
1770 }1770 }
1771 1771
1772 if (named_mode) {1772 if (named_mode) {
1773 strncpy(mode->name, name, mode_end);1773 if (mode_end + 1 > DRM_DISPLAY_MODE_LEN)
1774 return false;
1775 strscpy(mode->name, name, mode_end + 1);
1774 } else {1776 } else {
1775 ret = drm_mode_parse_cmdline_res_mode(name, mode_end,1777 ret = drm_mode_parse_cmdline_res_mode(name, mode_end,
1776 parse_extras,1778 parse_extras,
drivers/gpu/drm/i915/display/intel_hdcp.c+2−1
@@ -536,7 +536,8 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) · 535 unmodified lines
536 536
537 if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) {537 if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) {
538 DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n");538 DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n");
539 return -EPERM;539 ret = -EPERM;
540 goto err;
540 }541 }
541 542
542 /*543 /*
drivers/gpu/drm/i915/display/vlv_dsi_pll.c+2−2
@@ -396,8 +396,8 @@ static void glk_dsi_program_esc_clock(struct drm_device *dev, · 395 unmodified lines
396 else396 else
397 txesc2_div = 10;397 txesc2_div = 10;
398 398
399 I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);399 I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
400 I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);400 I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
401}401}
402 402
403/* Program BXT Mipi clocks and dividers */403/* Program BXT Mipi clocks and dividers */
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c+1−1
@@ -432,7 +432,7 @@ static int rockchip_dp_resume(struct device *dev) · 431 unmodified lines
432 432
433static const struct dev_pm_ops rockchip_dp_pm_ops = {433static const struct dev_pm_ops rockchip_dp_pm_ops = {
434#ifdef CONFIG_PM_SLEEP434#ifdef CONFIG_PM_SLEEP
435 .suspend = rockchip_dp_suspend,435 .suspend_late = rockchip_dp_suspend,
436 .resume_early = rockchip_dp_resume,436 .resume_early = rockchip_dp_resume,
437#endif437#endif
438};438};
drivers/gpu/drm/tegra/output.c+6−2
@@ -126,8 +126,12 @@ int tegra_output_probe(struct tegra_output *output) · 125 unmodified lines
126 "nvidia,hpd-gpio", 0,126 "nvidia,hpd-gpio", 0,
127 GPIOD_IN,127 GPIOD_IN,
128 "HDMI hotplug detect");128 "HDMI hotplug detect");
129 if (IS_ERR(output->hpd_gpio))129 if (IS_ERR(output->hpd_gpio)) {
130 return PTR_ERR(output->hpd_gpio);130 if (PTR_ERR(output->hpd_gpio) != -ENOENT)
131 return PTR_ERR(output->hpd_gpio);
132
133 output->hpd_gpio = NULL;
134 }
131 135
132 if (output->hpd_gpio) {136 if (output->hpd_gpio) {
133 err = gpiod_to_irq(output->hpd_gpio);137 err = gpiod_to_irq(output->hpd_gpio);
drivers/gpu/drm/vmwgfx/vmwgfx_msg.c+3−1
@@ -389,8 +389,10 @@ static int vmw_recv_msg(struct rpc_channel *channel, void **msg, · 388 unmodified lines
389 break;389 break;
390 }390 }
391 391
392 if (retries == RETRIES)392 if (retries == RETRIES) {
393 kfree(reply);
393 return -EINVAL;394 return -EINVAL;
395 }
394 396
395 *msg_len = reply_len;397 *msg_len = reply_len;
396 *msg = reply;398 *msg = reply;
include/uapi/linux/kfd_ioctl.h+1−19
@@ -410,21 +410,6 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { · 409 unmodified lines
410 __u32 n_success; /* to/from KFD */410 __u32 n_success; /* to/from KFD */
411};411};
412 412
413/* Allocate GWS for specific queue
414 *
415 * @gpu_id: device identifier
416 * @queue_id: queue's id that GWS is allocated for
417 * @num_gws: how many GWS to allocate
418 * @first_gws: index of the first GWS allocated.
419 * only support contiguous GWS allocation
420 */
421struct kfd_ioctl_alloc_queue_gws_args {
422 __u32 gpu_id; /* to KFD */
423 __u32 queue_id; /* to KFD */
424 __u32 num_gws; /* to KFD */
425 __u32 first_gws; /* from KFD */
426};
427
428struct kfd_ioctl_get_dmabuf_info_args {413struct kfd_ioctl_get_dmabuf_info_args {
429 __u64 size; /* from KFD */414 __u64 size; /* from KFD */
430 __u64 metadata_ptr; /* to KFD */415 __u64 metadata_ptr; /* to KFD */
@@ -544,10 +529,7 @@ enum kfd_mmio_remap { · 113 unmodified lines
544#define AMDKFD_IOC_IMPORT_DMABUF \529#define AMDKFD_IOC_IMPORT_DMABUF \
545 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)530 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
546 531
547#define AMDKFD_IOC_ALLOC_QUEUE_GWS \
548 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
549
550#define AMDKFD_COMMAND_START 0x01532#define AMDKFD_COMMAND_START 0x01
551#define AMDKFD_COMMAND_END 0x1F533#define AMDKFD_COMMAND_END 0x1E
552 534
553#endif535#endif