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irqchip: gicv3-its: Use non-cacheable accesses when no shareability

If the ITS or the redistributors report their shareability as zero, then it is important to make sure they will no generate any cacheable traffic, as this is unlikely to produce the expected result.

Marc Zyngier committed 11 years ago

Commit 241a3861 parent 4ad3e362 files · +47 −4Browse files

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include/linux/irqchip/arm-gic-v3.h+4−0
@@ -126,6 +126,7 @@ · 125 unmodified lines
126126 #define GICR_PROPBASER_WaWb (5U << 7)
127127 #define GICR_PROPBASER_RaWaWt (6U << 7)
128128 #define GICR_PROPBASER_RaWaWb (7U << 7)
129+#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
129130 #define GICR_PROPBASER_IDBITS_MASK (0x1f)
130131
131132 #define GICR_PENDBASER_NonShareable (0U << 10)
@@ -140,6 +141,7 @@ · 8 unmodified lines
140141 #define GICR_PENDBASER_WaWb (5U << 7)
141142 #define GICR_PENDBASER_RaWaWt (6U << 7)
142143 #define GICR_PENDBASER_RaWaWb (7U << 7)
144+#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
143145
144146 /*
145147 * Re-Distributor registers, offsets from SGI_base
@@ -195,6 +197,7 @@ · 49 unmodified lines
195197 #define GITS_CBASER_WaWb (5UL << 59)
196198 #define GITS_CBASER_RaWaWt (6UL << 59)
197199 #define GITS_CBASER_RaWaWb (7UL << 59)
200+#define GITS_CBASER_CACHEABILITY_MASK (7UL << 59)
198201 #define GITS_CBASER_NonShareable (0UL << 10)
199202 #define GITS_CBASER_InnerShareable (1UL << 10)
200203 #define GITS_CBASER_OuterShareable (2UL << 10)
@@ -211,6 +214,7 @@ · 10 unmodified lines
211214 #define GITS_BASER_WaWb (5UL << 59)
212215 #define GITS_BASER_RaWaWt (6UL << 59)
213216 #define GITS_BASER_RaWaWb (7UL << 59)
217+#define GITS_BASER_CACHEABILITY_MASK (7UL << 59)
214218 #define GITS_BASER_TYPE_SHIFT (56)
215219 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
216220 #define GITS_BASER_ENTRY_SIZE_SHIFT (48)