| @@ -154,25 +154,77 @@ enum i915_mocs_table_index { · 153 unmodified lines |
| 154 | I915_MOCS_CACHED, | 154 | I915_MOCS_CACHED, |
| 155 | }; | 155 | }; |
| 156 | | 156 | |
| 157 | /* | 157 | /** |
| | 158 | * enum drm_i915_gem_engine_class - uapi engine type enumeration |
| | 159 | * |
| 158 | * Different engines serve different roles, and there may be more than one | 160 | * Different engines serve different roles, and there may be more than one |
| 159 | * engine serving each role. enum drm_i915_gem_engine_class provides a | 161 | * engine serving each role. This enum provides a classification of the role |
| 160 | * classification of the role of the engine, which may be used when requesting | 162 | * of the engine, which may be used when requesting operations to be performed |
| 161 | * operations to be performed on a certain subset of engines, or for providing | 163 | * on a certain subset of engines, or for providing information about that |
| 162 | * information about that group. | 164 | * group. |
| 163 | */ | 165 | */ |
| 164 | enum drm_i915_gem_engine_class { | 166 | enum drm_i915_gem_engine_class { |
| | 167 | /** |
| | 168 | * @I915_ENGINE_CLASS_RENDER: |
| | 169 | * |
| | 170 | * Render engines support instructions used for 3D, Compute (GPGPU), |
| | 171 | * and programmable media workloads. These instructions fetch data and |
| | 172 | * dispatch individual work items to threads that operate in parallel. |
| | 173 | * The threads run small programs (called "kernels" or "shaders") on |
| | 174 | * the GPU's execution units (EUs). |
| | 175 | */ |
| 165 | I915_ENGINE_CLASS_RENDER = 0, | 176 | I915_ENGINE_CLASS_RENDER = 0, |
| | 177 | |
| | 178 | /** |
| | 179 | * @I915_ENGINE_CLASS_COPY: |
| | 180 | * |
| | 181 | * Copy engines (also referred to as "blitters") support instructions |
| | 182 | * that move blocks of data from one location in memory to another, |
| | 183 | * or that fill a specified location of memory with fixed data. |
| | 184 | * Copy engines can perform pre-defined logical or bitwise operations |
| | 185 | * on the source, destination, or pattern data. |
| | 186 | */ |
| 166 | I915_ENGINE_CLASS_COPY = 1, | 187 | I915_ENGINE_CLASS_COPY = 1, |
| | 188 | |
| | 189 | /** |
| | 190 | * @I915_ENGINE_CLASS_VIDEO: |
| | 191 | * |
| | 192 | * Video engines (also referred to as "bit stream decode" (BSD) or |
| | 193 | * "vdbox") support instructions that perform fixed-function media |
| | 194 | * decode and encode. |
| | 195 | */ |
| 167 | I915_ENGINE_CLASS_VIDEO = 2, | 196 | I915_ENGINE_CLASS_VIDEO = 2, |
| | 197 | |
| | 198 | /** |
| | 199 | * @I915_ENGINE_CLASS_VIDEO_ENHANCE: |
| | 200 | * |
| | 201 | * Video enhancement engines (also referred to as "vebox") support |
| | 202 | * instructions related to image enhancement. |
| | 203 | */ |
| 168 | I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, | 204 | I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, |
| 169 | | 205 | |
| 170 | /* should be kept compact */ | 206 | /** |
| | 207 | * @I915_ENGINE_CLASS_COMPUTE: |
| | 208 | * |
| | 209 | * Compute engines support a subset of the instructions available |
| | 210 | * on render engines: compute engines support Compute (GPGPU) and |
| | 211 | * programmable media workloads, but do not support the 3D pipeline. |
| | 212 | */ |
| | 213 | I915_ENGINE_CLASS_COMPUTE = 4, |
| | 214 | |
| | 215 | /* Values in this enum should be kept compact. */ |
| 171 | | 216 | |
| | 217 | /** |
| | 218 | * @I915_ENGINE_CLASS_INVALID: |
| | 219 | * |
| | 220 | * Placeholder value to represent an invalid engine class assignment. |
| | 221 | */ |
| 172 | I915_ENGINE_CLASS_INVALID = -1 | 222 | I915_ENGINE_CLASS_INVALID = -1 |
| 173 | }; | 223 | }; |
| 174 | | 224 | |
| 175 | /* | 225 | /** |
| | 226 | * struct i915_engine_class_instance - Engine class/instance identifier |
| | 227 | * |
| 176 | * There may be more than one engine fulfilling any role within the system. | 228 | * There may be more than one engine fulfilling any role within the system. |
| 177 | * Each engine of a class is given a unique instance number and therefore | 229 | * Each engine of a class is given a unique instance number and therefore |
| 178 | * any engine can be specified by its class:instance tuplet. APIs that allow | 230 | * any engine can be specified by its class:instance tuplet. APIs that allow |
| @@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class { · 1 unmodified line |
| 180 | * for this identification. | 232 | * for this identification. |
| 181 | */ | 233 | */ |
| 182 | struct i915_engine_class_instance { | 234 | struct i915_engine_class_instance { |
| 183 | __u16 engine_class; /* see enum drm_i915_gem_engine_class */ | 235 | /** |
| 184 | __u16 engine_instance; | 236 | * @engine_class: |
| | 237 | * |
| | 238 | * Engine class from enum drm_i915_gem_engine_class |
| | 239 | */ |
| | 240 | __u16 engine_class; |
| 185 | #define I915_ENGINE_CLASS_INVALID_NONE -1 | 241 | #define I915_ENGINE_CLASS_INVALID_NONE -1 |
| 186 | #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 | 242 | #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 |
| | 243 | |
| | 244 | /** |
| | 245 | * @engine_instance: |
| | 246 | * |
| | 247 | * Engine instance. |
| | 248 | */ |
| | 249 | __u16 engine_instance; |
| 187 | }; | 250 | }; |
| 188 | | 251 | |
| 189 | /** | 252 | /** |
| @@ -2657,24 +2720,65 @@ enum drm_i915_perf_record_type { · 2467 unmodified lines |
| 2657 | DRM_I915_PERF_RECORD_MAX /* non-ABI */ | 2720 | DRM_I915_PERF_RECORD_MAX /* non-ABI */ |
| 2658 | }; | 2721 | }; |
| 2659 | | 2722 | |
| 2660 | /* | 2723 | /** |
| | 2724 | * struct drm_i915_perf_oa_config |
| | 2725 | * |
| 2661 | * Structure to upload perf dynamic configuration into the kernel. | 2726 | * Structure to upload perf dynamic configuration into the kernel. |
| 2662 | */ | 2727 | */ |
| 2663 | struct drm_i915_perf_oa_config { | 2728 | struct drm_i915_perf_oa_config { |
| 2664 | /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ | 2729 | /** |
| | 2730 | * @uuid: |
| | 2731 | * |
| | 2732 | * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" |
| | 2733 | */ |
| 2665 | char uuid[36]; | 2734 | char uuid[36]; |
| 2666 | | 2735 | |
| | 2736 | /** |
| | 2737 | * @n_mux_regs: |
| | 2738 | * |
| | 2739 | * Number of mux regs in &mux_regs_ptr. |
| | 2740 | */ |
| 2667 | __u32 n_mux_regs; | 2741 | __u32 n_mux_regs; |
| | 2742 | |
| | 2743 | /** |
| | 2744 | * @n_boolean_regs: |
| | 2745 | * |
| | 2746 | * Number of boolean regs in &boolean_regs_ptr. |
| | 2747 | */ |
| 2668 | __u32 n_boolean_regs; | 2748 | __u32 n_boolean_regs; |
| | 2749 | |
| | 2750 | /** |
| | 2751 | * @n_flex_regs: |
| | 2752 | * |
| | 2753 | * Number of flex regs in &flex_regs_ptr. |
| | 2754 | */ |
| 2669 | __u32 n_flex_regs; | 2755 | __u32 n_flex_regs; |
| 2670 | | 2756 | |
| 2671 | /* | 2757 | /** |
| 2672 | * These fields are pointers to tuples of u32 values (register address, | 2758 | * @mux_regs_ptr: |
| 2673 | * value). For example the expected length of the buffer pointed by | 2759 | * |
| 2674 | * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). | 2760 | * Pointer to tuples of u32 values (register address, value) for mux |
| | 2761 | * registers. Expected length of buffer is (2 * sizeof(u32) * |
| | 2762 | * &n_mux_regs). |
| 2675 | */ | 2763 | */ |
| 2676 | __u64 mux_regs_ptr; | 2764 | __u64 mux_regs_ptr; |
| | 2765 | |
| | 2766 | /** |
| | 2767 | * @boolean_regs_ptr: |
| | 2768 | * |
| | 2769 | * Pointer to tuples of u32 values (register address, value) for mux |
| | 2770 | * registers. Expected length of buffer is (2 * sizeof(u32) * |
| | 2771 | * &n_boolean_regs). |
| | 2772 | */ |
| 2677 | __u64 boolean_regs_ptr; | 2773 | __u64 boolean_regs_ptr; |
| | 2774 | |
| | 2775 | /** |
| | 2776 | * @flex_regs_ptr: |
| | 2777 | * |
| | 2778 | * Pointer to tuples of u32 values (register address, value) for mux |
| | 2779 | * registers. Expected length of buffer is (2 * sizeof(u32) * |
| | 2780 | * &n_flex_regs). |
| | 2781 | */ |
| 2678 | __u64 flex_regs_ptr; | 2782 | __u64 flex_regs_ptr; |
| 2679 | }; | 2783 | }; |
| 2680 | | 2784 | |
| @@ -2685,12 +2789,24 @@ struct drm_i915_perf_oa_config { · 4 unmodified lines |
| 2685 | * @data_ptr is also depends on the specific @query_id. | 2789 | * @data_ptr is also depends on the specific @query_id. |
| 2686 | */ | 2790 | */ |
| 2687 | struct drm_i915_query_item { | 2791 | struct drm_i915_query_item { |
| 2688 | /** @query_id: The id for this query */ | 2792 | /** |
| | 2793 | * @query_id: |
| | 2794 | * |
| | 2795 | * The id for this query. Currently accepted query IDs are: |
| | 2796 | * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info) |
| | 2797 | * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info) |
| | 2798 | * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config) |
| | 2799 | * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions) |
| | 2800 | * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`) |
| | 2801 | * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info) |
| | 2802 | */ |
| 2689 | __u64 query_id; | 2803 | __u64 query_id; |
| 2690 | #define DRM_I915_QUERY_TOPOLOGY_INFO 1 | 2804 | #define DRM_I915_QUERY_TOPOLOGY_INFO 1 |
| 2691 | #define DRM_I915_QUERY_ENGINE_INFO 2 | 2805 | #define DRM_I915_QUERY_ENGINE_INFO 2 |
| 2692 | #define DRM_I915_QUERY_PERF_CONFIG 3 | 2806 | #define DRM_I915_QUERY_PERF_CONFIG 3 |
| 2693 | #define DRM_I915_QUERY_MEMORY_REGIONS 4 | 2807 | #define DRM_I915_QUERY_MEMORY_REGIONS 4 |
| | 2808 | #define DRM_I915_QUERY_HWCONFIG_BLOB 5 |
| | 2809 | #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 |
| 2694 | /* Must be kept compact -- no holes and well documented */ | 2810 | /* Must be kept compact -- no holes and well documented */ |
| 2695 | | 2811 | |
| 2696 | /** | 2812 | /** |
| @@ -2706,14 +2822,17 @@ struct drm_i915_query_item { · 9 unmodified lines |
| 2706 | /** | 2822 | /** |
| 2707 | * @flags: | 2823 | * @flags: |
| 2708 | * | 2824 | * |
| 2709 | * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. | 2825 | * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. |
| 2710 | * | 2826 | * |
| 2711 | * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the | 2827 | * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the |
| 2712 | * following: | 2828 | * following: |
| 2713 | * | 2829 | * |
| 2714 | * - DRM_I915_QUERY_PERF_CONFIG_LIST | 2830 | * - %DRM_I915_QUERY_PERF_CONFIG_LIST |
| 2715 | * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID | 2831 | * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID |
| 2716 | * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID | 2832 | * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID |
| | 2833 | * |
| | 2834 | * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain |
| | 2835 | * a struct i915_engine_class_instance that references a render engine. |
| 2717 | */ | 2836 | */ |
| 2718 | __u32 flags; | 2837 | __u32 flags; |
| 2719 | #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 | 2838 | #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 |
| @@ -2771,66 +2890,112 @@ struct drm_i915_query { · 51 unmodified lines |
| 2771 | __u64 items_ptr; | 2890 | __u64 items_ptr; |
| 2772 | }; | 2891 | }; |
| 2773 | | 2892 | |
| 2774 | /* | 2893 | /** |
| 2775 | * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : | 2894 | * struct drm_i915_query_topology_info |
| 2776 | * | | |
| 2777 | * data: contains the 3 pieces of information : | | |
| 2778 | * | | |
| 2779 | * - the slice mask with one bit per slice telling whether a slice is | | |
| 2780 | * available. The availability of slice X can be queried with the following | | |
| 2781 | * formula : | | |
| 2782 | * | | |
| 2783 | * (data[X / 8] >> (X % 8)) & 1 | | |
| 2784 | * | | |
| 2785 | * - the subslice mask for each slice with one bit per subslice telling | | |
| 2786 | * whether a subslice is available. Gen12 has dual-subslices, which are | | |
| 2787 | * similar to two gen11 subslices. For gen12, this array represents dual- | | |
| 2788 | * subslices. The availability of subslice Y in slice X can be queried | | |
| 2789 | * with the following formula : | | |
| 2790 | * | | |
| 2791 | * (data[subslice_offset + | | |
| 2792 | * X * subslice_stride + | | |
| 2793 | * Y / 8] >> (Y % 8)) & 1 | | |
| 2794 | * | | |
| 2795 | * - the EU mask for each subslice in each slice with one bit per EU telling | | |
| 2796 | * whether an EU is available. The availability of EU Z in subslice Y in | | |
| 2797 | * slice X can be queried with the following formula : | | |
| 2798 | * | 2895 | * |
| 2799 | * (data[eu_offset + | 2896 | * Describes slice/subslice/EU information queried by |
| 2800 | * (X * max_subslices + Y) * eu_stride + | 2897 | * %DRM_I915_QUERY_TOPOLOGY_INFO |
| 2801 | * Z / 8] >> (Z % 8)) & 1 | | |
| 2802 | */ | 2898 | */ |
| 2803 | struct drm_i915_query_topology_info { | 2899 | struct drm_i915_query_topology_info { |
| 2804 | /* | 2900 | /** |
| | 2901 | * @flags: |
| | 2902 | * |
| 2805 | * Unused for now. Must be cleared to zero. | 2903 | * Unused for now. Must be cleared to zero. |
| 2806 | */ | 2904 | */ |
| 2807 | __u16 flags; | 2905 | __u16 flags; |
| 2808 | | 2906 | |
| | 2907 | /** |
| | 2908 | * @max_slices: |
| | 2909 | * |
| | 2910 | * The number of bits used to express the slice mask. |
| | 2911 | */ |
| 2809 | __u16 max_slices; | 2912 | __u16 max_slices; |
| | 2913 | |
| | 2914 | /** |
| | 2915 | * @max_subslices: |
| | 2916 | * |
| | 2917 | * The number of bits used to express the subslice mask. |
| | 2918 | */ |
| 2810 | __u16 max_subslices; | 2919 | __u16 max_subslices; |
| | 2920 | |
| | 2921 | /** |
| | 2922 | * @max_eus_per_subslice: |
| | 2923 | * |
| | 2924 | * The number of bits in the EU mask that correspond to a single |
| | 2925 | * subslice's EUs. |
| | 2926 | */ |
| 2811 | __u16 max_eus_per_subslice; | 2927 | __u16 max_eus_per_subslice; |
| 2812 | | 2928 | |
| 2813 | /* | 2929 | /** |
| | 2930 | * @subslice_offset: |
| | 2931 | * |
| 2814 | * Offset in data[] at which the subslice masks are stored. | 2932 | * Offset in data[] at which the subslice masks are stored. |
| 2815 | */ | 2933 | */ |
| 2816 | __u16 subslice_offset; | 2934 | __u16 subslice_offset; |
| 2817 | | 2935 | |
| 2818 | /* | 2936 | /** |
| | 2937 | * @subslice_stride: |
| | 2938 | * |
| 2819 | * Stride at which each of the subslice masks for each slice are | 2939 | * Stride at which each of the subslice masks for each slice are |
| 2820 | * stored. | 2940 | * stored. |
| 2821 | */ | 2941 | */ |
| 2822 | __u16 subslice_stride; | 2942 | __u16 subslice_stride; |
| 2823 | | 2943 | |
| 2824 | /* | 2944 | /** |
| | 2945 | * @eu_offset: |
| | 2946 | * |
| 2825 | * Offset in data[] at which the EU masks are stored. | 2947 | * Offset in data[] at which the EU masks are stored. |
| 2826 | */ | 2948 | */ |
| 2827 | __u16 eu_offset; | 2949 | __u16 eu_offset; |
| 2828 | | 2950 | |
| 2829 | /* | 2951 | /** |
| | 2952 | * @eu_stride: |
| | 2953 | * |
| 2830 | * Stride at which each of the EU masks for each subslice are stored. | 2954 | * Stride at which each of the EU masks for each subslice are stored. |
| 2831 | */ | 2955 | */ |
| 2832 | __u16 eu_stride; | 2956 | __u16 eu_stride; |
| 2833 | | 2957 | |
| | 2958 | /** |
| | 2959 | * @data: |
| | 2960 | * |
| | 2961 | * Contains 3 pieces of information : |
| | 2962 | * |
| | 2963 | * - The slice mask with one bit per slice telling whether a slice is |
| | 2964 | * available. The availability of slice X can be queried with the |
| | 2965 | * following formula : |
| | 2966 | * |
| | 2967 | * .. code:: c |
| | 2968 | * |
| | 2969 | * (data[X / 8] >> (X % 8)) & 1 |
| | 2970 | * |
| | 2971 | * Starting with Xe_HP platforms, Intel hardware no longer has |
| | 2972 | * traditional slices so i915 will always report a single slice |
| | 2973 | * (hardcoded slicemask = 0x1) which contains all of the platform's |
| | 2974 | * subslices. I.e., the mask here does not reflect any of the newer |
| | 2975 | * hardware concepts such as "gslices" or "cslices" since userspace |
| | 2976 | * is capable of inferring those from the subslice mask. |
| | 2977 | * |
| | 2978 | * - The subslice mask for each slice with one bit per subslice telling |
| | 2979 | * whether a subslice is available. Starting with Gen12 we use the |
| | 2980 | * term "subslice" to refer to what the hardware documentation |
| | 2981 | * describes as a "dual-subslices." The availability of subslice Y |
| | 2982 | * in slice X can be queried with the following formula : |
| | 2983 | * |
| | 2984 | * .. code:: c |
| | 2985 | * |
| | 2986 | * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 |
| | 2987 | * |
| | 2988 | * - The EU mask for each subslice in each slice, with one bit per EU |
| | 2989 | * telling whether an EU is available. The availability of EU Z in |
| | 2990 | * subslice Y in slice X can be queried with the following formula : |
| | 2991 | * |
| | 2992 | * .. code:: c |
| | 2993 | * |
| | 2994 | * (data[eu_offset + |
| | 2995 | * (X * max_subslices + Y) * eu_stride + |
| | 2996 | * Z / 8 |
| | 2997 | * ] >> (Z % 8)) & 1 |
| | 2998 | */ |
| 2834 | __u8 data[]; | 2999 | __u8 data[]; |
| 2835 | }; | 3000 | }; |
| 2836 | | 3001 | |
| @@ -2951,52 +3116,68 @@ struct drm_i915_query_engine_info { · 114 unmodified lines |
| 2951 | struct drm_i915_engine_info engines[]; | 3116 | struct drm_i915_engine_info engines[]; |
| 2952 | }; | 3117 | }; |
| 2953 | | 3118 | |
| 2954 | /* | 3119 | /** |
| 2955 | * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG. | 3120 | * struct drm_i915_query_perf_config |
| | 3121 | * |
| | 3122 | * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and |
| | 3123 | * %DRM_I915_QUERY_GEOMETRY_SUBSLICES. |
| 2956 | */ | 3124 | */ |
| 2957 | struct drm_i915_query_perf_config { | 3125 | struct drm_i915_query_perf_config { |
| 2958 | union { | 3126 | union { |
| 2959 | /* | 3127 | /** |
| 2960 | * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets | 3128 | * @n_configs: |
| 2961 | * this fields to the number of configurations available. | 3129 | * |
| | 3130 | * When &drm_i915_query_item.flags == |
| | 3131 | * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to |
| | 3132 | * the number of configurations available. |
| 2962 | */ | 3133 | */ |
| 2963 | __u64 n_configs; | 3134 | __u64 n_configs; |
| 2964 | | 3135 | |
| 2965 | /* | 3136 | /** |
| 2966 | * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, | 3137 | * @config: |
| 2967 | * i915 will use the value in this field as configuration | 3138 | * |
| 2968 | * identifier to decide what data to write into config_ptr. | 3139 | * When &drm_i915_query_item.flags == |
| | 3140 | * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the |
| | 3141 | * value in this field as configuration identifier to decide |
| | 3142 | * what data to write into config_ptr. |
| 2969 | */ | 3143 | */ |
| 2970 | __u64 config; | 3144 | __u64 config; |
| 2971 | | 3145 | |
| 2972 | /* | 3146 | /** |
| 2973 | * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, | 3147 | * @uuid: |
| 2974 | * i915 will use the value in this field as configuration | 3148 | * |
| 2975 | * identifier to decide what data to write into config_ptr. | 3149 | * When &drm_i915_query_item.flags == |
| | 3150 | * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the |
| | 3151 | * value in this field as configuration identifier to decide |
| | 3152 | * what data to write into config_ptr. |
| 2976 | * | 3153 | * |
| 2977 | * String formatted like "%08x-%04x-%04x-%04x-%012x" | 3154 | * String formatted like "%08x-%04x-%04x-%04x-%012x" |
| 2978 | */ | 3155 | */ |
| 2979 | char uuid[36]; | 3156 | char uuid[36]; |
| 2980 | }; | 3157 | }; |
| 2981 | | 3158 | |
| 2982 | /* | 3159 | /** |
| | 3160 | * @flags: |
| | 3161 | * |
| 2983 | * Unused for now. Must be cleared to zero. | 3162 | * Unused for now. Must be cleared to zero. |
| 2984 | */ | 3163 | */ |
| 2985 | __u32 flags; | 3164 | __u32 flags; |
| 2986 | | 3165 | |
| 2987 | /* | 3166 | /** |
| 2988 | * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will | 3167 | * @data: |
| 2989 | * write an array of __u64 of configuration identifiers. | | |
| 2990 | * | 3168 | * |
| 2991 | * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will | 3169 | * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST, |
| 2992 | * write a struct drm_i915_perf_oa_config. If the following fields of | 3170 | * i915 will write an array of __u64 of configuration identifiers. |
| 2993 | * drm_i915_perf_oa_config are set not set to 0, i915 will write into | 3171 | * |
| 2994 | * the associated pointers the values of submitted when the | 3172 | * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA, |
| | 3173 | * i915 will write a struct drm_i915_perf_oa_config. If the following |
| | 3174 | * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will |
| | 3175 | * write into the associated pointers the values of submitted when the |
| 2995 | * configuration was created : | 3176 | * configuration was created : |
| 2996 | * | 3177 | * |
| 2997 | * - n_mux_regs | 3178 | * - &drm_i915_perf_oa_config.n_mux_regs |
| 2998 | * - n_boolean_regs | 3179 | * - &drm_i915_perf_oa_config.n_boolean_regs |
| 2999 | * - n_flex_regs | 3180 | * - &drm_i915_perf_oa_config.n_flex_regs |
| 3000 | */ | 3181 | */ |
| 3001 | __u8 data[]; | 3182 | __u8 data[]; |
| 3002 | }; | 3183 | }; |
| @@ -3134,6 +3315,16 @@ struct drm_i915_query_memory_regions { · 131 unmodified lines |
| 3134 | struct drm_i915_memory_region_info regions[]; | 3315 | struct drm_i915_memory_region_info regions[]; |
| 3135 | }; | 3316 | }; |
| 3136 | | 3317 | |
| | 3318 | /** |
| | 3319 | * DOC: GuC HWCONFIG blob uAPI |
| | 3320 | * |
| | 3321 | * The GuC produces a blob with information about the current device. |
| | 3322 | * i915 reads this blob from GuC and makes it available via this uAPI. |
| | 3323 | * |
| | 3324 | * The format and meaning of the blob content are documented in the |
| | 3325 | * Programmer's Reference Manual. |
| | 3326 | */ |
| | 3327 | |
| 3137 | /** | 3328 | /** |
| 3138 | * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added | 3329 | * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added |
| 3139 | * extension support using struct i915_user_extension. | 3330 | * extension support using struct i915_user_extension. |