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Merge tag 'drm-fixes-2025-06-14' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie: "Quiet week, only two pull requests came my way, xe has a couple of fixes and then a bunch of fixes across the board, vc4 probably fixes the biggest problem: vc4: - Fix infinite EPROBE_DEFER loop in vc4 probing amdxdna: - Fix amdxdna firmware size meson: - modesetting fixes sitronix: - Kconfig fix for st7171-i2c dma-buf: - Fix -EBUSY WARN_ON_ONCE in dma-buf udmabuf: - Use dma_sync_sgtable_for_cpu in udmabuf xe: - Fix regression disallowing 64K SVM migration - Use a bounce buffer for WA BB" * tag 'drm-fixes-2025-06-14' of https://gitlab.freedesktop.org/drm/kernel: drm/xe/lrc: Use a temporary buffer for WA BB udmabuf: use sgtable-based scatterlist wrappers dma-buf: fix compare in WARN_ON_ONCE drm/sitronix: st7571-i2c: Select VIDEOMODE_HELPERS drm/meson: fix more rounding issues with 59.94Hz modes drm/meson: use vclk_freq instead of pixel_freq in debug print drm/meson: fix debug log statement when setting the HDMI clocks drm/vc4: fix infinite EPROBE_DEFER loop drm/xe/svm: Fix regression disallowing 64K SVM migration accel/amdxdna: Fix incorrect PSP firmware size

Linus Torvalds committed 1 year ago

Commit 25294cb2 parents 18531f4 1364af99 files · +68 −39Browse files

Unified · Split

9 files
  1. drivers/accel/amdxdna/aie2_psp.c +2 −2
  2. drivers/dma-buf/dma-buf.c +1 −1
  3. drivers/dma-buf/udmabuf.c +2 −3
  4. drivers/gpu/drm/meson/meson_encoder_hdmi.c +1 −1
  5. drivers/gpu/drm/meson/meson_vclk.c +34 −21
  6. drivers/gpu/drm/sitronix/Kconfig +1 −0
  7. drivers/gpu/drm/vc4/vc4_hdmi.c +6 −6
  8. drivers/gpu/drm/xe/xe_lrc.c +20 −4
  9. drivers/gpu/drm/xe/xe_svm.c +1 −1
drivers/accel/amdxdna/aie2_psp.c+2−2
@@ -126,8 +126,8 @@ struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config * · 125 unmodified lines
126 psp->ddev = ddev;126 psp->ddev = ddev;
127 memcpy(psp->psp_regs, conf->psp_regs, sizeof(psp->psp_regs));127 memcpy(psp->psp_regs, conf->psp_regs, sizeof(psp->psp_regs));
128 128
129 psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN) + PSP_FW_ALIGN;129 psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN);
130 psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz, GFP_KERNEL);130 psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz + PSP_FW_ALIGN, GFP_KERNEL);
131 if (!psp->fw_buffer) {131 if (!psp->fw_buffer) {
132 drm_err(ddev, "no memory for fw buffer");132 drm_err(ddev, "no memory for fw buffer");
133 return NULL;133 return NULL;
drivers/dma-buf/dma-buf.c+1−1
@@ -1118,7 +1118,7 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach, · 1117 unmodified lines
1118 * Catch exporters making buffers inaccessible even when1118 * Catch exporters making buffers inaccessible even when
1119 * attachments preventing that exist.1119 * attachments preventing that exist.
1120 */1120 */
1121 WARN_ON_ONCE(ret == EBUSY);1121 WARN_ON_ONCE(ret == -EBUSY);
1122 if (ret)1122 if (ret)
1123 return ERR_PTR(ret);1123 return ERR_PTR(ret);
1124 }1124 }
drivers/dma-buf/udmabuf.c+2−3
@@ -264,8 +264,7 @@ static int begin_cpu_udmabuf(struct dma_buf *buf, · 263 unmodified lines
264 ubuf->sg = NULL;264 ubuf->sg = NULL;
265 }265 }
266 } else {266 } else {
267 dma_sync_sg_for_cpu(dev, ubuf->sg->sgl, ubuf->sg->nents,267 dma_sync_sgtable_for_cpu(dev, ubuf->sg, direction);
268 direction);
269 }268 }
270 269
271 return ret;270 return ret;
@@ -280,7 +279,7 @@ static int end_cpu_udmabuf(struct dma_buf *buf, · 8 unmodified lines
280 if (!ubuf->sg)279 if (!ubuf->sg)
281 return -EINVAL;280 return -EINVAL;
282 281
283 dma_sync_sg_for_device(dev, ubuf->sg->sgl, ubuf->sg->nents, direction);282 dma_sync_sgtable_for_device(dev, ubuf->sg, direction);
284 return 0;283 return 0;
285}284}
286 285
drivers/gpu/drm/meson/meson_encoder_hdmi.c+1−1
@@ -109,7 +109,7 @@ static void meson_encoder_hdmi_set_vclk(struct meson_encoder_hdmi *encoder_hdmi, · 108 unmodified lines
109 venc_freq /= 2;109 venc_freq /= 2;
110 110
111 dev_dbg(priv->dev,111 dev_dbg(priv->dev,
112 "vclk:%lluHz phy=%lluHz venc=%lluHz hdmi=%lluHz enci=%d\n",112 "phy:%lluHz vclk=%lluHz venc=%lluHz hdmi=%lluHz enci=%d\n",
113 phy_freq, vclk_freq, venc_freq, hdmi_freq,113 phy_freq, vclk_freq, venc_freq, hdmi_freq,
114 priv->venc.hdmi_use_enci);114 priv->venc.hdmi_use_enci);
115 115
drivers/gpu/drm/meson/meson_vclk.c+34−21
@@ -110,10 +110,7 @@ · 109 unmodified lines
110#define HDMI_PLL_LOCK BIT(31)110#define HDMI_PLL_LOCK BIT(31)
111#define HDMI_PLL_LOCK_G12A (3 << 30)111#define HDMI_PLL_LOCK_G12A (3 << 30)
112 112
113#define PIXEL_FREQ_1000_1001(_freq) \113#define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST_ULL((_freq) * 1000ULL, 1001ULL)
114 DIV_ROUND_CLOSEST_ULL((_freq) * 1000ULL, 1001ULL)
115#define PHY_FREQ_1000_1001(_freq) \
116 (PIXEL_FREQ_1000_1001(DIV_ROUND_DOWN_ULL(_freq, 10ULL)) * 10)
117 114
118/* VID PLL Dividers */115/* VID PLL Dividers */
119enum {116enum {
@@ -772,6 +769,36 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, · 652 unmodified lines
772 pll_freq);769 pll_freq);
773}770}
774 771
772static bool meson_vclk_freqs_are_matching_param(unsigned int idx,
773 unsigned long long phy_freq,
774 unsigned long long vclk_freq)
775{
776 DRM_DEBUG_DRIVER("i = %d vclk_freq = %lluHz alt = %lluHz\n",
777 idx, params[idx].vclk_freq,
778 FREQ_1000_1001(params[idx].vclk_freq));
779 DRM_DEBUG_DRIVER("i = %d phy_freq = %lluHz alt = %lluHz\n",
780 idx, params[idx].phy_freq,
781 FREQ_1000_1001(params[idx].phy_freq));
782
783 /* Match strict frequency */
784 if (phy_freq == params[idx].phy_freq &&
785 vclk_freq == params[idx].vclk_freq)
786 return true;
787
788 /* Match 1000/1001 variant: vclk deviation has to be less than 1kHz
789 * (drm EDID is defined in 1kHz steps, so everything smaller must be
790 * rounding error) and the PHY freq deviation has to be less than
791 * 10kHz (as the TMDS clock is 10 times the pixel clock, so anything
792 * smaller must be rounding error as well).
793 */
794 if (abs(vclk_freq - FREQ_1000_1001(params[idx].vclk_freq)) < 1000 &&
795 abs(phy_freq - FREQ_1000_1001(params[idx].phy_freq)) < 10000)
796 return true;
797
798 /* no match */
799 return false;
800}
801
775enum drm_mode_status802enum drm_mode_status
776meson_vclk_vic_supported_freq(struct meson_drm *priv,803meson_vclk_vic_supported_freq(struct meson_drm *priv,
777 unsigned long long phy_freq,804 unsigned long long phy_freq,
@@ -790,19 +817,7 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, · 12 unmodified lines
790 }817 }
791 818
792 for (i = 0 ; params[i].pixel_freq ; ++i) {819 for (i = 0 ; params[i].pixel_freq ; ++i) {
793 DRM_DEBUG_DRIVER("i = %d pixel_freq = %lluHz alt = %lluHz\n",820 if (meson_vclk_freqs_are_matching_param(i, phy_freq, vclk_freq))
794 i, params[i].pixel_freq,
795 PIXEL_FREQ_1000_1001(params[i].pixel_freq));
796 DRM_DEBUG_DRIVER("i = %d phy_freq = %lluHz alt = %lluHz\n",
797 i, params[i].phy_freq,
798 PHY_FREQ_1000_1001(params[i].phy_freq));
799 /* Match strict frequency */
800 if (phy_freq == params[i].phy_freq &&
801 vclk_freq == params[i].vclk_freq)
802 return MODE_OK;
803 /* Match 1000/1001 variant */
804 if (phy_freq == PHY_FREQ_1000_1001(params[i].phy_freq) &&
805 vclk_freq == PIXEL_FREQ_1000_1001(params[i].vclk_freq))
806 return MODE_OK;821 return MODE_OK;
807 }822 }
808 823
@@ -1075,10 +1090,8 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, · 266 unmodified lines
1075 }1090 }
1076 1091
1077 for (freq = 0 ; params[freq].pixel_freq ; ++freq) {1092 for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
1078 if ((phy_freq == params[freq].phy_freq ||1093 if (meson_vclk_freqs_are_matching_param(freq, phy_freq,
1079 phy_freq == PHY_FREQ_1000_1001(params[freq].phy_freq)) &&1094 vclk_freq)) {
1080 (vclk_freq == params[freq].vclk_freq ||
1081 vclk_freq == PIXEL_FREQ_1000_1001(params[freq].vclk_freq))) {
1082 if (vclk_freq != params[freq].vclk_freq)1095 if (vclk_freq != params[freq].vclk_freq)
1083 vic_alternate_clock = true;1096 vic_alternate_clock = true;
1084 else1097 else
drivers/gpu/drm/sitronix/Kconfig+1−0
@@ -5,6 +5,7 @@ config DRM_ST7571_I2C · 4 unmodified lines
5 select DRM_GEM_SHMEM_HELPER5 select DRM_GEM_SHMEM_HELPER
6 select DRM_KMS_HELPER6 select DRM_KMS_HELPER
7 select REGMAP_I2C7 select REGMAP_I2C
8 select VIDEOMODE_HELPERS
8 help9 help
9 DRM driver for Sitronix ST7571 panels controlled over I2C.10 DRM driver for Sitronix ST7571 panels controlled over I2C.
10 11
drivers/gpu/drm/vc4/vc4_hdmi.c+6−6
@@ -560,12 +560,6 @@ static int vc4_hdmi_connector_init(struct drm_device *dev, · 559 unmodified lines
560 if (ret)560 if (ret)
561 return ret;561 return ret;
562 562
563 ret = drm_connector_hdmi_audio_init(connector, dev->dev,
564 &vc4_hdmi_audio_funcs,
565 8, false, -1);
566 if (ret)
567 return ret;
568
569 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);563 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
570 564
571 /*565 /*
@@ -2291,6 +2285,12 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) · 1719 unmodified lines
2291 return ret;2285 return ret;
2292 }2286 }
2293 2287
2288 ret = drm_connector_hdmi_audio_init(&vc4_hdmi->connector, dev,
2289 &vc4_hdmi_audio_funcs, 8, false,
2290 -1);
2291 if (ret)
2292 return ret;
2293
2294 dai_link->cpus = &vc4_hdmi->audio.cpu;2294 dai_link->cpus = &vc4_hdmi->audio.cpu;
2295 dai_link->codecs = &vc4_hdmi->audio.codec;2295 dai_link->codecs = &vc4_hdmi->audio.codec;
2296 dai_link->platforms = &vc4_hdmi->audio.platform;2296 dai_link->platforms = &vc4_hdmi->audio.platform;
drivers/gpu/drm/xe/xe_lrc.c+20−4
@@ -941,11 +941,18 @@ static void xe_lrc_finish(struct xe_lrc *lrc) · 940 unmodified lines
941 * store it in the PPHSWP.941 * store it in the PPHSWP.
942 */942 */
943#define CONTEXT_ACTIVE 1ULL943#define CONTEXT_ACTIVE 1ULL
944static void xe_lrc_setup_utilization(struct xe_lrc *lrc)944static int xe_lrc_setup_utilization(struct xe_lrc *lrc)
945{945{
946 u32 *cmd;946 u32 *cmd, *buf = NULL;
947 947
948 cmd = lrc->bb_per_ctx_bo->vmap.vaddr;948 if (lrc->bb_per_ctx_bo->vmap.is_iomem) {
949 buf = kmalloc(lrc->bb_per_ctx_bo->size, GFP_KERNEL);
950 if (!buf)
951 return -ENOMEM;
952 cmd = buf;
953 } else {
954 cmd = lrc->bb_per_ctx_bo->vmap.vaddr;
955 }
949 956
950 *cmd++ = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT | MI_SRM_ADD_CS_OFFSET;957 *cmd++ = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT | MI_SRM_ADD_CS_OFFSET;
951 *cmd++ = ENGINE_ID(0).addr;958 *cmd++ = ENGINE_ID(0).addr;
@@ -966,9 +973,16 @@ static void xe_lrc_setup_utilization(struct xe_lrc *lrc) · 14 unmodified lines
966 973
967 *cmd++ = MI_BATCH_BUFFER_END;974 *cmd++ = MI_BATCH_BUFFER_END;
968 975
976 if (buf) {
977 xe_map_memcpy_to(gt_to_xe(lrc->gt), &lrc->bb_per_ctx_bo->vmap, 0,
978 buf, (cmd - buf) * sizeof(*cmd));
979 kfree(buf);
980 }
981
969 xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR,982 xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR,
970 xe_bo_ggtt_addr(lrc->bb_per_ctx_bo) | 1);983 xe_bo_ggtt_addr(lrc->bb_per_ctx_bo) | 1);
971 984
985 return 0;
972}986}
973 987
974#define PVC_CTX_ASID (0x2e + 1)988#define PVC_CTX_ASID (0x2e + 1)
@@ -1125,7 +1139,9 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, · 150 unmodified lines
1125 map = __xe_lrc_start_seqno_map(lrc);1139 map = __xe_lrc_start_seqno_map(lrc);
1126 xe_map_write32(lrc_to_xe(lrc), &map, lrc->fence_ctx.next_seqno - 1);1140 xe_map_write32(lrc_to_xe(lrc), &map, lrc->fence_ctx.next_seqno - 1);
1127 1141
1128 xe_lrc_setup_utilization(lrc);1142 err = xe_lrc_setup_utilization(lrc);
1143 if (err)
1144 goto err_lrc_finish;
1129 1145
1130 return 0;1146 return 0;
1131 1147
drivers/gpu/drm/xe/xe_svm.c+1−1
@@ -764,7 +764,7 @@ static bool xe_svm_range_needs_migrate_to_vram(struct xe_svm_range *range, · 763 unmodified lines
764 return false;764 return false;
765 }765 }
766 766
767 if (range_size <= SZ_64K && !supports_4K_migration(vm->xe)) {767 if (range_size < SZ_64K && !supports_4K_migration(vm->xe)) {
768 drm_dbg(&vm->xe->drm, "Platform doesn't support SZ_4K range migration\n");768 drm_dbg(&vm->xe->drm, "Platform doesn't support SZ_4K range migration\n");
769 return false;769 return false;
770 }770 }