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accel/ivpu: Add Intel VPU MMU support

VPU Memory Management Unit is based on ARM MMU-600. It allows the creation of multiple virtual address spaces for the device and map noncontinuous host memory (there is no dedicated memory on the VPU). Address space is implemented as a struct ivpu_mmu_context, it has an ID, drm_mm allocator for VPU addresses and struct ivpu_mmu_pgtable that holds actual 3-level, 4KB page table. Context with ID 0 (global context) is created upon driver initialization and it's mainly used for mapping memory required to execute the firmware. Contexts with non-zero IDs are user contexts allocated each time the devices is open()-ed and they map command buffers and other workload-related memory. Workloads executing in a given contexts have access only to the memory mapped in this context. This patch is has two main files: - ivpu_mmu_context.c handles MMU page tables and memory mapping - ivpu_mmu.c implements a driver that programs the MMU device

Jacek Lawrynowicz committed 3 years ago

Commit 263b2ba1 parent 35b13769 files · +1479 −3Browse files

Showing the changes to include/uapi (1 of 9 files). Show all

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include/uapi/drm/ivpu_accel.h+4−0
@@ -38,6 +38,7 @@ extern "C" { · 37 unmodified lines
3838 #define DRM_IVPU_PARAM_NUM_CONTEXTS 4
3939 #define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
4040 #define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6
41+#define DRM_IVPU_PARAM_CONTEXT_ID 7
4142
4243 #define DRM_IVPU_PLATFORM_TYPE_SILICON 0
4344
@@ -78,6 +79,9 @@ struct drm_ivpu_param { · 34 unmodified lines
7879 * Value of current context scheduling priority (read-write).
7980 * See DRM_IVPU_CONTEXT_PRIORITY_* for possible values.
8081 *
82+ * %DRM_IVPU_PARAM_CONTEXT_ID:
83+ * Current context ID, always greater than 0 (read-only)
84+ *
8185 */
8286 __u32 param;
8387

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