lael-labs/linux

drivers/gpu/drm/amd/amdgpu/Makefile+1−17

@@ -39,23 +39,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ · 38 unmodified lines
39	-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \	39	-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
40	-I$(FULL_AMD_PATH)/amdkfd	40	-I$(FULL_AMD_PATH)/amdkfd
41		41
42	subdir-ccflags-y := -Wextra	42	# Locally disable W=1 warnings enabled in drm subsystem Makefile
43	subdir-ccflags-y += -Wunused
44	subdir-ccflags-y += -Wmissing-prototypes
45	subdir-ccflags-y += -Wmissing-declarations
46	subdir-ccflags-y += -Wmissing-include-dirs
47	subdir-ccflags-y += -Wold-style-definition
48	subdir-ccflags-y += -Wmissing-format-attribute
49	# Need this to avoid recursive variable evaluation issues
50	cond-flags := $(call cc-option, -Wunused-but-set-variable) \
51	$(call cc-option, -Wunused-const-variable) \
52	$(call cc-option, -Wstringop-truncation) \
53	$(call cc-option, -Wpacked-not-aligned)
54	subdir-ccflags-y += $(cond-flags)
55	subdir-ccflags-y += -Wno-unused-parameter
56	subdir-ccflags-y += -Wno-type-limits
57	subdir-ccflags-y += -Wno-sign-compare
58	subdir-ccflags-y += -Wno-missing-field-initializers
59	subdir-ccflags-y += -Wno-override-init	43	subdir-ccflags-y += -Wno-override-init
60	subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror	44	subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror
61		45

drivers/gpu/drm/amd/amdgpu/amdgpu.h+1−0

@@ -237,6 +237,7 @@ extern int sched_policy; · 236 unmodified lines
237	extern bool debug_evictions;	237	extern bool debug_evictions;
238	extern bool no_system_mem_limit;	238	extern bool no_system_mem_limit;
239	extern int halt_if_hws_hang;	239	extern int halt_if_hws_hang;
		240	extern uint amdgpu_svm_default_granularity;
240	#else	241	#else
241	static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;	242	static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
242	static const bool __maybe_unused debug_evictions; /* = false */	243	static const bool __maybe_unused debug_evictions; /* = false */

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c+0−1

@@ -20,7 +20,6 @@ · 19 unmodified lines
20	* OTHER DEALINGS IN THE SOFTWARE.	20	* OTHER DEALINGS IN THE SOFTWARE.
21	*/	21	*/
22	#include <linux/module.h>	22	#include <linux/module.h>
23	#include <linux/fdtable.h>
24	#include <linux/uaccess.h>	23	#include <linux/uaccess.h>
25	#include <linux/firmware.h>	24	#include <linux/firmware.h>
26	#include "amdgpu.h"	25	#include "amdgpu.h"

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c+3−9

 #include <linux/pagemap.h>
 #include <linux/sched/mm.h>
 #include <linux/sched/task.h>
-#include <linux/fdtable.h>
 #include <drm/ttm/ttm_tt.h>
 #include <drm/drm_exec.h>
 	if (!mem->dmabuf) {
 		struct amdgpu_device *bo_adev;
 		struct dma_buf *dmabuf;
-		int r, fd;
 		bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
-		r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file,
+		dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file,
 					       mem->gem_handle,
 			mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
-					       DRM_RDWR : 0, &fd);
+					       DRM_RDWR : 0);
-		if (r)
+		if (IS_ERR(dmabuf))
-			return r;
-		dmabuf = dma_buf_get(fd);
-		close_fd(fd);
-		if (WARN_ON_ONCE(IS_ERR(dmabuf)))
 			return PTR_ERR(dmabuf);
 		mem->dmabuf = dmabuf;
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+17−0

@@ -169,6 +169,16 @@ uint amdgpu_sdma_phase_quantum = 32; · 168 unmodified lines
169	char *amdgpu_disable_cu;	169	char *amdgpu_disable_cu;
170	char *amdgpu_virtual_display;	170	char *amdgpu_virtual_display;
171	bool enforce_isolation;	171	bool enforce_isolation;
		172
		173	/* Specifies the default granularity for SVM, used in buffer
		174	* migration and restoration of backing memory when handling
		175	* recoverable page faults.
		176	*
		177	* The value is given as log(numPages(buffer)); for a 2 MiB
		178	* buffer it computes to be 9
		179	*/
		180	uint amdgpu_svm_default_granularity = 9;
		181
172	/*	182	/*
173	* OverDrive(bit 14) disabled by default	183	* OverDrive(bit 14) disabled by default
174	* GFX DCS(bit 19) disabled by default	184	* GFX DCS(bit 19) disabled by default
@@ -320,6 +330,13 @@ module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); · 145 unmodified lines
320	MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");	330	MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
321	module_param_named(msi, amdgpu_msi, int, 0444);	331	module_param_named(msi, amdgpu_msi, int, 0444);
322		332
		333	/**
		334	* DOC: svm_default_granularity (uint)
		335	* Used in buffer migration and handling of recoverable page faults
		336	*/
		337	MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB");
		338	module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644);
		339
323	/**	340	/**
324	* DOC: lockup_timeout (string)	341	* DOC: lockup_timeout (string)
325	* Set GPU scheduler timeout value in ms.	342	* Set GPU scheduler timeout value in ms.

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+19−16

 static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
-	long timeout = msecs_to_jiffies(1000);
+	struct drm_gpu_scheduler *sched = &ring->sched;
-	struct dma_fence *f = NULL;
+	struct drm_sched_entity entity;
+	struct dma_fence *f;
 	struct amdgpu_job *job;
 	struct amdgpu_ib *ib;
 	int i, r;
-	r = amdgpu_job_alloc_with_ib(adev, NULL, NULL,
+	/* Initialize the scheduler entity */
-				     64, AMDGPU_IB_POOL_DIRECT,
+	r = drm_sched_entity_init(&entity, DRM_SCHED_PRIORITY_NORMAL,
+				  &sched, 1, NULL);
+	if (r) {
+		dev_err(adev->dev, "Failed setting up GFX kernel entity.\n");
+		goto err;
+	}
+	r = amdgpu_job_alloc_with_ib(ring->adev, &entity, NULL,
+				     64, 0,
 				     &job);
 	if (r)
 		goto err;
 		ib->ptr[i] = ring->funcs->nop;
 	ib->length_dw = ring->funcs->align_mask + 1;
-	r = amdgpu_job_submit_direct(job, ring, &f);
+	f = amdgpu_job_submit(job);
-	if (r)
-		goto err_free;
-	r = dma_fence_wait_timeout(f, false, timeout);
+	r = dma_fence_wait(f, false);
-	if (r == 0)
+	if (r)
-		r = -ETIMEDOUT;
+		goto err;
-	else if (r > 0)
-		r = 0;
-	amdgpu_ib_free(adev, ib, f);
 	dma_fence_put(f);
+	/* Clean up the scheduler entity */
+	drm_sched_entity_destroy(&entity);
 	return 0;
-err_free:
-	amdgpu_job_free(job);
-	amdgpu_ib_free(adev, ib, f);
 err:
 	return r;
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c+1−0

@@ -832,6 +832,7 @@ int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, · 831 unmodified lines
832	struct mes_reset_queue_input queue_input;	832	struct mes_reset_queue_input queue_input;
833	int r;	833	int r;
834		834
		835	queue_input.queue_type = queue_type;
835	queue_input.use_mmio = true;	836	queue_input.use_mmio = true;
836	queue_input.me_id = me_id;	837	queue_input.me_id = me_id;
837	queue_input.pipe_id = pipe_id;	838	queue_input.pipe_id = pipe_id;

drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c+1−1

@@ -94,7 +94,7 @@ static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int n · 93 unmodified lines
94	ref_div_max = min(128 / post_div, ref_div_max);	94	ref_div_max = min(128 / post_div, ref_div_max);
95		95
96	/* get matching reference and feedback divider */	96	/* get matching reference and feedback divider */
97	*ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);	97	*ref_div = clamp(DIV_ROUND_CLOSEST(den, post_div), 1u, ref_div_max);
98	fb_div = DIV_ROUND_CLOSEST(nom ref_div post_div, den);	98	fb_div = DIV_ROUND_CLOSEST(nom ref_div post_div, den);
99		99
100	/* limit fb divider to its maximum */	100	/* limit fb divider to its maximum */

drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c+0−1

@@ -22,7 +22,6 @@ · 21 unmodified lines
22	* Authors: Andres Rodriguez <andresx7@gmail.com>	22	* Authors: Andres Rodriguez <andresx7@gmail.com>
23	*/	23	*/
24		24
25	#include <linux/fdtable.h>
26	#include <linux/file.h>	25	#include <linux/file.h>
27	#include <linux/pid.h>	26	#include <linux/pid.h>
28		27

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+57−42

@@ -844,7 +844,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, · 843 unmodified lines
844	params.vm = vm;	844	params.vm = vm;
845	params.immediate = immediate;	845	params.immediate = immediate;
846		846
847	r = vm->update_funcs->prepare(&params, NULL, AMDGPU_SYNC_EXPLICIT);	847	r = vm->update_funcs->prepare(&params, NULL);
848	if (r)	848	if (r)
849	goto error;	849	goto error;
850		850
@@ -908,10 +908,12 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, · 57 unmodified lines
908	{	908	{
909	struct amdgpu_vm *vm = params->vm;	909	struct amdgpu_vm *vm = params->vm;
910		910
911	if (!fence \|\| !*fence)	911	tlb_cb->vm = vm;
		912	if (!fence \|\| !*fence) {
		913	amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
912	return;	914	return;
		915	}
913		916
914	tlb_cb->vm = vm;
915	if (!dma_fence_add_callback(*fence, &tlb_cb->cb,	917	if (!dma_fence_add_callback(*fence, &tlb_cb->cb,
916	amdgpu_vm_tlb_seq_cb)) {	918	amdgpu_vm_tlb_seq_cb)) {
917	dma_fence_put(vm->last_tlb_flush);	919	dma_fence_put(vm->last_tlb_flush);
@@ -939,7 +941,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, · 21 unmodified lines
939	* @unlocked: unlocked invalidation during MM callback	941	* @unlocked: unlocked invalidation during MM callback
940	* @flush_tlb: trigger tlb invalidation after update completed	942	* @flush_tlb: trigger tlb invalidation after update completed
941	* @allow_override: change MTYPE for local NUMA nodes	943	* @allow_override: change MTYPE for local NUMA nodes
942	* @resv: fences we need to sync to	944	* @sync: fences we need to sync to
943	* @start: start of mapped range	945	* @start: start of mapped range
944	* @last: last mapped entry	946	* @last: last mapped entry
945	* @flags: flags for the entries	947	* @flags: flags for the entries
@@ -955,16 +957,16 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, · 9 unmodified lines
955	* 0 for success, negative erro code for failure.	957	* 0 for success, negative erro code for failure.
956	*/	958	*/
957	int amdgpu_vm_update_range(struct amdgpu_device adev, struct amdgpu_vm vm,	959	int amdgpu_vm_update_range(struct amdgpu_device adev, struct amdgpu_vm vm,
958	bool immediate, bool unlocked, bool flush_tlb, bool allow_override,	960	bool immediate, bool unlocked, bool flush_tlb,
959	struct dma_resv *resv, uint64_t start, uint64_t last,	961	bool allow_override, struct amdgpu_sync *sync,
960	uint64_t flags, uint64_t offset, uint64_t vram_base,	962	uint64_t start, uint64_t last, uint64_t flags,
		963	uint64_t offset, uint64_t vram_base,
961	struct ttm_resource res, dma_addr_t pages_addr,	964	struct ttm_resource res, dma_addr_t pages_addr,
962	struct dma_fence **fence)	965	struct dma_fence **fence)
963	{	966	{
964	struct amdgpu_vm_tlb_seq_struct *tlb_cb;	967	struct amdgpu_vm_tlb_seq_struct *tlb_cb;
965	struct amdgpu_vm_update_params params;	968	struct amdgpu_vm_update_params params;
966	struct amdgpu_res_cursor cursor;	969	struct amdgpu_res_cursor cursor;
967	enum amdgpu_sync_mode sync_mode;
968	int r, idx;	970	int r, idx;
969		971
970	if (!drm_dev_enter(adev_to_drm(adev), &idx))	972	if (!drm_dev_enter(adev_to_drm(adev), &idx))
@@ -997,14 +999,6 @@ int amdgpu_vm_update_range(struct amdgpu_device adev, struct amdgpu_vm vm, · 26 unmodified lines
997	params.allow_override = allow_override;	999	params.allow_override = allow_override;
998	INIT_LIST_HEAD(&params.tlb_flush_waitlist);	1000	INIT_LIST_HEAD(&params.tlb_flush_waitlist);
999		1001
1000	/* Implicitly sync to command submissions in the same VM before
1001	* unmapping. Sync to moving fences before mapping.
1002	*/
1003	if (!(flags & AMDGPU_PTE_VALID))
1004	sync_mode = AMDGPU_SYNC_EQ_OWNER;
1005	else
1006	sync_mode = AMDGPU_SYNC_EXPLICIT;
1007
1008	amdgpu_vm_eviction_lock(vm);	1002	amdgpu_vm_eviction_lock(vm);
1009	if (vm->evicting) {	1003	if (vm->evicting) {
1010	r = -EBUSY;	1004	r = -EBUSY;
@@ -1019,7 +1013,7 @@ int amdgpu_vm_update_range(struct amdgpu_device adev, struct amdgpu_vm vm, · 8 unmodified lines
1019	dma_fence_put(tmp);	1013	dma_fence_put(tmp);
1020	}	1014	}
1021		1015
1022	r = vm->update_funcs->prepare(&params, resv, sync_mode);	1016	r = vm->update_funcs->prepare(&params, sync);
1023	if (r)	1017	if (r)
1024	goto error_free;	1018	goto error_free;
1025		1019
@@ -1161,23 +1155,30 @@ int amdgpu_vm_bo_update(struct amdgpu_device adev, struct amdgpu_bo_va bo_va, · 135 unmodified lines
1161	struct amdgpu_bo *bo = bo_va->base.bo;	1155	struct amdgpu_bo *bo = bo_va->base.bo;
1162	struct amdgpu_vm *vm = bo_va->base.vm;	1156	struct amdgpu_vm *vm = bo_va->base.vm;
1163	struct amdgpu_bo_va_mapping *mapping;	1157	struct amdgpu_bo_va_mapping *mapping;
		1158	struct dma_fence **last_update;
1164	dma_addr_t *pages_addr = NULL;	1159	dma_addr_t *pages_addr = NULL;
1165	struct ttm_resource *mem;	1160	struct ttm_resource *mem;
1166	struct dma_fence **last_update;	1161	struct amdgpu_sync sync;
1167	bool flush_tlb = clear;	1162	bool flush_tlb = clear;
1168	bool uncached;
1169	struct dma_resv *resv;
1170	uint64_t vram_base;	1163	uint64_t vram_base;
1171	uint64_t flags;	1164	uint64_t flags;
		1165	bool uncached;
1172	int r;	1166	int r;
1173		1167
		1168	amdgpu_sync_create(&sync);
1174	if (clear \|\| !bo) {	1169	if (clear \|\| !bo) {
1175	mem = NULL;	1170	mem = NULL;
1176	resv = vm->root.bo->tbo.base.resv;	1171
		1172	/* Implicitly sync to command submissions in the same VM before
		1173	* unmapping.
		1174	*/
		1175	r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
		1176	AMDGPU_SYNC_EQ_OWNER, vm);
		1177	if (r)
		1178	goto error_free;
1177	} else {	1179	} else {
1178	struct drm_gem_object *obj = &bo->tbo.base;	1180	struct drm_gem_object *obj = &bo->tbo.base;
1179		1181
1180	resv = bo->tbo.base.resv;
1181	if (obj->import_attach && bo_va->is_xgmi) {	1182	if (obj->import_attach && bo_va->is_xgmi) {
1182	struct dma_buf *dma_buf = obj->import_attach->dmabuf;	1183	struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1183	struct drm_gem_object *gobj = dma_buf->priv;	1184	struct drm_gem_object *gobj = dma_buf->priv;
@@ -1191,6 +1192,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device adev, struct amdgpu_bo_va bo_va, · 7 unmodified lines
1191	if (mem && (mem->mem_type == TTM_PL_TT \|\|	1192	if (mem && (mem->mem_type == TTM_PL_TT \|\|
1192	mem->mem_type == AMDGPU_PL_PREEMPT))	1193	mem->mem_type == AMDGPU_PL_PREEMPT))
1193	pages_addr = bo->tbo.ttm->dma_address;	1194	pages_addr = bo->tbo.ttm->dma_address;
		1195
		1196	/* Implicitly sync to moving fences before mapping anything */
		1197	r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
		1198	AMDGPU_SYNC_EXPLICIT, vm);
		1199	if (r)
		1200	goto error_free;
1194	}	1201	}
1195		1202
1196	if (bo) {	1203	if (bo) {
@@ -1240,12 +1247,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device adev, struct amdgpu_bo_va bo_va, · 43 unmodified lines
1240	trace_amdgpu_vm_bo_update(mapping);	1247	trace_amdgpu_vm_bo_update(mapping);
1241		1248
1242	r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,	1249	r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1243	!uncached, resv, mapping->start, mapping->last,	1250	!uncached, &sync, mapping->start,
1244	update_flags, mapping->offset,	1251	mapping->last, update_flags,
1245	vram_base, mem, pages_addr,	1252	mapping->offset, vram_base, mem,
1246	last_update);	1253	pages_addr, last_update);
1247	if (r)	1254	if (r)
1248	return r;	1255	goto error_free;
1249	}	1256	}
1250		1257
1251	/* If the BO is not in its preferred location add it back to	1258	/* If the BO is not in its preferred location add it back to
@@ -1273,7 +1280,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device adev, struct amdgpu_bo_va bo_va, · 21 unmodified lines
1273	trace_amdgpu_vm_bo_mapping(mapping);	1280	trace_amdgpu_vm_bo_mapping(mapping);
1274	}	1281	}
1275		1282
1276	return 0;	1283	error_free:
		1284	amdgpu_sync_free(&sync);
		1285	return r;
1277	}	1286	}
1278		1287
1279	/**	1288	/**
@@ -1420,25 +1429,34 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, · 140 unmodified lines
1420	struct amdgpu_vm *vm,	1429	struct amdgpu_vm *vm,
1421	struct dma_fence **fence)	1430	struct dma_fence **fence)
1422	{	1431	{
1423	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1424	struct amdgpu_bo_va_mapping *mapping;	1432	struct amdgpu_bo_va_mapping *mapping;
1425	uint64_t init_pte_value = 0;
1426	struct dma_fence *f = NULL;	1433	struct dma_fence *f = NULL;
		1434	struct amdgpu_sync sync;
1427	int r;	1435	int r;
1428		1436
		1437
		1438	/*
		1439	* Implicitly sync to command submissions in the same VM before
		1440	* unmapping.
		1441	*/
		1442	amdgpu_sync_create(&sync);
		1443	r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
		1444	AMDGPU_SYNC_EQ_OWNER, vm);
		1445	if (r)
		1446	goto error_free;
		1447
1429	while (!list_empty(&vm->freed)) {	1448	while (!list_empty(&vm->freed)) {
1430	mapping = list_first_entry(&vm->freed,	1449	mapping = list_first_entry(&vm->freed,
1431	struct amdgpu_bo_va_mapping, list);	1450	struct amdgpu_bo_va_mapping, list);
1432	list_del(&mapping->list);	1451	list_del(&mapping->list);
1433		1452
1434	r = amdgpu_vm_update_range(adev, vm, false, false, true, false,	1453	r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1435	resv, mapping->start, mapping->last,	1454	&sync, mapping->start, mapping->last,
1436	init_pte_value, 0, 0, NULL, NULL,	1455	0, 0, 0, NULL, NULL, &f);
1437	&f);
1438	amdgpu_vm_free_mapping(adev, vm, mapping, f);	1456	amdgpu_vm_free_mapping(adev, vm, mapping, f);
1439	if (r) {	1457	if (r) {
1440	dma_fence_put(f);	1458	dma_fence_put(f);
1441	return r;	1459	goto error_free;
1442	}	1460	}
1443	}	1461	}
1444		1462
@@ -1449,7 +1467,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, · 4 unmodified lines
1449	dma_fence_put(f);	1467	dma_fence_put(f);
1450	}	1468	}
1451		1469
1452	return 0;	1470	error_free:
		1471	amdgpu_sync_free(&sync);
		1472	return r;
1453		1473
1454	}	1474	}
1455		1475
@@ -2224,7 +2244,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, · 768 unmodified lines
2224	phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +	2244	phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2225	(1 << 30) - 1) >> 30;	2245	(1 << 30) - 1) >> 30;
2226	vm_size = roundup_pow_of_two(	2246	vm_size = roundup_pow_of_two(
2227	min(max(phys_ram_gb * 3, min_vm_size), max_size));	2247	clamp(phys_ram_gb * 3, min_vm_size, max_size));
2228	}	2248	}
2229		2249
2230	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;	2250	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
@@ -2403,7 +2423,6 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) · 172 unmodified lines
2403	int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm,	2423	int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm,
2404	int32_t xcp_id)	2424	int32_t xcp_id)
2405	{	2425	{
2406	struct amdgpu_ip_block *ip_block;
2407	struct amdgpu_bo *root_bo;	2426	struct amdgpu_bo *root_bo;
2408	struct amdgpu_bo_vm *root;	2427	struct amdgpu_bo_vm *root;
2409	int r, i;	2428	int r, i;
@@ -2435,11 +2454,6 @@ int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm, · 25 unmodified lines
2435	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &	2454	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2436	AMDGPU_VM_USE_CPU_FOR_GFX);	2455	AMDGPU_VM_USE_CPU_FOR_GFX);
2437		2456
2438	/* use CPU for page table update if SDMA is unavailable */
2439	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SDMA);
2440	if (!ip_block \|\| ip_block->status.valid == false)
2441	vm->use_cpu_for_update = true;
2442
2443	DRM_DEBUG_DRIVER("VM update mode is %s\n",	2457	DRM_DEBUG_DRIVER("VM update mode is %s\n",
2444	vm->use_cpu_for_update ? "CPU" : "SDMA");	2458	vm->use_cpu_for_update ? "CPU" : "SDMA");
2445	WARN_ONCE((vm->use_cpu_for_update &&	2459	WARN_ONCE((vm->use_cpu_for_update &&
@@ -2770,6 +2784,7 @@ int amdgpu_vm_ioctl(struct drm_device dev, void data, struct drm_file *filp) · 324 unmodified lines
2770	* amdgpu_vm_handle_fault - graceful handling of VM faults.	2784	* amdgpu_vm_handle_fault - graceful handling of VM faults.
2771	* @adev: amdgpu device pointer	2785	* @adev: amdgpu device pointer
2772	* @pasid: PASID of the VM	2786	* @pasid: PASID of the VM
		2787	* @ts: Timestamp of the fault
2773	* @vmid: VMID, only used for GFX 9.4.3.	2788	* @vmid: VMID, only used for GFX 9.4.3.
2774	* @node_id: Node_id received in IH cookie. Only applicable for	2789	* @node_id: Node_id received in IH cookie. Only applicable for
2775	* GFX 9.4.3.	2790	* GFX 9.4.3.

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+6−5

 struct amdgpu_vm_update_funcs {
 	int (*map_table)(struct amdgpu_bo_vm *bo);
-	int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
+	int (*prepare)(struct amdgpu_vm_update_params *p,
-		       enum amdgpu_sync_mode sync_mode);
+		       struct amdgpu_sync *sync);
 	int (*update)(struct amdgpu_vm_update_params *p,
 		      struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
 		      unsigned count, uint32_t incr, uint64_t flags);
 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
 			    struct amdgpu_vm *vm, struct amdgpu_bo *bo);
 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-			   bool immediate, bool unlocked, bool flush_tlb, bool allow_override,
+			   bool immediate, bool unlocked, bool flush_tlb,
-			   struct dma_resv *resv, uint64_t start, uint64_t last,
+			   bool allow_override, struct amdgpu_sync *sync,
-			   uint64_t flags, uint64_t offset, uint64_t vram_base,
+			   uint64_t start, uint64_t last, uint64_t flags,
+			   uint64_t offset, uint64_t vram_base,
 			   struct ttm_resource *res, dma_addr_t *pages_addr,
 			   struct dma_fence **fence);
 int amdgpu_vm_bo_update(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c+4−6

  * amdgpu_vm_cpu_prepare - prepare page table update with the CPU
  *
  * @p: see amdgpu_vm_update_params definition
- * @resv: reservation object with embedded fence
+ * @sync: sync obj with fences to wait on
- * @sync_mode: synchronization mode
  *
  * Returns:
  * Negativ errno, 0 for success.
  */
 static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
-				 struct dma_resv *resv,
+				 struct amdgpu_sync *sync)
-				 enum amdgpu_sync_mode sync_mode)
 {
-	if (!resv)
+	if (!sync)
 		return 0;
-	return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, p->vm, true);
+	return amdgpu_sync_wait(sync, true);
 }
 /**

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c+1−1

@@ -403,7 +403,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device adev, struct amdgpu_vm vm, · 402 unmodified lines
403	params.vm = vm;	403	params.vm = vm;
404	params.immediate = immediate;	404	params.immediate = immediate;
405		405
406	r = vm->update_funcs->prepare(&params, NULL, AMDGPU_SYNC_EXPLICIT);	406	r = vm->update_funcs->prepare(&params, NULL);
407	if (r)	407	if (r)
408	goto exit;	408	goto exit;
409		409

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c+4−12

  * amdgpu_vm_sdma_prepare - prepare SDMA command submission
  *
  * @p: see amdgpu_vm_update_params definition
- * @resv: reservation object with embedded fence
+ * @sync: amdgpu_sync object with fences to wait for
- * @sync_mode: synchronization mode
  *
  * Returns:
  * Negativ errno, 0 for success.
  */
 static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
-				  struct dma_resv *resv,
+				  struct amdgpu_sync *sync)
-				  enum amdgpu_sync_mode sync_mode)
 {
-	struct amdgpu_sync sync;
 	int r;
 	r = amdgpu_vm_sdma_alloc_job(p, 0);
 	if (r)
 		return r;
-	if (!resv)
+	if (!sync)
 		return 0;
-	amdgpu_sync_create(&sync);
+	r = amdgpu_sync_push_to_job(sync, p->job);
-	r = amdgpu_sync_resv(p->adev, &sync, resv, sync_mode, p->vm);
-	if (!r)
-		r = amdgpu_sync_push_to_job(&sync, p->job);
-	amdgpu_sync_free(&sync);
 	if (r) {
 		p->num_dw_left = 0;
 		amdgpu_job_free(p->job);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+4−0

 	{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
 	/* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */
 	{ 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 },
+	/* https://bbs.openkylin.top/t/topic/171497 */
+	{ 0x1002, 0x15d8, 0x19e5, 0x3e14, 0xc2 },
+	/* HP 705G4 DM with R5 2400G */
+	{ 0x1002, 0x15dd, 0x103c, 0x8464, 0xd6 },
 	{ 0, 0, 0, 0, 0 },
 };

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c+75−1

@@ -23,6 +23,7 @@ · 22 unmodified lines
23		23
24	#include "amdgpu.h"	24	#include "amdgpu.h"
25	#include "amdgpu_jpeg.h"	25	#include "amdgpu_jpeg.h"
		26	#include "amdgpu_cs.h"
26	#include "soc15.h"	27	#include "soc15.h"
27	#include "soc15d.h"	28	#include "soc15d.h"
28	#include "vcn_v1_0.h"	29	#include "vcn_v1_0.h"
@@ -34,6 +35,9 @@ · 5 unmodified lines
34	static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);	35	static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
35	static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);	36	static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
36	static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);	37	static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);
		38	static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
		39	struct amdgpu_job *job,
		40	struct amdgpu_ib *ib);
37		41
38	static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring ring, uint32_t ptr, uint32_t reg_offset, uint32_t val)	42	static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring ring, uint32_t ptr, uint32_t reg_offset, uint32_t val)
39	{	43	{
@@ -300,7 +304,10 @@ static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring, · 260 unmodified lines
300		304
301	amdgpu_ring_write(ring,	305	amdgpu_ring_write(ring,
302	PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));	306	PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
303	amdgpu_ring_write(ring, (vmid \| (vmid << 4)));	307	if (ring->funcs->parse_cs)
		308	amdgpu_ring_write(ring, 0);
		309	else
		310	amdgpu_ring_write(ring, (vmid \| (vmid << 4)));
304		311
305	amdgpu_ring_write(ring,	312	amdgpu_ring_write(ring,
306	PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));	313	PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
@@ -554,6 +561,7 @@ static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = { · 247 unmodified lines
554	.get_rptr = jpeg_v1_0_decode_ring_get_rptr,	561	.get_rptr = jpeg_v1_0_decode_ring_get_rptr,
555	.get_wptr = jpeg_v1_0_decode_ring_get_wptr,	562	.get_wptr = jpeg_v1_0_decode_ring_get_wptr,
556	.set_wptr = jpeg_v1_0_decode_ring_set_wptr,	563	.set_wptr = jpeg_v1_0_decode_ring_set_wptr,
		564	.parse_cs = jpeg_v1_dec_ring_parse_cs,
557	.emit_frame_size =	565	.emit_frame_size =
558	6 + 6 + /* hdp invalidate / flush */	566	6 + 6 + /* hdp invalidate / flush */
559	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +	567	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
@@ -611,3 +619,69 @@ static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring) · 51 unmodified lines
611		619
612	vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);	620	vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
613	}	621	}
		622
		623	/**
		624	* jpeg_v1_dec_ring_parse_cs - command submission parser
		625	*
		626	* @parser: Command submission parser context
		627	* @job: the job to parse
		628	* @ib: the IB to parse
		629	*
		630	* Parse the command stream, return -EINVAL for invalid packet,
		631	* 0 otherwise
		632	*/
		633	static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
		634	struct amdgpu_job *job,
		635	struct amdgpu_ib *ib)
		636	{
		637	u32 i, reg, res, cond, type;
		638	int ret = 0;
		639	struct amdgpu_device *adev = parser->adev;
		640
		641	for (i = 0; i < ib->length_dw ; i += 2) {
		642	reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
		643	res = CP_PACKETJ_GET_RES(ib->ptr[i]);
		644	cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
		645	type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
		646
		647	if (res \|\| cond != PACKETJ_CONDITION_CHECK0) /* only allow 0 for now */
		648	return -EINVAL;
		649
		650	if (reg >= JPEG_V1_REG_RANGE_START && reg <= JPEG_V1_REG_RANGE_END)
		651	continue;
		652
		653	switch (type) {
		654	case PACKETJ_TYPE0:
		655	if (reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH &&
		656	reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW &&
		657	reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH &&
		658	reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW &&
		659	reg != JPEG_V1_REG_CTX_INDEX &&
		660	reg != JPEG_V1_REG_CTX_DATA) {
		661	ret = -EINVAL;
		662	}
		663	break;
		664	case PACKETJ_TYPE1:
		665	if (reg != JPEG_V1_REG_CTX_DATA)
		666	ret = -EINVAL;
		667	break;
		668	case PACKETJ_TYPE3:
		669	if (reg != JPEG_V1_REG_SOFT_RESET)
		670	ret = -EINVAL;
		671	break;
		672	case PACKETJ_TYPE6:
		673	if (ib->ptr[i] != CP_PACKETJ_NOP)
		674	ret = -EINVAL;
		675	break;
		676	default:
		677	ret = -EINVAL;
		678	}
		679
		680	if (ret) {
		681	dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
		682	break;
		683	}
		684	}
		685
		686	return ret;
		687	}

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h+11−0

@@ -29,4 +29,15 @@ int jpeg_v1_0_sw_init(void *handle); · 28 unmodified lines
29	void jpeg_v1_0_sw_fini(void *handle);	29	void jpeg_v1_0_sw_fini(void *handle);
30	void jpeg_v1_0_start(struct amdgpu_device *adev, int mode);	30	void jpeg_v1_0_start(struct amdgpu_device *adev, int mode);
31		31
		32	#define JPEG_V1_REG_RANGE_START 0x8000
		33	#define JPEG_V1_REG_RANGE_END 0x803f
		34
		35	#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x8238
		36	#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x8239
		37	#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH 0x825a
		38	#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW 0x825b
		39	#define JPEG_V1_REG_CTX_INDEX 0x8328
		40	#define JPEG_V1_REG_CTX_DATA 0x8329
		41	#define JPEG_V1_REG_SOFT_RESET 0x83a0
		42
32	#endif /__JPEG_V1_0_H__/	43	#endif /__JPEG_V1_0_H__/

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c+62−1

@@ -23,6 +23,7 @@ · 22 unmodified lines
23		23
24	#include "amdgpu.h"	24	#include "amdgpu.h"
25	#include "amdgpu_jpeg.h"	25	#include "amdgpu_jpeg.h"
		26	#include "amdgpu_cs.h"
26	#include "amdgpu_pm.h"	27	#include "amdgpu_pm.h"
27	#include "soc15.h"	28	#include "soc15.h"
28	#include "soc15d.h"	29	#include "soc15d.h"
@@ -538,7 +539,11 @@ void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, · 509 unmodified lines
538		539
539	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,	540	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
540	0, 0, PACKETJ_TYPE0));	541	0, 0, PACKETJ_TYPE0));
541	amdgpu_ring_write(ring, (vmid \| (vmid << 4) \| (vmid << 8)));	542
		543	if (ring->funcs->parse_cs)
		544	amdgpu_ring_write(ring, 0);
		545	else
		546	amdgpu_ring_write(ring, (vmid \| (vmid << 4) \| (vmid << 8)));
542		547
543	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,	548	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
544	0, 0, PACKETJ_TYPE0));	549	0, 0, PACKETJ_TYPE0));
@@ -764,6 +769,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { · 219 unmodified lines
764	.get_rptr = jpeg_v2_0_dec_ring_get_rptr,	769	.get_rptr = jpeg_v2_0_dec_ring_get_rptr,
765	.get_wptr = jpeg_v2_0_dec_ring_get_wptr,	770	.get_wptr = jpeg_v2_0_dec_ring_get_wptr,
766	.set_wptr = jpeg_v2_0_dec_ring_set_wptr,	771	.set_wptr = jpeg_v2_0_dec_ring_set_wptr,
		772	.parse_cs = jpeg_v2_dec_ring_parse_cs,
767	.emit_frame_size =	773	.emit_frame_size =
768	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +	774	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
769	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +	775	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -810,3 +816,58 @@ const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = { · 40 unmodified lines
810	.rev = 0,	816	.rev = 0,
811	.funcs = &jpeg_v2_0_ip_funcs,	817	.funcs = &jpeg_v2_0_ip_funcs,
812	};	818	};
		819
		820	/**
		821	* jpeg_v2_dec_ring_parse_cs - command submission parser
		822	*
		823	* @parser: Command submission parser context
		824	* @job: the job to parse
		825	* @ib: the IB to parse
		826	*
		827	* Parse the command stream, return -EINVAL for invalid packet,
		828	* 0 otherwise
		829	*/
		830	int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
		831	struct amdgpu_job *job,
		832	struct amdgpu_ib *ib)
		833	{
		834	u32 i, reg, res, cond, type;
		835	struct amdgpu_device *adev = parser->adev;
		836
		837	for (i = 0; i < ib->length_dw ; i += 2) {
		838	reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
		839	res = CP_PACKETJ_GET_RES(ib->ptr[i]);
		840	cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
		841	type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
		842
		843	if (res) /* only support 0 at the moment */
		844	return -EINVAL;
		845
		846	switch (type) {
		847	case PACKETJ_TYPE0:
		848	if (cond != PACKETJ_CONDITION_CHECK0 \|\| reg < JPEG_REG_RANGE_START \|\|
		849	reg > JPEG_REG_RANGE_END) {
		850	dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
		851	return -EINVAL;
		852	}
		853	break;
		854	case PACKETJ_TYPE3:
		855	if (cond != PACKETJ_CONDITION_CHECK3 \|\| reg < JPEG_REG_RANGE_START \|\|
		856	reg > JPEG_REG_RANGE_END) {
		857	dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
		858	return -EINVAL;
		859	}
		860	break;
		861	case PACKETJ_TYPE6:
		862	if (ib->ptr[i] == CP_PACKETJ_NOP)
		863	continue;
		864	dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
		865	return -EINVAL;
		866	default:
		867	dev_err(adev->dev, "Unknown packet type %d !\n", type);
		868	return -EINVAL;
		869	}
		870	}
		871
		872	return 0;
		873	}

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h+6−0

 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000
+#define JPEG_REG_RANGE_START						0x4000
+#define JPEG_REG_RANGE_END						0x41c2
 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 				unsigned vmid, uint64_t pd_addr);
 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
+int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
+			      struct amdgpu_job *job,
+			      struct amdgpu_ib *ib);
 extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c+2−0

 	.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
 	.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
 	.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
+	.parse_cs = jpeg_v2_dec_ring_parse_cs,
 	.emit_frame_size =
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 	.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
 	.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
 	.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
+	.parse_cs = jpeg_v2_dec_ring_parse_cs,
 	.emit_frame_size =
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c+1−0

@@ -560,6 +560,7 @@ static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { · 559 unmodified lines
560	.get_rptr = jpeg_v3_0_dec_ring_get_rptr,	560	.get_rptr = jpeg_v3_0_dec_ring_get_rptr,
561	.get_wptr = jpeg_v3_0_dec_ring_get_wptr,	561	.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
562	.set_wptr = jpeg_v3_0_dec_ring_set_wptr,	562	.set_wptr = jpeg_v3_0_dec_ring_set_wptr,
		563	.parse_cs = jpeg_v2_dec_ring_parse_cs,
563	.emit_frame_size =	564	.emit_frame_size =
564	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +	565	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
565	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +	566	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c+1−0

@@ -727,6 +727,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { · 726 unmodified lines
727	.get_rptr = jpeg_v4_0_dec_ring_get_rptr,	727	.get_rptr = jpeg_v4_0_dec_ring_get_rptr,
728	.get_wptr = jpeg_v4_0_dec_ring_get_wptr,	728	.get_wptr = jpeg_v4_0_dec_ring_get_wptr,
729	.set_wptr = jpeg_v4_0_dec_ring_set_wptr,	729	.set_wptr = jpeg_v4_0_dec_ring_set_wptr,
		730	.parse_cs = jpeg_v2_dec_ring_parse_cs,
730	.emit_frame_size =	731	.emit_frame_size =
731	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +	732	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
732	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +	733	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h+0−1

@@ -32,5 +32,4 @@ enum amdgpu_jpeg_v4_0_sub_block { · 31 unmodified lines
32	};	32	};
33		33
34	extern const struct amdgpu_ip_block_version jpeg_v4_0_ip_block;	34	extern const struct amdgpu_ip_block_version jpeg_v4_0_ip_block;
35
36	#endif /* __JPEG_V4_0_H__ */	35	#endif /* __JPEG_V4_0_H__ */

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c+17−76

@@ -23,9 +23,9 @@ · 22 unmodified lines
23		23
24	#include "amdgpu.h"	24	#include "amdgpu.h"
25	#include "amdgpu_jpeg.h"	25	#include "amdgpu_jpeg.h"
26	#include "amdgpu_cs.h"
27	#include "soc15.h"	26	#include "soc15.h"
28	#include "soc15d.h"	27	#include "soc15d.h"
		28	#include "jpeg_v2_0.h"
29	#include "jpeg_v4_0_3.h"	29	#include "jpeg_v4_0_3.h"
30	#include "mmsch_v4_0_3.h"	30	#include "mmsch_v4_0_3.h"
31		31
@@ -59,6 +59,12 @@ static int amdgpu_ih_srcid_jpeg[] = { · 27 unmodified lines
59	VCN_4_0__SRCID__JPEG7_DECODE	59	VCN_4_0__SRCID__JPEG7_DECODE
60	};	60	};
61		61
		62	static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
		63	{
		64	return amdgpu_sriov_vf(adev) \|\|
		65	(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4));
		66	}
		67
62	/**	68	/**
63	* jpeg_v4_0_3_early_init - set function pointers	69	* jpeg_v4_0_3_early_init - set function pointers
64	*	70	*
@@ -734,32 +740,20 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq · 669 unmodified lines
734	0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));	740	0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
735	amdgpu_ring_write(ring, 0);	741	amdgpu_ring_write(ring, 0);
736		742
737	if (ring->adev->jpeg.inst[ring->me].aid_id) {	743	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
738	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,	744	amdgpu_ring_write(ring, 0);
739	0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
740	amdgpu_ring_write(ring, 0x4);
741	} else {
742	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
743	amdgpu_ring_write(ring, 0);
744	}
745		745
746	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,	746	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
747	0, 0, PACKETJ_TYPE0));	747	0, 0, PACKETJ_TYPE0));
748	amdgpu_ring_write(ring, 0x3fbc);	748	amdgpu_ring_write(ring, 0x3fbc);
749		749
750	if (ring->adev->jpeg.inst[ring->me].aid_id) {
751	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
752	0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
753	amdgpu_ring_write(ring, 0x0);
754	} else {
755	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
756	amdgpu_ring_write(ring, 0);
757	}
758
759	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,	750	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
760	0, 0, PACKETJ_TYPE0));	751	0, 0, PACKETJ_TYPE0));
761	amdgpu_ring_write(ring, 0x1);	752	amdgpu_ring_write(ring, 0x1);
762		753
		754	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
		755	amdgpu_ring_write(ring, 0);
		756
763	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));	757	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
764	amdgpu_ring_write(ring, 0);	758	amdgpu_ring_write(ring, 0);
765	}	759	}
@@ -834,8 +828,8 @@ void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, · 68 unmodified lines
834	{	828	{
835	uint32_t reg_offset;	829	uint32_t reg_offset;
836		830
837	/* For VF, only local offsets should be used */	831	/* Use normalized offsets if required */
838	if (amdgpu_sriov_vf(ring->adev))	832	if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
839	reg = NORMALIZE_JPEG_REG_OFFSET(reg);	833	reg = NORMALIZE_JPEG_REG_OFFSET(reg);
840		834
841	reg_offset = (reg << 2);	835	reg_offset = (reg << 2);
@@ -881,8 +875,8 @@ void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint · 39 unmodified lines
881	{	875	{
882	uint32_t reg_offset;	876	uint32_t reg_offset;
883		877
884	/* For VF, only local offsets should be used */	878	/* Use normalized offsets if required */
885	if (amdgpu_sriov_vf(ring->adev))	879	if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
886	reg = NORMALIZE_JPEG_REG_OFFSET(reg);	880	reg = NORMALIZE_JPEG_REG_OFFSET(reg);
887		881
888	reg_offset = (reg << 2);	882	reg_offset = (reg << 2);
@@ -1089,7 +1083,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { · 200 unmodified lines
1089	.get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,	1083	.get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,
1090	.get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,	1084	.get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,
1091	.set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,	1085	.set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,
1092	.parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,	1086	.parse_cs = jpeg_v2_dec_ring_parse_cs,
1093	.emit_frame_size =	1087	.emit_frame_size =
1094	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +	1088	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1095	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +	1089	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -1254,56 +1248,3 @@ static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) · 158 unmodified lines
1254	{	1248	{
1255	adev->jpeg.ras = &jpeg_v4_0_3_ras;	1249	adev->jpeg.ras = &jpeg_v4_0_3_ras;
1256	}	1250	}
1257
1258	/**
1259	* jpeg_v4_0_3_dec_ring_parse_cs - command submission parser
1260	*
1261	* @parser: Command submission parser context
1262	* @job: the job to parse
1263	* @ib: the IB to parse
1264	*
1265	* Parse the command stream, return -EINVAL for invalid packet,
1266	* 0 otherwise
1267	*/
1268	int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
1269	struct amdgpu_job *job,
1270	struct amdgpu_ib *ib)
1271	{
1272	uint32_t i, reg, res, cond, type;
1273	struct amdgpu_device *adev = parser->adev;
1274
1275	for (i = 0; i < ib->length_dw ; i += 2) {
1276	reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
1277	res = CP_PACKETJ_GET_RES(ib->ptr[i]);
1278	cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
1279	type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
1280
1281	if (res) /* only support 0 at the moment */
1282	return -EINVAL;
1283
1284	switch (type) {
1285	case PACKETJ_TYPE0:
1286	if (cond != PACKETJ_CONDITION_CHECK0 \|\| reg < JPEG_REG_RANGE_START \|\| reg > JPEG_REG_RANGE_END) {
1287	dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1288	return -EINVAL;
1289	}
1290	break;
1291	case PACKETJ_TYPE3:
1292	if (cond != PACKETJ_CONDITION_CHECK3 \|\| reg < JPEG_REG_RANGE_START \|\| reg > JPEG_REG_RANGE_END) {
1293	dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1294	return -EINVAL;
1295	}
1296	break;
1297	case PACKETJ_TYPE6:
1298	if (ib->ptr[i] == CP_PACKETJ_NOP)
1299	continue;
1300	dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1301	return -EINVAL;
1302	default:
1303	dev_err(adev->dev, "Unknown packet type %d !\n", type);
1304	return -EINVAL;
1305	}
1306	}
1307
1308	return 0;
1309	}

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h+1−6

@@ -46,9 +46,6 @@ · 45 unmodified lines
46		46
47	#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000	47	#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
48		48
49	#define JPEG_REG_RANGE_START 0x4000
50	#define JPEG_REG_RANGE_END 0x41c2
51
52	extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;	49	extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;
53		50
54	void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,	51	void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
@@ -65,7 +62,5 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring); · 10 unmodified lines
65	void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);	62	void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
66	void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,	63	void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
67	uint32_t val, uint32_t mask);	64	uint32_t val, uint32_t mask);
68	int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,	65
69	struct amdgpu_job *job,
70	struct amdgpu_ib *ib);
71	#endif /* __JPEG_V4_0_3_H__ */	66	#endif /* __JPEG_V4_0_3_H__ */

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c+1−0

@@ -768,6 +768,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = { · 767 unmodified lines
768	.get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,	768	.get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,
769	.get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,	769	.get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,
770	.set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,	770	.set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,
		771	.parse_cs = jpeg_v2_dec_ring_parse_cs,
771	.emit_frame_size =	772	.emit_frame_size =
772	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +	773	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
773	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +	774	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c+2−1

 #include "amdgpu_pm.h"
 #include "soc15.h"
 #include "soc15d.h"
+#include "jpeg_v2_0.h"
 #include "jpeg_v4_0_3.h"
 #include "vcn/vcn_5_0_0_offset.h"
 	.get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,
 	.get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
 	.set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
-	.parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,
+	.parse_cs = jpeg_v2_dec_ring_parse_cs,
 	.emit_frame_size =
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c+1−1

@@ -415,7 +415,7 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ · 414 unmodified lines
415	/* wait till dequeue take effects */	415	/* wait till dequeue take effects */
416	for (i = 0; i < adev->usec_timeout; i++) {	416	for (i = 0; i < adev->usec_timeout; i++) {
417	if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))	417	if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
418	break;	418	break;
419	udelay(1);	419	udelay(1);
420	}	420	}
421	if (i >= adev->usec_timeout) {	421	if (i >= adev->usec_timeout) {

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+46−18

 #include <linux/mman.h>
 #include <linux/ptrace.h>
 #include <linux/dma-buf.h>
-#include <linux/fdtable.h>
 #include <linux/processor.h>
 #include "kfd_priv.h"
 #include "kfd_device_queue_manager.h"
 }
 static int criu_get_prime_handle(struct kgd_mem *mem,
-				 int flags, u32 *shared_fd)
+				 int flags, u32 *shared_fd,
+				 struct file **file)
 {
 	struct dma_buf *dmabuf;
 	int ret;
 		return ret;
 	}
-	ret = dma_buf_fd(dmabuf, flags);
+	ret = get_unused_fd_flags(flags);
 	if (ret < 0) {
 		pr_err("dmabuf create fd failed, ret:%d\n", ret);
 		goto out_free_dmabuf;
 	}
 	*shared_fd = ret;
+	*file = dmabuf->file;
 	return 0;
 out_free_dmabuf:
 	return ret;
 }
+static void commit_files(struct file **files,
+			 struct kfd_criu_bo_bucket *bo_buckets,
+			 unsigned int count,
+			 int err)
+{
+	while (count--) {
+		struct file *file = files[count];
+		if (!file)
+			continue;
+		if (err) {
+			fput(file);
+			put_unused_fd(bo_buckets[count].dmabuf_fd);
+		} else {
+			fd_install(bo_buckets[count].dmabuf_fd, file);
+		}
+	}
+}
 static int criu_checkpoint_bos(struct kfd_process *p,
 			       uint32_t num_bos,
 			       uint8_t __user *user_bos,
 {
 	struct kfd_criu_bo_bucket *bo_buckets;
 	struct kfd_criu_bo_priv_data *bo_privs;
+	struct file **files = NULL;
 	int ret = 0, pdd_index, bo_index = 0, id;
 	void *mem;
 		goto exit;
 	}
+	files = kvzalloc(num_bos * sizeof(struct file *), GFP_KERNEL);
+	if (!files) {
+		ret = -ENOMEM;
+		goto exit;
+	}
 	for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
 		struct kfd_process_device *pdd = p->pdds[pdd_index];
 		struct amdgpu_bo *dumper_bo;
 				ret = criu_get_prime_handle(kgd_mem,
 						bo_bucket->alloc_flags &
 						KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
-						&bo_bucket->dmabuf_fd);
+						&bo_bucket->dmabuf_fd, &files[bo_index]);
 				if (ret)
 					goto exit;
 			} else {
 	*priv_offset += num_bos * sizeof(*bo_privs);
 exit:
-	while (ret && bo_index--) {
+	commit_files(files, bo_buckets, bo_index, ret);
-		if (bo_buckets[bo_index].alloc_flags
+	kvfree(files);
-		    & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
-			close_fd(bo_buckets[bo_index].dmabuf_fd);
-	}
 	kvfree(bo_buckets);
 	kvfree(bo_privs);
 	return ret;
 static int criu_restore_bo(struct kfd_process *p,
 			   struct kfd_criu_bo_bucket *bo_bucket,
-			   struct kfd_criu_bo_priv_data *bo_priv)
+			   struct kfd_criu_bo_priv_data *bo_priv,
+			   struct file **file)
 {
 	struct kfd_process_device *pdd;
 	struct kgd_mem *kgd_mem;
 	if (bo_bucket->alloc_flags
 	    & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
 		ret = criu_get_prime_handle(kgd_mem, DRM_RDWR,
-					    &bo_bucket->dmabuf_fd);
+					    &bo_bucket->dmabuf_fd, file);
 		if (ret)
 			return ret;
 	} else {
 {
 	struct kfd_criu_bo_bucket *bo_buckets = NULL;
 	struct kfd_criu_bo_priv_data *bo_privs = NULL;
+	struct file **files = NULL;
 	int ret = 0;
 	uint32_t i = 0;
 	if (!bo_buckets)
 		return -ENOMEM;
+	files = kvzalloc(args->num_bos * sizeof(struct file *), GFP_KERNEL);
+	if (!files) {
+		ret = -ENOMEM;
+		goto exit;
+	}
 	ret = copy_from_user(bo_buckets, (void __user *)args->bos,
 			     args->num_bos * sizeof(*bo_buckets));
 	if (ret) {
 	/* Create and map new BOs */
 	for (; i < args->num_bos; i++) {
-		ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]);
+		ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i], &files[i]);
 		if (ret) {
 			pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);
 			goto exit;
 		ret = -EFAULT;
 exit:
-	while (ret && i--) {
+	commit_files(files, bo_buckets, i, ret);
-		if (bo_buckets[i].alloc_flags
+	kvfree(files);
-		   & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
-			close_fd(bo_buckets[i].dmabuf_fd);
-	}
 	kvfree(bo_buckets);
 	kvfree(bo_privs);
 	return ret;

drivers/gpu/drm/amd/amdkfd/kfd_crat.c+7−1

 		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
 					CRAT_CACHE_FLAGS_DATA_CACHE |
 					CRAT_CACHE_FLAGS_SIMD_CACHE);
-		pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
+		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
+		pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;
 		i++;
 	}
 	/* Scalar L1 Instruction Cache per SQC */
 					CRAT_CACHE_FLAGS_INST_CACHE |
 					CRAT_CACHE_FLAGS_SIMD_CACHE);
 		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
+		pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;
 		i++;
 	}
 	/* Scalar L1 Data Cache per SQC */
 					CRAT_CACHE_FLAGS_DATA_CACHE |
 					CRAT_CACHE_FLAGS_SIMD_CACHE);
 		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
+		pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;
 		i++;
 	}
 	/* GL1 Data Cache per SA */
 					CRAT_CACHE_FLAGS_DATA_CACHE |
 					CRAT_CACHE_FLAGS_SIMD_CACHE);
 		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
+		pcache_info[i].cache_line_size = 0;
 		i++;
 	}
 	/* L2 Data Cache per GPU (Total Tex Cache) */
 					CRAT_CACHE_FLAGS_DATA_CACHE |
 					CRAT_CACHE_FLAGS_SIMD_CACHE);
 		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
+		pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;
 		i++;
 	}
 	/* L3 Data Cache per GPU */
 					CRAT_CACHE_FLAGS_DATA_CACHE |
 					CRAT_CACHE_FLAGS_SIMD_CACHE);
 		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
+		pcache_info[i].cache_line_size = 0;
 		i++;
 	}
 	return i;

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+3−2

 		pdd->sdma_past_activity_counter += sdma_val;
 	}
-	list_del(&q->list);
-	qpd->queue_count--;
 	if (q->properties.is_active) {
 		decrement_queue_count(dqm, qpd, q);
+		q->properties.is_active = false;
 		if (!dqm->dev->kfd->shared_resources.enable_mes) {
 			retval = execute_queues_cpsch(dqm,
 						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
 			retval = remove_queue_mes(dqm, q, qpd);
 		}
 	}
+	list_del(&q->list);
+	qpd->queue_count--;
 	/*
 	 * Unconditionally decrement this counter, regardless of the queue's

drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c+32−8

@@ -167,11 +167,23 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, · 166 unmodified lines
167	case SOC15_IH_CLIENTID_SE3SH:	167	case SOC15_IH_CLIENTID_SE3SH:
168	case SOC15_IH_CLIENTID_UTCL2:	168	case SOC15_IH_CLIENTID_UTCL2:
169	block = AMDGPU_RAS_BLOCK__GFX;	169	block = AMDGPU_RAS_BLOCK__GFX;
170	if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) \|\|	170	if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
171	amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4))	171	/* driver mode-2 for gfx poison is only supported by
172	reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;	172	* pmfw 0x00557300 and onwards */
173	else	173	if (dev->adev->pm.fw_version < 0x00557300)
		174	reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
		175	else
		176	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
		177	} else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) {
		178	/* driver mode-2 for gfx poison is only supported by
		179	* pmfw 0x05550C00 and onwards */
		180	if (dev->adev->pm.fw_version < 0x05550C00)
		181	reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
		182	else
		183	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
		184	} else {
174	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;	185	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
		186	}
175	break;	187	break;
176	case SOC15_IH_CLIENTID_VMC:	188	case SOC15_IH_CLIENTID_VMC:
177	case SOC15_IH_CLIENTID_VMC1:	189	case SOC15_IH_CLIENTID_VMC1:
@@ -184,11 +196,23 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, · 6 unmodified lines
184	case SOC15_IH_CLIENTID_SDMA3:	196	case SOC15_IH_CLIENTID_SDMA3:
185	case SOC15_IH_CLIENTID_SDMA4:	197	case SOC15_IH_CLIENTID_SDMA4:
186	block = AMDGPU_RAS_BLOCK__SDMA;	198	block = AMDGPU_RAS_BLOCK__SDMA;
187	if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) \|\|	199	if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) {
188	amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4))	200	/* driver mode-2 for gfx poison is only supported by
189	reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;	201	* pmfw 0x00557300 and onwards */
190	else	202	if (dev->adev->pm.fw_version < 0x00557300)
		203	reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
		204	else
		205	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
		206	} else if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {
		207	/* driver mode-2 for gfx poison is only supported by
		208	* pmfw 0x05550C00 and onwards */
		209	if (dev->adev->pm.fw_version < 0x05550C00)
		210	reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
		211	else
		212	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
		213	} else {
191	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;	214	reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
		215	}
192	break;	216	break;
193	default:	217	default:
194	dev_warn(dev->adev->dev,	218	dev_warn(dev->adev->dev,

drivers/gpu/drm/amd/amdkfd/kfd_priv.h+6−0

 	struct task_struct		*faulting_task;
 	/* check point ts decides if page fault recovery need be dropped */
 	uint64_t			checkpoint_ts[MAX_GPU_INSTANCE];
+	/* Default granularity to use in buffer migration
+	 * and restoration of backing memory while handling
+	 * recoverable page faults
+	 */
+	uint8_t default_granularity;
 };
 /* Process data */

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c+1−0

@@ -1046,6 +1046,7 @@ exit: · 1045 unmodified lines
1046	pr_debug("Queue id %d was restored successfully\n", queue_id);	1046	pr_debug("Queue id %d was restored successfully\n", queue_id);
1047		1047
1048	kfree(q_data);	1048	kfree(q_data);
		1049	kfree(q_extra_data);
1049		1050
1050	return ret;	1051	return ret;
1051	}	1052	}

drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c+22−23

 		amdgpu_reset_get_desc(reset_context, reset_cause,
 				      sizeof(reset_cause));
-	kfd_smi_event_add(0, dev, event, "%x %s\n",
+	kfd_smi_event_add(0, dev, event, KFD_EVENT_FMT_UPDATE_GPU_RESET(
-			  dev->reset_seq_num,
+			  dev->reset_seq_num, reset_cause));
-			  reset_cause);
 }
 void kfd_smi_event_update_thermal_throttling(struct kfd_node *dev,
 					     uint64_t throttle_bitmask)
 {
-	kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, "%llx:%llx\n",
+	kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, KFD_EVENT_FMT_THERMAL_THROTTLING(
 			  throttle_bitmask,
-			  amdgpu_dpm_get_thermal_throttling_counter(dev->adev));
+			  amdgpu_dpm_get_thermal_throttling_counter(dev->adev)));
 }
 void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid)
 	if (task_info) {
 		/* Report VM faults from user applications, not retry from kernel */
 		if (task_info->pid)
-			kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, "%x:%s\n",
+			kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, KFD_EVENT_FMT_VMFAULT(
-					 task_info->pid, task_info->task_name);
+					  task_info->pid, task_info->task_name));
 		amdgpu_vm_put_task_info(task_info);
 	}
 }
 				    ktime_t ts)
 {
 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_PAGE_FAULT_START,
-			  "%lld -%d @%lx(%x) %c\n", ktime_to_ns(ts), pid,
+			  KFD_EVENT_FMT_PAGEFAULT_START(ktime_to_ns(ts), pid,
-			  address, node->id, write_fault ? 'W' : 'R');
+			  address, node->id, write_fault ? 'W' : 'R'));
 }
 void kfd_smi_event_page_fault_end(struct kfd_node *node, pid_t pid,
 				  unsigned long address, bool migration)
 {
 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_PAGE_FAULT_END,
-			  "%lld -%d @%lx(%x) %c\n", ktime_get_boottime_ns(),
+			  KFD_EVENT_FMT_PAGEFAULT_END(ktime_get_boottime_ns(),
-			  pid, address, node->id, migration ? 'M' : 'U');
+			  pid, address, node->id, migration ? 'M' : 'U'));
 }
 void kfd_smi_event_migration_start(struct kfd_node *node, pid_t pid,
 				   uint32_t trigger)
 {
 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_MIGRATE_START,
-			  "%lld -%d @%lx(%lx) %x->%x %x:%x %d\n",
+			  KFD_EVENT_FMT_MIGRATE_START(
 			  ktime_get_boottime_ns(), pid, start, end - start,
-			  from, to, prefetch_loc, preferred_loc, trigger);
+			  from, to, prefetch_loc, preferred_loc, trigger));
 }
 void kfd_smi_event_migration_end(struct kfd_node *node, pid_t pid,
 				 uint32_t from, uint32_t to, uint32_t trigger)
 {
 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_MIGRATE_END,
-			  "%lld -%d @%lx(%lx) %x->%x %d\n",
+			  KFD_EVENT_FMT_MIGRATE_END(
 			  ktime_get_boottime_ns(), pid, start, end - start,
-			  from, to, trigger);
+			  from, to, trigger));
 }
 void kfd_smi_event_queue_eviction(struct kfd_node *node, pid_t pid,
 				  uint32_t trigger)
 {
 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_QUEUE_EVICTION,
-			  "%lld -%d %x %d\n", ktime_get_boottime_ns(), pid,
+			  KFD_EVENT_FMT_QUEUE_EVICTION(ktime_get_boottime_ns(), pid,
-			  node->id, trigger);
+			  node->id, trigger));
 }
 void kfd_smi_event_queue_restore(struct kfd_node *node, pid_t pid)
 {
 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_QUEUE_RESTORE,
-			  "%lld -%d %x\n", ktime_get_boottime_ns(), pid,
+			  KFD_EVENT_FMT_QUEUE_RESTORE(ktime_get_boottime_ns(), pid,
-			  node->id);
+			  node->id, 0));
 }
 void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm)
 		kfd_smi_event_add(p->lead_thread->pid, pdd->dev,
 				  KFD_SMI_EVENT_QUEUE_RESTORE,
-				  "%lld -%d %x %c\n", ktime_get_boottime_ns(),
+				  KFD_EVENT_FMT_QUEUE_RESTORE(ktime_get_boottime_ns(),
-				  p->lead_thread->pid, pdd->dev->id, 'R');
+				  p->lead_thread->pid, pdd->dev->id, 'R'));
 	}
 	kfd_unref_process(p);
 }
 				  uint32_t trigger)
 {
 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_UNMAP_FROM_GPU,
-			  "%lld -%d @%lx(%lx) %x %d\n", ktime_get_boottime_ns(),
+			  KFD_EVENT_FMT_UNMAP_FROM_GPU(ktime_get_boottime_ns(),
-			  pid, address, last - address + 1, node->id, trigger);
+			  pid, address, last - address + 1, node->id, trigger));
 }
 int kfd_smi_event_open(struct kfd_node *dev, uint32_t *fd)

drivers/gpu/drm/amd/amdkfd/kfd_svm.c+15−7

 }
 static void
-svm_range_set_default_attributes(int32_t *location, int32_t *prefetch_loc,
+svm_range_set_default_attributes(struct svm_range_list *svms, int32_t *location,
-				 uint8_t *granularity, uint32_t *flags)
+				 int32_t *prefetch_loc, uint8_t *granularity,
+				 uint32_t *flags)
 {
 	*location = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
 	*prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED;
-	*granularity = 9;
+	*granularity = svms->default_granularity;
 	*flags =
 		KFD_IOCTL_SVM_FLAG_HOST_ACCESS | KFD_IOCTL_SVM_FLAG_COHERENT;
 }
 		bitmap_copy(prange->bitmap_access, svms->bitmap_supported,
 			    MAX_GPU_INSTANCE);
-	svm_range_set_default_attributes(&prange->preferred_loc,
+	svm_range_set_default_attributes(svms, &prange->preferred_loc,
 					 &prange->prefetch_loc,
 					 &prange->granularity, &prange->flags);
 	*is_heap_stack = vma_is_initial_heap(vma) || vma_is_initial_stack(vma);
 	start_limit = max(vma->vm_start >> PAGE_SHIFT,
-		      (unsigned long)ALIGN_DOWN(addr, 2UL << 8));
+		      (unsigned long)ALIGN_DOWN(addr, 1UL << p->svms.default_granularity));
 	end_limit = min(vma->vm_end >> PAGE_SHIFT,
-		    (unsigned long)ALIGN(addr + 1, 2UL << 8));
+		    (unsigned long)ALIGN(addr + 1, 1UL << p->svms.default_granularity));
 	/* First range that starts after the fault address */
 	node = interval_tree_iter_first(&p->svms.objects, addr + 1, ULONG_MAX);
 	if (node) {
 		if (KFD_IS_SVM_API_SUPPORTED(p->pdds[i]->dev->adev))
 			bitmap_set(svms->bitmap_supported, i, 1);
+	 /* Value of default granularity cannot exceed 0x1B, the
+	  * number of pages supported by a 4-level paging table
+	  */
+	svms->default_granularity = min_t(u8, amdgpu_svm_default_granularity, 0x1B);
+	pr_debug("Default SVM Granularity to use: %d\n", svms->default_granularity);
 	return 0;
 }
 	node = interval_tree_iter_first(&svms->objects, start, last);
 	if (!node) {
 		pr_debug("range attrs not found return default values\n");
-		svm_range_set_default_attributes(&location, &prefetch_loc,
+		svm_range_set_default_attributes(svms, &location, &prefetch_loc,
 						 &granularity, &flags_and);
 		flags_or = flags_and;
 		if (p->xnack_enabled)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+12−1

 	 * TODO: We can likely skip bandwidth validation if the only thing that
 	 * changed about the plane was it'z z-ordering.
 	 */
-	if (new_crtc_state->zpos_changed)
+	if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos)
 		return true;
 	if (drm_atomic_crtc_needs_modeset(new_crtc_state))
 			drm_dbg(dev, "Failed to determine cursor mode\n");
 			goto fail;
 		}
+		/*
+		 * If overlay cursor is needed, DC cannot go through the
+		 * native cursor update path. All enabled planes on the CRTC
+		 * need to be added for DC to not disable a plane by mistake
+		 */
+		if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) {
+			ret = drm_atomic_add_affected_planes(state, crtc);
+			if (ret)
+				goto fail;
+		}
 	}
 	/* Remove exiting planes if they are modified */

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+1−1

@@ -1325,7 +1325,7 @@ static bool is_dsc_need_re_compute( · 1324 unmodified lines
1325	if (new_crtc_state->enable && new_crtc_state->active) {	1325	if (new_crtc_state->enable && new_crtc_state->active) {
1326	if (new_crtc_state->mode_changed \|\| new_crtc_state->active_changed \|\|	1326	if (new_crtc_state->mode_changed \|\| new_crtc_state->active_changed \|\|
1327	new_crtc_state->connectors_changed) {	1327	new_crtc_state->connectors_changed) {
1328	DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompte required."	1328	DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1329	"stream 0x%p in new dc_state\n",	1329	"stream 0x%p in new dc_state\n",
1330	__func__, __LINE__, stream);	1330	__func__, __LINE__, stream);
1331	is_dsc_need_re_compute = true;	1331	is_dsc_need_re_compute = true;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c+34−45

@@ -1748,10 +1748,6 @@ void dccg35_init(struct dccg *dccg) · 1747 unmodified lines
1748	dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);	1748	dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);
1749	}	1749	}
1750		1750
1751	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
1752	for (otg_inst = 0; otg_inst < 4; otg_inst++)
1753	dccg35_set_dppclk_root_clock_gating(dccg, otg_inst, 0);
1754
1755	/*	1751	/*
1756	dccg35_enable_global_fgcg_rep(	1752	dccg35_enable_global_fgcg_rep(
1757	dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits	1753	dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits
@@ -1932,47 +1928,32 @@ static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, · 174 unmodified lines
1932	}	1928	}
1933		1929
1934	/get other front end connected to this backend/	1930	/get other front end connected to this backend/
1935	static uint8_t dccg35_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)	1931	static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)
1936	{	1932	{
1937	uint8_t num_enabled_symclk_fe = 0;	1933	uint8_t num_enabled_symclk_fe = 0;
1938	uint32_t be_clk_en = 0, fe_clk_en[5] = {0}, be_clk_sel[5] = {0};	1934	uint32_t fe_clk_en[5] = {0}, be_clk_sel[5] = {0};
1939	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);	1935	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
1940		1936
1941	switch (link_enc_inst) {	1937	REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, &fe_clk_en[0],
1942	case 0:	1938	SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]);
1943	REG_GET_3(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, &be_clk_en,	1939
1944	SYMCLKA_FE_EN, &fe_clk_en[0],	1940	REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, &fe_clk_en[1],
1945	SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]);	1941	SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]);
1946	break;	1942
1947	case 1:	1943	REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, &fe_clk_en[2],
1948	REG_GET_3(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, &be_clk_en,	1944	SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]);
1949	SYMCLKB_FE_EN, &fe_clk_en[1],	1945
1950	SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]);	1946	REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, &fe_clk_en[3],
1951	break;	1947	SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]);
1952	case 2:	1948
1953	REG_GET_3(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, &be_clk_en,	1949	REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, &fe_clk_en[4],
1954	SYMCLKC_FE_EN, &fe_clk_en[2],	1950	SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]);
1955	SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]);	1951
1956	break;	1952	uint8_t i;
1957	case 3:	1953
1958	REG_GET_3(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, &be_clk_en,	1954	for (i = 0; i < ARRAY_SIZE(fe_clk_en); i++) {
1959	SYMCLKD_FE_EN, &fe_clk_en[3],	1955	if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst)
1960	SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]);	1956	num_enabled_symclk_fe++;
1961	break;
1962	case 4:
1963	REG_GET_3(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, &be_clk_en,
1964	SYMCLKE_FE_EN, &fe_clk_en[4],
1965	SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]);
1966	break;
1967	}
1968	if (be_clk_en) {
1969	/* for DPMST, this backend could be used by multiple front end.
1970	only disable the backend if this stream_enc_ins is the last active stream enc connected to this back_end*/
1971	uint8_t i;
1972	for (i = 0; i != link_enc_inst && i < ARRAY_SIZE(fe_clk_en); i++) {
1973	if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst)
1974	num_enabled_symclk_fe++;
1975	}
1976	}	1957	}
1977	return num_enabled_symclk_fe;	1958	return num_enabled_symclk_fe;
1978	}	1959	}
@@ -2020,9 +2001,9 @@ static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst · 41 unmodified lines
2020	break;	2001	break;
2021	}	2002	}
2022		2003
2023	/check other enabled symclk fe /	2004	/check other enabled symclk fe connected to this be /
2024	num_enabled_symclk_fe = dccg35_get_other_enabled_symclk_fe(dccg, stream_enc_inst, link_enc_inst);	2005	num_enabled_symclk_fe = dccg35_get_number_enabled_symclk_fe_connected_to_be(dccg, link_enc_inst);
2025	/*only turn off backend clk if other front end attachecd to this backend are all off,	2006	/*only turn off backend clk if other front end attached to this backend are all off,
2026	for mst, only turn off the backend if this is the last front end*/	2007	for mst, only turn off the backend if this is the last front end*/
2027	if (num_enabled_symclk_fe == 0) {	2008	if (num_enabled_symclk_fe == 0) {
2028	switch (link_enc_inst) {	2009	switch (link_enc_inst) {
@@ -2351,6 +2332,14 @@ static void dccg35_disable_symclk_se_cb( · 322 unmodified lines
2351	/* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock once PHY is turned off */	2332	/* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock once PHY is turned off */
2352	}	2333	}
2353		2334
		2335	void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)
		2336	{
		2337
		2338	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {
		2339	dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating);
		2340	}
		2341	}
		2342
2354	static const struct dccg_funcs dccg35_funcs_new = {	2343	static const struct dccg_funcs dccg35_funcs_new = {
2355	.update_dpp_dto = dccg35_update_dpp_dto_cb,	2344	.update_dpp_dto = dccg35_update_dpp_dto_cb,
2356	.dpp_root_clock_control = dccg35_dpp_root_clock_control_cb,	2345	.dpp_root_clock_control = dccg35_dpp_root_clock_control_cb,
@@ -2411,7 +2400,7 @@ static const struct dccg_funcs dccg35_funcs = { · 54 unmodified lines
2411	.enable_symclk_se = dccg35_enable_symclk_se,	2400	.enable_symclk_se = dccg35_enable_symclk_se,
2412	.disable_symclk_se = dccg35_disable_symclk_se,	2401	.disable_symclk_se = dccg35_disable_symclk_se,
2413	.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,	2402	.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,
2414		2403	.dccg_root_gate_disable_control = dccg35_root_gate_disable_control,
2415	};	2404	};
2416		2405
2417	struct dccg *dccg35_create(	2406	struct dccg *dccg35_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h+1−0

@@ -241,6 +241,7 @@ struct dccg *dccg35_create( · 240 unmodified lines
241	void dccg35_init(struct dccg *dccg);	241	void dccg35_init(struct dccg *dccg);
242		242
243	void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);	243	void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);
		244	void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);
244		245
245		246
246	#endif //__DCN35_DCCG_H__	247	#endif //__DCN35_DCCG_H__

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c+2−0

  *
  * @dpp_base: High level DPP struct
  * @scl_data: scalaer_data info
+ * @program_isharp_1dlut: flag to program isharp 1D LUT
+ * @bs_coeffs_updated: Blur and Scale Coefficients update flag
  *
  * This is the primary function to program isharp
  *

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c+12−8

 	 * as well.
 	 */
 	for (i = 0; i < num_pipes; i++) {
-		if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
+		/* dc_state_destruct() might null the stream resources, so fetch tg
-			if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
+		 * here first to avoid a race condition. The lifetime of the pointee
-				pipe_ctx[i]->stream_res.tg->funcs->set_drr(
+		 * itself (the timing_generator object) is not a problem here.
-					pipe_ctx[i]->stream_res.tg, &params);
+		 */
+		struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;
+		if ((tg != NULL) && tg->funcs) {
+			if (tg->funcs->set_drr)
+				tg->funcs->set_drr(tg, &params);
 			if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
-				if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
+				if (tg->funcs->set_static_screen_control)
-					pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
+					tg->funcs->set_static_screen_control(
-						pipe_ctx[i]->stream_res.tg,
+						tg, event_triggers, num_frames);
-						event_triggers, num_frames);
 		}
 	}
 }

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c+16−8

 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 	}
+	if (res_pool->dccg->funcs->dccg_root_gate_disable_control) {
+		for (i = 0; i < res_pool->pipe_count; i++)
+			res_pool->dccg->funcs->dccg_root_gate_disable_control(res_pool->dccg, i, 0);
+	}
 	for (i = 0; i < res_pool->audio_count; i++) {
 		struct audio *audio = res_pool->audios[i];
 	params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
 	for (i = 0; i < num_pipes; i++) {
-		if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
+		/* dc_state_destruct() might null the stream resources, so fetch tg
+		 * here first to avoid a race condition. The lifetime of the pointee
+		 * itself (the timing_generator object) is not a problem here.
+		 */
+		struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;
+		if ((tg != NULL) && tg->funcs) {
 			if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) {
 				struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;
 				struct dc *dc = pipe_ctx[i]->stream->ctx->dc;
 					num_frames = 2 * (frame_rate % 60);
 				}
 			}
-			if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
+			if (tg->funcs->set_drr)
-				pipe_ctx[i]->stream_res.tg->funcs->set_drr(
+				tg->funcs->set_drr(tg, &params);
-					pipe_ctx[i]->stream_res.tg, &params);
 			if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
-				if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
+				if (tg->funcs->set_static_screen_control)
-					pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
+					tg->funcs->set_static_screen_control(
-						pipe_ctx[i]->stream_res.tg,
+						tg, event_triggers, num_frames);
-						event_triggers, num_frames);
 		}
 	}
 }

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h+1−0

@@ -213,6 +213,7 @@ struct dccg_funcs { · 212 unmodified lines
213	uint32_t otg_inst);	213	uint32_t otg_inst);
214	void (set_dto_dscclk)(struct dccg dccg, uint32_t dsc_inst);	214	void (set_dto_dscclk)(struct dccg dccg, uint32_t dsc_inst);
215	void (set_ref_dscclk)(struct dccg dccg, uint32_t dsc_inst);	215	void (set_ref_dscclk)(struct dccg dccg, uint32_t dsc_inst);
		216	void (dccg_root_gate_disable_control)(struct dccg dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);
216	};	217	};
217		218
218	#endif //__DAL_DCCG_H__	219	#endif //__DAL_DCCG_H__

drivers/gpu/drm/amd/include/atomfirmware.h+2−2

@@ -1038,7 +1038,7 @@ struct display_object_info_table_v1_4 · 1037 unmodified lines
1038	uint16_t supporteddevices;	1038	uint16_t supporteddevices;
1039	uint8_t number_of_path;	1039	uint8_t number_of_path;
1040	uint8_t reserved;	1040	uint8_t reserved;
1041	struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path	1041	struct atom_display_object_path_v2 display_path[]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1042	};	1042	};
1043		1043
1044	struct display_object_info_table_v1_5 {	1044	struct display_object_info_table_v1_5 {
@@ -1048,7 +1048,7 @@ struct display_object_info_table_v1_5 { · 3 unmodified lines
1048	uint8_t reserved;	1048	uint8_t reserved;
1049	// the real number of this included in the structure is calculated by using the	1049	// the real number of this included in the structure is calculated by using the
1050	// (whole structure size - the header size- number_of_path)/size of atom_display_object_path	1050	// (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1051	struct atom_display_object_path_v3 display_path[8];	1051	struct atom_display_object_path_v3 display_path[];
1052	};	1052	};
1053		1053
1054	/*	1054	/*

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h+10−1

@@ -439,7 +439,16 @@ enum smu_clk_type { · 438 unmodified lines
439	__SMU_DUMMY_MAP(BACO_CG), \	439	__SMU_DUMMY_MAP(BACO_CG), \
440	__SMU_DUMMY_MAP(SOC_CG), \	440	__SMU_DUMMY_MAP(SOC_CG), \
441	__SMU_DUMMY_MAP(LOW_POWER_DCNCLKS), \	441	__SMU_DUMMY_MAP(LOW_POWER_DCNCLKS), \
442	__SMU_DUMMY_MAP(WHISPER_MODE),	442	__SMU_DUMMY_MAP(WHISPER_MODE), \
		443	__SMU_DUMMY_MAP(EDC_PWRBRK), \
		444	__SMU_DUMMY_MAP(SOC_EDC_XVMIN), \
		445	__SMU_DUMMY_MAP(GFX_PSM_DIDT), \
		446	__SMU_DUMMY_MAP(APT_ALL_ENABLE), \
		447	__SMU_DUMMY_MAP(APT_SQ_THROTTLE), \
		448	__SMU_DUMMY_MAP(APT_PF_DCS), \
		449	__SMU_DUMMY_MAP(GFX_EDC_XVMIN), \
		450	__SMU_DUMMY_MAP(GFX_DIDT_XVMIN), \
		451	__SMU_DUMMY_MAP(FAN_ABNORMAL),
443		452
444	#undef __SMU_DUMMY_MAP	453	#undef __SMU_DUMMY_MAP
445	#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT	454	#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c+12−0

 	FEA_MAP(MEM_TEMP_READ),
 	FEA_MAP(ATHUB_MMHUB_PG),
 	FEA_MAP(SOC_PCC),
+	FEA_MAP(EDC_PWRBRK),
+	FEA_MAP(SOC_EDC_XVMIN),
+	FEA_MAP(GFX_PSM_DIDT),
+	FEA_MAP(APT_ALL_ENABLE),
+	FEA_MAP(APT_SQ_THROTTLE),
+	FEA_MAP(APT_PF_DCS),
+	FEA_MAP(GFX_EDC_XVMIN),
+	FEA_MAP(GFX_DIDT_XVMIN),
+	FEA_MAP(FAN_ABNORMAL),
 	[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 	[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 	[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
 		pcie_table->clk_freq[pcie_table->num_of_link_levels] =
 					skutable->LclkFreq[link_level];
 		pcie_table->num_of_link_levels++;
+		if (link_level == 0)
+			link_level++;
 	}
 	/* dcefclk dpm table setup */

drivers/gpu/drm/drm_prime.c+54−30

@@ -410,22 +410,30 @@ static struct dma_buf export_and_register_object(struct drm_device dev, · 409 unmodified lines
410	}	410	}
411		411
412	/**	412	/**
413	* drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers	413	* drm_gem_prime_handle_to_dmabuf - PRIME export function for GEM drivers
414	* @dev: dev to export the buffer from	414	* @dev: dev to export the buffer from
415	* @file_priv: drm file-private structure	415	* @file_priv: drm file-private structure
416	* @handle: buffer handle to export	416	* @handle: buffer handle to export
417	* @flags: flags like DRM_CLOEXEC	417	* @flags: flags like DRM_CLOEXEC
418	* @prime_fd: pointer to storage for the fd id of the create dma-buf
419	*	418	*
420	* This is the PRIME export function which must be used mandatorily by GEM	419	* This is the PRIME export function which must be used mandatorily by GEM
421	* drivers to ensure correct lifetime management of the underlying GEM object.	420	* drivers to ensure correct lifetime management of the underlying GEM object.
422	* The actual exporting from GEM object to a dma-buf is done through the	421	* The actual exporting from GEM object to a dma-buf is done through the
423	* &drm_gem_object_funcs.export callback.	422	* &drm_gem_object_funcs.export callback.
		423	*
		424	* Unlike drm_gem_prime_handle_to_fd(), it returns the struct dma_buf it
		425	* has created, without attaching it to any file descriptors. The difference
		426	* between those two is similar to that between anon_inode_getfile() and
		427	* anon_inode_getfd(); insertion into descriptor table is something you
		428	* can not revert if any cleanup is needed, so the descriptor-returning
		429	* variants should only be used when you are past the last failure exit
		430	* and the only thing left is passing the new file descriptor to userland.
		431	* When all you need is the object itself or when you need to do something
		432	* else that might fail, use that one instead.
424	*/	433	*/
425	int drm_gem_prime_handle_to_fd(struct drm_device *dev,	434	struct dma_buf drm_gem_prime_handle_to_dmabuf(struct drm_device dev,
426	struct drm_file *file_priv, uint32_t handle,	435	struct drm_file *file_priv, uint32_t handle,
427	uint32_t flags,	436	uint32_t flags)
428	int *prime_fd)
429	{	437	{
430	struct drm_gem_object *obj;	438	struct drm_gem_object *obj;
431	int ret = 0;	439	int ret = 0;
@@ -434,14 +442,14 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev, · 2 unmodified lines
434	mutex_lock(&file_priv->prime.lock);	442	mutex_lock(&file_priv->prime.lock);
435	obj = drm_gem_object_lookup(file_priv, handle);	443	obj = drm_gem_object_lookup(file_priv, handle);
436	if (!obj) {	444	if (!obj) {
437	ret = -ENOENT;	445	dmabuf = ERR_PTR(-ENOENT);
438	goto out_unlock;	446	goto out_unlock;
439	}	447	}
440		448
441	dmabuf = drm_prime_lookup_buf_by_handle(&file_priv->prime, handle);	449	dmabuf = drm_prime_lookup_buf_by_handle(&file_priv->prime, handle);
442	if (dmabuf) {	450	if (dmabuf) {
443	get_dma_buf(dmabuf);	451	get_dma_buf(dmabuf);
444	goto out_have_handle;	452	goto out;
445	}	453	}
446		454
447	mutex_lock(&dev->object_name_lock);	455	mutex_lock(&dev->object_name_lock);
@@ -463,7 +471,6 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev, · 15 unmodified lines
463	/* normally the created dma-buf takes ownership of the ref,	471	/* normally the created dma-buf takes ownership of the ref,
464	* but if that fails then drop the ref	472	* but if that fails then drop the ref
465	*/	473	*/
466	ret = PTR_ERR(dmabuf);
467	mutex_unlock(&dev->object_name_lock);	474	mutex_unlock(&dev->object_name_lock);
468	goto out;	475	goto out;
469	}	476	}
@@ -478,34 +485,51 @@ out_have_obj: · 8 unmodified lines
478	ret = drm_prime_add_buf_handle(&file_priv->prime,	485	ret = drm_prime_add_buf_handle(&file_priv->prime,
479	dmabuf, handle);	486	dmabuf, handle);
480	mutex_unlock(&dev->object_name_lock);	487	mutex_unlock(&dev->object_name_lock);
481	if (ret)	488	if (ret) {
482	goto fail_put_dmabuf;	489	dma_buf_put(dmabuf);
483		490	dmabuf = ERR_PTR(ret);
484	out_have_handle:
485	ret = dma_buf_fd(dmabuf, flags);
486	/*
487	* We must _not_ remove the buffer from the handle cache since the newly
488	* created dma buf is already linked in the global obj->dma_buf pointer,
489	* and that is invariant as long as a userspace gem handle exists.
490	* Closing the handle will clean out the cache anyway, so we don't leak.
491	*/
492	if (ret < 0) {
493	goto fail_put_dmabuf;
494	} else {
495	*prime_fd = ret;
496	ret = 0;
497	}	491	}
498
499	goto out;
500
501	fail_put_dmabuf:
502	dma_buf_put(dmabuf);
503	out:	492	out:
504	drm_gem_object_put(obj);	493	drm_gem_object_put(obj);
505	out_unlock:	494	out_unlock:
506	mutex_unlock(&file_priv->prime.lock);	495	mutex_unlock(&file_priv->prime.lock);
		496	return dmabuf;
		497	}
		498	EXPORT_SYMBOL(drm_gem_prime_handle_to_dmabuf);
507		499
508	return ret;	500	/**
		501	* drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers
		502	* @dev: dev to export the buffer from
		503	* @file_priv: drm file-private structure
		504	* @handle: buffer handle to export
		505	* @flags: flags like DRM_CLOEXEC
		506	* @prime_fd: pointer to storage for the fd id of the create dma-buf
		507	*
		508	* This is the PRIME export function which must be used mandatorily by GEM
		509	* drivers to ensure correct lifetime management of the underlying GEM object.
		510	* The actual exporting from GEM object to a dma-buf is done through the
		511	* &drm_gem_object_funcs.export callback.
		512	*/
		513	int drm_gem_prime_handle_to_fd(struct drm_device *dev,
		514	struct drm_file *file_priv, uint32_t handle,
		515	uint32_t flags,
		516	int *prime_fd)
		517	{
		518	struct dma_buf *dmabuf;
		519	int fd = get_unused_fd_flags(flags);
		520
		521	if (fd < 0)
		522	return fd;
		523
		524	dmabuf = drm_gem_prime_handle_to_dmabuf(dev, file_priv, handle, flags);
		525	if (IS_ERR(dmabuf)) {
		526	put_unused_fd(fd);
		527	return PTR_ERR(dmabuf);
		528	}
		529
		530	fd_install(fd, dmabuf->file);
		531	*prime_fd = fd;
		532	return 0;
509	}	533	}
510	EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);	534	EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
511		535

include/drm/drm_prime.h+3−0

 int drm_gem_prime_fd_to_handle(struct drm_device *dev,
 			       struct drm_file *file_priv, int prime_fd, uint32_t *handle);
+struct dma_buf *drm_gem_prime_handle_to_dmabuf(struct drm_device *dev,
+			       struct drm_file *file_priv, uint32_t handle,
+			       uint32_t flags);
 int drm_gem_prime_handle_to_fd(struct drm_device *dev,
 			       struct drm_file *file_priv, uint32_t handle, uint32_t flags,
 			       int *prime_fd);

include/uapi/linux/kfd_ioctl.h+87−13

@@ -540,26 +540,29 @@ enum kfd_smi_event { · 539 unmodified lines
540	KFD_SMI_EVENT_ALL_PROCESS = 64	540	KFD_SMI_EVENT_ALL_PROCESS = 64
541	};	541	};
542		542
		543	/* The reason of the page migration event */
543	enum KFD_MIGRATE_TRIGGERS {	544	enum KFD_MIGRATE_TRIGGERS {
544	KFD_MIGRATE_TRIGGER_PREFETCH,	545	KFD_MIGRATE_TRIGGER_PREFETCH, /* Prefetch to GPU VRAM or system memory */
545	KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU,	546	KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, /* GPU page fault recover */
546	KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU,	547	KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, /* CPU page fault recover */
547	KFD_MIGRATE_TRIGGER_TTM_EVICTION	548	KFD_MIGRATE_TRIGGER_TTM_EVICTION /* TTM eviction */
548	};	549	};
549		550
		551	/* The reason of user queue evition event */
550	enum KFD_QUEUE_EVICTION_TRIGGERS {	552	enum KFD_QUEUE_EVICTION_TRIGGERS {
551	KFD_QUEUE_EVICTION_TRIGGER_SVM,	553	KFD_QUEUE_EVICTION_TRIGGER_SVM, /* SVM buffer migration */
552	KFD_QUEUE_EVICTION_TRIGGER_USERPTR,	554	KFD_QUEUE_EVICTION_TRIGGER_USERPTR, /* userptr movement */
553	KFD_QUEUE_EVICTION_TRIGGER_TTM,	555	KFD_QUEUE_EVICTION_TRIGGER_TTM, /* TTM move buffer */
554	KFD_QUEUE_EVICTION_TRIGGER_SUSPEND,	556	KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, /* GPU suspend */
555	KFD_QUEUE_EVICTION_CRIU_CHECKPOINT,	557	KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, /* CRIU checkpoint */
556	KFD_QUEUE_EVICTION_CRIU_RESTORE	558	KFD_QUEUE_EVICTION_CRIU_RESTORE /* CRIU restore */
557	};	559	};
558		560
		561	/* The reason of unmap buffer from GPU event */
559	enum KFD_SVM_UNMAP_TRIGGERS {	562	enum KFD_SVM_UNMAP_TRIGGERS {
560	KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY,	563	KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, /* MMU notifier CPU buffer movement */
561	KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE,	564	KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE,/* MMU notifier page migration */
562	KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU	565	KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU /* Unmap to free the buffer */
563	};	566	};
564		567
565	#define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))	568	#define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
@@ -570,6 +573,77 @@ struct kfd_ioctl_smi_events_args { · 4 unmodified lines
570	__u32 anon_fd; /* from KFD */	573	__u32 anon_fd; /* from KFD */
571	};	574	};
572		575
		576	/*
		577	* SVM event tracing via SMI system management interface
		578	*
		579	* Open event file descriptor
		580	* use ioctl AMDKFD_IOC_SMI_EVENTS, pass in gpuid and return a anonymous file
		581	* descriptor to receive SMI events.
		582	* If calling with sudo permission, then file descriptor can be used to receive
		583	* SVM events from all processes, otherwise, to only receive SVM events of same
		584	* process.
		585	*
		586	* To enable the SVM event
		587	* Write event file descriptor with KFD_SMI_EVENT_MASK_FROM_INDEX(event) bitmap
		588	* mask to start record the event to the kfifo, use bitmap mask combination
		589	* for multiple events. New event mask will overwrite the previous event mask.
		590	* KFD_SMI_EVENT_MASK_FROM_INDEX(KFD_SMI_EVENT_ALL_PROCESS) bit requires sudo
		591	* permisson to receive SVM events from all process.
		592	*
		593	* To receive the event
		594	* Application can poll file descriptor to wait for the events, then read event
		595	* from the file into a buffer. Each event is one line string message, starting
		596	* with the event id, then the event specific information.
		597	*
		598	* To decode event information
		599	* The following event format string macro can be used with sscanf to decode
		600	* the specific event information.
		601	* event triggers: the reason to generate the event, defined as enum for unmap,
		602	* eviction and migrate events.
		603	* node, from, to, prefetch_loc, preferred_loc: GPU ID, or 0 for system memory.
		604	* addr: user mode address, in pages
		605	* size: in pages
		606	* pid: the process ID to generate the event
		607	* ns: timestamp in nanosecond-resolution, starts at system boot time but
		608	* stops during suspend
		609	* migrate_update: GPU page fault is recovered by 'M' for migrate, 'U' for update
		610	* rw: 'W' for write page fault, 'R' for read page fault
		611	* rescheduled: 'R' if the queue restore failed and rescheduled to try again
		612	*/
		613	#define KFD_EVENT_FMT_UPDATE_GPU_RESET(reset_seq_num, reset_cause)\
		614	"%x %s\n", (reset_seq_num), (reset_cause)
		615
		616	#define KFD_EVENT_FMT_THERMAL_THROTTLING(bitmask, counter)\
		617	"%llx:%llx\n", (bitmask), (counter)
		618
		619	#define KFD_EVENT_FMT_VMFAULT(pid, task_name)\
		620	"%x:%s\n", (pid), (task_name)
		621
		622	#define KFD_EVENT_FMT_PAGEFAULT_START(ns, pid, addr, node, rw)\
		623	"%lld -%d @%lx(%x) %c\n", (ns), (pid), (addr), (node), (rw)
		624
		625	#define KFD_EVENT_FMT_PAGEFAULT_END(ns, pid, addr, node, migrate_update)\
		626	"%lld -%d @%lx(%x) %c\n", (ns), (pid), (addr), (node), (migrate_update)
		627
		628	#define KFD_EVENT_FMT_MIGRATE_START(ns, pid, start, size, from, to, prefetch_loc,\
		629	preferred_loc, migrate_trigger)\
		630	"%lld -%d @%lx(%lx) %x->%x %x:%x %d\n", (ns), (pid), (start), (size),\
		631	(from), (to), (prefetch_loc), (preferred_loc), (migrate_trigger)
		632
		633	#define KFD_EVENT_FMT_MIGRATE_END(ns, pid, start, size, from, to, migrate_trigger)\
		634	"%lld -%d @%lx(%lx) %x->%x %d\n", (ns), (pid), (start), (size),\
		635	(from), (to), (migrate_trigger)
		636
		637	#define KFD_EVENT_FMT_QUEUE_EVICTION(ns, pid, node, evict_trigger)\
		638	"%lld -%d %x %d\n", (ns), (pid), (node), (evict_trigger)
		639
		640	#define KFD_EVENT_FMT_QUEUE_RESTORE(ns, pid, node, rescheduled)\
		641	"%lld -%d %x %c\n", (ns), (pid), (node), (rescheduled)
		642
		643	#define KFD_EVENT_FMT_UNMAP_FROM_GPU(ns, pid, addr, size, node, unmap_trigger)\
		644	"%lld -%d @%lx(%lx) %x %d\n", (ns), (pid), (addr), (size),\
		645	(node), (unmap_trigger)
		646
573	/**************************************************************************************************	647	/**************************************************************************************************
574	* CRIU IOCTLs (Checkpoint Restore In Userspace)	648	* CRIU IOCTLs (Checkpoint Restore In Userspace)
575	*	649	*