These are set of two capability registers, it's pretty much given that they're registers, so reflect their purpose in the name.
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| @@ -677,15 +677,15 @@ · 676 unmodified lines | |||
| 677 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ | 677 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
| 678 | 678 | ||
| 679 | /* Virtual Channel */ | 679 | /* Virtual Channel */ |
| 680 | #define PCI_VC_PORT_REG1 4 | 680 | #define PCI_VC_PORT_CAP1 4 |
| 681 | #define PCI_VC_REG1_EVCC 0x00000007 /* extended VC count */ | 681 | #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ |
| 682 | #define PCI_VC_REG1_LPEVCC 0x00000070 /* low prio extended VC count */ | 682 | #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ |
| 683 | #define PCI_VC_REG1_ARB_SIZE 0x00000c00 | 683 | #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 |
| 684 | #define PCI_VC_PORT_REG2 8 | 684 | #define PCI_VC_PORT_CAP2 8 |
| 685 | #define PCI_VC_REG2_32_PHASE 0x00000002 | 685 | #define PCI_VC_CAP2_32_PHASE 0x00000002 |
| 686 | #define PCI_VC_REG2_64_PHASE 0x00000004 | 686 | #define PCI_VC_CAP2_64_PHASE 0x00000004 |
| 687 | #define PCI_VC_REG2_128_PHASE 0x00000008 | 687 | #define PCI_VC_CAP2_128_PHASE 0x00000008 |
| 688 | #define PCI_VC_REG2_ARB_OFF 0xff000000 | 688 | #define PCI_VC_CAP2_ARB_OFF 0xff000000 |
| 689 | #define PCI_VC_PORT_CTRL 12 | 689 | #define PCI_VC_PORT_CTRL 12 |
| 690 | #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 | 690 | #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 |
| 691 | #define PCI_VC_PORT_STATUS 14 | 691 | #define PCI_VC_PORT_STATUS 14 |