Pull pci updates from Bjorn Helgaas: "Enumeration: - Use acpi_evaluate_dsm_typed() instead of open-coding _DSM evaluation to learn device characteristics (Andy Shevchenko) - Tidy multi-function header checks using new PCI_HEADER_TYPE_MASK definition (Ilpo Järvinen) - Simplify config access error checking in various drivers (Ilpo Järvinen) - Use pcie_capability_clear_word() (not pcie_capability_clear_and_set_word()) when only clearing (Ilpo Järvinen) - Add pci_get_base_class() to simplify finding devices using base class only (ignoring subclass and programming interface) (Sui Jingfeng) - Add pci_is_vga(), which includes ancient PCI_CLASS_NOT_DEFINED_VGA devices from before the Class Code was added to PCI (Sui Jingfeng) - Use pci_is_vga() for vgaarb, sysfs "boot_vga", virtio, qxl to include ancient VGA devices (Sui Jingfeng) Resource management: - Make pci_assign_unassigned_resources() non-init because sparc uses it after init (Randy Dunlap) Driver binding: - Retain .remove() and .probe() callbacks (previously __init) because sysfs may cause them to be called later (Uwe Kleine-König) - Prevent xHCI driver from claiming AMD VanGogh USB3 DRD device, so it can be claimed by dwc3 instead (Vicki Pfau) PCI device hotplug: - Add Ampere Altra Attention Indicator extension driver for acpiphp (D Scott Phillips) Power management: - Quirk VideoPropulsion Torrent QN16e with longer delay after reset (Lukas Wunner) - Prevent users from overriding drivers that say we shouldn't use D3cold (Lukas Wunner) - Avoid PME from D3hot/D3cold for AMD Rembrandt and Phoenix USB4 because wakeup interrupts from those states don't work if amd-pmc has put the platform in a hardware sleep state (Mario Limonciello) IOMMU: - Disable ATS for Intel IPU E2000 devices with invalidation message endianness erratum (Bartosz Pawlowski) Error handling: - Factor out interrupt enable/disable into helpers (Kai-Heng Feng) Peer-to-peer DMA: - Fix flexible-array usage in struct pci_p2pdma_pagemap in case we ever use pagemaps with multiple entries (Gustavo A. R. Silva) ASPM: - Revert a change that broke when drivers disabled L1 and users later enabled an L1.x substate via sysfs, and fix a similar issue when users disabled L1 via sysfs (Heiner Kallweit) Endpoint framework: - Fix double free in __pci_epc_create() (Dan Carpenter) - Use IS_ERR_OR_NULL() to simplify endpoint core (Ruan Jinjie) Cadence PCIe controller driver: - Drop unused "is_rc" member (Li Chen) Freescale Layerscape PCIe controller driver: - Enable 64-bit addressing in endpoint mode (Guanhua Gao) Intel VMD host bridge driver: - Fix multi-function header check (Ilpo Järvinen) Microsoft Hyper-V host bridge driver: - Annotate struct hv_dr_state with __counted_by (Kees Cook) NVIDIA Tegra194 PCIe controller driver: - Drop setting of LNKCAP_MLW (max link width) since dw_pcie_setup() already does this via dw_pcie_link_set_max_link_width() (Yoshihiro Shimoda) Qualcomm PCIe controller driver: - Use PCIE_SPEED2MBS_ENC() to simplify encoding of link speed (Manivannan Sadhasivam) - Add a .write_dbi2() callback so DBI2 register writes, e.g., for setting the BAR size, work correctly (Manivannan Sadhasivam) - Enable ASPM for platforms that use 1.9.0 ops, because the PCI core doesn't enable ASPM states that haven't been enabled by the firmware (Manivannan Sadhasivam) Renesas R-Car Gen4 PCIe controller driver: - Add DesignWare core support (set max link width, EDMA_UNROLL flag, .pre_init(), .deinit(), etc) for use by R-Car Gen4 driver (Yoshihiro Shimoda) - Add driver and DT schema for DesignWare-based Renesas R-Car Gen4 controller in both host and endpoint mode (Yoshihiro Shimoda) Xilinx NWL PCIe controller driver: - Update ECAM size to support 256 buses (Thippeswamy Havalige) - Stop setting bridge primary/secondary/subordinate bus numbers, since PCI core does this (Thippeswamy Havalige) Xilinx XDMA controller driver: - Add driver and DT schema for Zynq UltraScale+ MPSoCs devices with Xilinx XDMA Soft IP (Thippeswamy Havalige) Miscellaneous: - Use FIELD_GET()/FIELD_PREP() to simplify and reduce use of _SHIFT macros (Ilpo Järvinen, Bjorn Helgaas) - Remove logic_outb(), _outw(), outl() duplicate declarations (John Sanpe) - Replace unnecessary UTF-8 in Kconfig help text because menuconfig doesn't render it correctly (Liu Song)" * tag 'pci-v6.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (102 commits) PCI: qcom-ep: Add dedicated callback for writing to DBI2 registers PCI: Simplify pcie_capability_clear_and_set_word() to ..._clear_word() PCI: endpoint: Fix double free in __pci_epc_create() PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx XDMA PCIe Root Port Bridge PCI: xilinx-cpm: Move IRQ definitions to a common header PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields PCI: hotplug: Add Ampere Altra Attention Indicator extension driver PCI/AER: Factor out interrupt toggling into helpers PCI: acpiphp: Allow built-in drivers for Attention Indicators PCI/portdrv: Use FIELD_GET() PCI/VC: Use FIELD_GET() PCI/PTM: Use FIELD_GET() PCI/PME: Use FIELD_GET() PCI/ATS: Use FIELD_GET() PCI/ATS: Show PASID Capability register width in bitmasks PCI/ASPM: Fix L1 substate handling in aspm_attr_store_common() ...
Showing the changes to include/uapi/linux (1 of 88 files). Show all
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| @@ -80,6 +80,7 @@ · 79 unmodified lines | |||
| 80 | #define PCI_HEADER_TYPE_NORMAL 0 | 80 | #define PCI_HEADER_TYPE_NORMAL 0 |
| 81 | #define PCI_HEADER_TYPE_BRIDGE 1 | 81 | #define PCI_HEADER_TYPE_BRIDGE 1 |
| 82 | #define PCI_HEADER_TYPE_CARDBUS 2 | 82 | #define PCI_HEADER_TYPE_CARDBUS 2 |
| 83 | #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */ | ||
| 83 | 84 | ||
| 84 | #define PCI_BIST 0x0f /* 8 bits */ | 85 | #define PCI_BIST 0x0f /* 8 bits */ |
| 85 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ | 86 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
| @@ -637,6 +638,7 @@ · 551 unmodified lines | |||
| 637 | #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ | 638 | #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ |
| 638 | #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ | 639 | #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ |
| 639 | #define PCI_EXP_RTSTA 0x20 /* Root Status */ | 640 | #define PCI_EXP_RTSTA 0x20 /* Root Status */ |
| 641 | #define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */ | ||
| 640 | #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ | 642 | #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ |
| 641 | #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ | 643 | #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ |
| 642 | /* | 644 | /* |
| @@ -930,12 +932,13 @@ · 287 unmodified lines | |||
| 930 | 932 | ||
| 931 | /* Process Address Space ID */ | 933 | /* Process Address Space ID */ |
| 932 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ | 934 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ |
| 933 | #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ | 935 | #define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ |
| 934 | #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ | 936 | #define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ |
| 937 | #define PCI_PASID_CAP_WIDTH 0x1f00 | ||
| 935 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ | 938 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ |
| 936 | #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ | 939 | #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ |
| 937 | #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ | 940 | #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ |
| 938 | #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ | 941 | #define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ |
| 939 | #define PCI_EXT_CAP_PASID_SIZEOF 8 | 942 | #define PCI_EXT_CAP_PASID_SIZEOF 8 |
| 940 | 943 | ||
| 941 | /* Single Root I/O Virtualization */ | 944 | /* Single Root I/O Virtualization */ |
| @@ -975,6 +978,8 @@ · 33 unmodified lines | |||
| 975 | #define PCI_LTR_VALUE_MASK 0x000003ff | 978 | #define PCI_LTR_VALUE_MASK 0x000003ff |
| 976 | #define PCI_LTR_SCALE_MASK 0x00001c00 | 979 | #define PCI_LTR_SCALE_MASK 0x00001c00 |
| 977 | #define PCI_LTR_SCALE_SHIFT 10 | 980 | #define PCI_LTR_SCALE_SHIFT 10 |
| 981 | #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */ | ||
| 982 | #define PCI_LTR_NOSNOOP_SCALE 0x1c000000 /* Scale for Max Value */ | ||
| 978 | #define PCI_EXT_CAP_LTR_SIZEOF 8 | 983 | #define PCI_EXT_CAP_LTR_SIZEOF 8 |
| 979 | 984 | ||
| 980 | /* Access Control Service */ | 985 | /* Access Control Service */ |
| @@ -1042,9 +1047,16 @@ · 61 unmodified lines | |||
| 1042 | #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ | 1047 | #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ |
| 1043 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ | 1048 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ |
| 1044 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ | 1049 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ |
| 1050 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR 0x0000 /* Uncorrectable error */ | ||
| 1051 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE 0x0002 /* Rcvd ERR_NONFATAL */ | ||
| 1052 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE 0x0004 /* Rcvd ERR_FATAL */ | ||
| 1053 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */ | ||
| 1045 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ | 1054 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ |
| 1046 | #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ | 1055 | #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ |
| 1047 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ | 1056 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ |
| 1057 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO 0x0000 /* RP PIO error */ | ||
| 1058 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER 0x0020 /* DPC SW Trigger bit */ | ||
| 1059 | #define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */ | ||
| 1048 | 1060 | ||
| 1049 | #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ | 1061 | #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ |
| 1050 | 1062 | ||
| @@ -1088,6 +1100,8 @@ · 37 unmodified lines | |||
| 1088 | #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ | 1100 | #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ |
| 1089 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ | 1101 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ |
| 1090 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ | 1102 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ |
| 1103 | #define PCI_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */ | ||
| 1104 | #define PCI_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */ | ||
| 1091 | 1105 | ||
| 1092 | /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ | 1106 | /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ |
| 1093 | #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ | 1107 | #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ |