Last batch of drm/i915 features for v4.15: - transparent huge pages support (Matthew) - uapi: I915_PARAM_HAS_SCHEDULER into a capability bitmask (Chris) - execlists: preemption (Chris) - scheduler: user defined priorities (Chris) - execlists optimization (Michał) - plenty of display fixes (Imre) - has_ipc fix (Rodrigo) - platform features definition refactoring (Rodrigo) - legacy cursor update fix (Maarten) - fix vblank waits for cursor updates (Maarten) - reprogram dmc firmware on resume, dmc state fix (Imre) - remove use_mmio_flip module parameter (Maarten) - wa fixes (Oscar) - huc/guc firmware refacoring (Sagar, Michal) - push encoder specific code to encoder hooks (Jani) - DP MST fixes (Dhinakaran) - eDP power sequencing fixes (Manasi) - selftest updates (Chris, Matthew) - mmu notifier cpu hotplug deadlock fix (Daniel) - more VBT parser refactoring (Jani) - max pipe refactoring (Mika Kahola) - rc6/rps refactoring and separation (Sagar) - userptr lockdep fix (Chris) - tracepoint fixes and defunct tracepoint removal (Chris) - use rcu instead of abusing stop_machine (Daniel) - plenty of other fixes all around (Everyone) * tag 'drm-intel-next-2017-10-12' of git://anongit.freedesktop.org/drm/drm-intel: (145 commits) drm/i915: Update DRIVER_DATE to 20171012 drm/i915: Simplify intel_sanitize_enable_ppgtt drm/i915/userptr: Drop struct_mutex before cleanup drm/i915/dp: limit sink rates based on rate drm/i915/dp: centralize max source rate conditions more drm/i915: Allow PCH platforms fall back to BIOS LVDS mode drm/i915: Reuse normal state readout for LVDS/DVO fixed mode drm/i915: Use rcu instead of stop_machine in set_wedged drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup drm/i915: Create generic functions to control RC6, RPS drm/i915: Create generic function to setup LLC ring frequency table drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "gt_pm" drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock drm/i915: Name i915_runtime_pm structure in dev_priv as "runtime_pm" drm/i915: Separate RPS and RC6 handling for CHV drm/i915: Separate RPS and RC6 handling for VLV drm/i915: Separate RPS and RC6 handling for BDW drm/i915: Remove superfluous IS_BDW checks and non-BDW changes from gen8_enable_rps drm/i915: Separate RPS and RC6 handling for gen6+ ...
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| @@ -397,10 +397,20 @@ typedef struct drm_i915_irq_wait { · 396 unmodified lines | |||
| 397 | #define I915_PARAM_MIN_EU_IN_POOL 39 | 397 | #define I915_PARAM_MIN_EU_IN_POOL 39 |
| 398 | #define I915_PARAM_MMAP_GTT_VERSION 40 | 398 | #define I915_PARAM_MMAP_GTT_VERSION 40 |
| 399 | 399 | ||
| 400 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution | 400 | /* |
| 401 | * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution | ||
| 401 | * priorities and the driver will attempt to execute batches in priority order. | 402 | * priorities and the driver will attempt to execute batches in priority order. |
| 403 | * The param returns a capability bitmask, nonzero implies that the scheduler | ||
| 404 | * is enabled, with different features present according to the mask. | ||
| 405 | * | ||
| 406 | * The initial priority for each batch is supplied by the context and is | ||
| 407 | * controlled via I915_CONTEXT_PARAM_PRIORITY. | ||
| 402 | */ | 408 | */ |
| 403 | #define I915_PARAM_HAS_SCHEDULER 41 | 409 | #define I915_PARAM_HAS_SCHEDULER 41 |
| 410 | #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) | ||
| 411 | #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) | ||
| 412 | #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) | ||
| 413 | |||
| 404 | #define I915_PARAM_HUC_STATUS 42 | 414 | #define I915_PARAM_HUC_STATUS 42 |
| 405 | 415 | ||
| 406 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of | 416 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of |
| @@ -1308,7 +1318,7 @@ struct drm_i915_reg_read { · 901 unmodified lines | |||
| 1308 | * be specified | 1318 | * be specified |
| 1309 | */ | 1319 | */ |
| 1310 | __u64 offset; | 1320 | __u64 offset; |
| 1311 | #define I915_REG_READ_8B_WA BIT(0) | 1321 | #define I915_REG_READ_8B_WA (1ul << 0) |
| 1312 | 1322 | ||
| 1313 | __u64 val; /* Return value */ | 1323 | __u64 val; /* Return value */ |
| 1314 | }; | 1324 | }; |
| @@ -1360,6 +1370,10 @@ struct drm_i915_gem_context_param { · 45 unmodified lines | |||
| 1360 | #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 | 1370 | #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 |
| 1361 | #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 | 1371 | #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 |
| 1362 | #define I915_CONTEXT_PARAM_BANNABLE 0x5 | 1372 | #define I915_CONTEXT_PARAM_BANNABLE 0x5 |
| 1373 | #define I915_CONTEXT_PARAM_PRIORITY 0x6 | ||
| 1374 | #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ | ||
| 1375 | #define I915_CONTEXT_DEFAULT_PRIORITY 0 | ||
| 1376 | #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ | ||
| 1363 | __u64 value; | 1377 | __u64 value; |
| 1364 | }; | 1378 | }; |
| 1365 | 1379 | ||