History

habanalabs: expose ASIC specific PLL index

Currently the user cannot interpret the PLL information based on index as its exposed as an integer. This commit exposes ASIC specific PLL indexes and maps it to a generic FW compatible index.

Bharat Jauhari committed 5 years ago

Commit 285c0fa1 parent a48b0878 files · +127 −114Browse files

Unified · Split

8 files
  1. drivers/misc/habanalabs/common/firmware_if.c +20 −14
  2. drivers/misc/habanalabs/common/habanalabs.h +8 −8
  3. drivers/misc/habanalabs/common/sysfs.c +2 −2
  4. drivers/misc/habanalabs/gaudi/gaudi.c +20 −35
  5. drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c +6 −6
  6. drivers/misc/habanalabs/goya/goya.c +18 −29
  7. drivers/misc/habanalabs/goya/goya_hwmgr.c +20 −20
  8. include/uapi/misc/habanalabs.h +33 −0
drivers/misc/habanalabs/common/firmware_if.c+20−14
@@ -661,18 +661,13 @@ int hl_fw_cpucp_total_energy_get(struct hl_device *hdev, u64 *total_energy) · 660 unmodified lines
661 return rc;661 return rc;
662}662}
663 663
664int get_used_pll_index(struct hl_device *hdev, enum pll_index input_pll_index,664int get_used_pll_index(struct hl_device *hdev, u32 input_pll_index,
665 enum pll_index *pll_index)665 enum pll_index *pll_index)
666{666{
667 struct asic_fixed_properties *prop = &hdev->asic_prop;667 struct asic_fixed_properties *prop = &hdev->asic_prop;
668 u8 pll_byte, pll_bit_off;668 u8 pll_byte, pll_bit_off;
669 bool dynamic_pll;669 bool dynamic_pll;
670 670 int fw_pll_idx;
671 if (input_pll_index >= PLL_MAX) {
672 dev_err(hdev->dev, "PLL index %d is out of range\n",
673 input_pll_index);
674 return -EINVAL;
675 }
676 671
677 dynamic_pll = prop->fw_security_status_valid &&672 dynamic_pll = prop->fw_security_status_valid &&
678 (prop->fw_app_security_map & CPU_BOOT_DEV_STS0_DYN_PLL_EN);673 (prop->fw_app_security_map & CPU_BOOT_DEV_STS0_DYN_PLL_EN);
@@ -680,28 +675,39 @@ int get_used_pll_index(struct hl_device *hdev, enum pll_index input_pll_index, · 1 unmodified line
680 if (!dynamic_pll) {675 if (!dynamic_pll) {
681 /*676 /*
682 * in case we are working with legacy FW (each asic has unique677 * in case we are working with legacy FW (each asic has unique
683 * PLL numbering) extract the legacy numbering678 * PLL numbering) use the driver based index as they are
679 * aligned with fw legacy numbering
684 */680 */
685 *pll_index = hdev->legacy_pll_map[input_pll_index];681 *pll_index = input_pll_index;
686 return 0;682 return 0;
687 }683 }
688 684
685 /* retrieve a FW compatible PLL index based on
686 * ASIC specific user request
687 */
688 fw_pll_idx = hdev->asic_funcs->map_pll_idx_to_fw_idx(input_pll_index);
689 if (fw_pll_idx < 0) {
690 dev_err(hdev->dev, "Invalid PLL index (%u) error %d\n",
691 input_pll_index, fw_pll_idx);
692 return -EINVAL;
693 }
694
689 /* PLL map is a u8 array */695 /* PLL map is a u8 array */
690 pll_byte = prop->cpucp_info.pll_map[input_pll_index >> 3];696 pll_byte = prop->cpucp_info.pll_map[fw_pll_idx >> 3];
691 pll_bit_off = input_pll_index & 0x7;697 pll_bit_off = fw_pll_idx & 0x7;
692 698
693 if (!(pll_byte & BIT(pll_bit_off))) {699 if (!(pll_byte & BIT(pll_bit_off))) {
694 dev_err(hdev->dev, "PLL index %d is not supported\n",700 dev_err(hdev->dev, "PLL index %d is not supported\n",
695 input_pll_index);701 fw_pll_idx);
696 return -EINVAL;702 return -EINVAL;
697 }703 }
698 704
699 *pll_index = input_pll_index;705 *pll_index = fw_pll_idx;
700 706
701 return 0;707 return 0;
702}708}
703 709
704int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, enum pll_index pll_index,710int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u32 pll_index,
705 u16 *pll_freq_arr)711 u16 *pll_freq_arr)
706{712{
707 struct cpucp_packet pkt;713 struct cpucp_packet pkt;
drivers/misc/habanalabs/common/habanalabs.h+8−8
@@ -930,6 +930,9 @@ enum div_select_defs { · 929 unmodified lines
930 * driver is ready to receive asynchronous events. This930 * driver is ready to receive asynchronous events. This
931 * function should be called during the first init and931 * function should be called during the first init and
932 * after every hard-reset of the device932 * after every hard-reset of the device
933 * @get_msi_info: Retrieve asic-specific MSI ID of the f/w async event
934 * @map_pll_idx_to_fw_idx: convert driver specific per asic PLL index to
935 * generic f/w compatible PLL Indexes
933 */936 */
934struct hl_asic_funcs {937struct hl_asic_funcs {
935 int (*early_init)(struct hl_device *hdev);938 int (*early_init)(struct hl_device *hdev);
@@ -1054,6 +1057,7 @@ struct hl_asic_funcs { · 118 unmodified lines
1054 u32 block_id, u32 block_size);1057 u32 block_id, u32 block_size);
1055 void (*enable_events_from_fw)(struct hl_device *hdev);1058 void (*enable_events_from_fw)(struct hl_device *hdev);
1056 void (*get_msi_info)(u32 *table);1059 void (*get_msi_info)(u32 *table);
1060 int (*map_pll_idx_to_fw_idx)(u32 pll_idx);
1057};1061};
1058 1062
1059 1063
@@ -1950,8 +1954,6 @@ struct hl_mmu_funcs { · 890 unmodified lines
1950 * @aggregated_cs_counters: aggregated cs counters among all contexts1954 * @aggregated_cs_counters: aggregated cs counters among all contexts
1951 * @mmu_priv: device-specific MMU data.1955 * @mmu_priv: device-specific MMU data.
1952 * @mmu_func: device-related MMU functions.1956 * @mmu_func: device-related MMU functions.
1953 * @legacy_pll_map: map holding map between dynamic (common) PLL indexes and
1954 * static (asic specific) PLL indexes.
1955 * @dram_used_mem: current DRAM memory consumption.1957 * @dram_used_mem: current DRAM memory consumption.
1956 * @timeout_jiffies: device CS timeout value.1958 * @timeout_jiffies: device CS timeout value.
1957 * @max_power: the max power of the device, as configured by the sysadmin. This1959 * @max_power: the max power of the device, as configured by the sysadmin. This
@@ -2071,8 +2073,6 @@ struct hl_device { · 113 unmodified lines
2071 struct hl_mmu_priv mmu_priv;2073 struct hl_mmu_priv mmu_priv;
2072 struct hl_mmu_funcs mmu_func[MMU_NUM_PGT_LOCATIONS];2074 struct hl_mmu_funcs mmu_func[MMU_NUM_PGT_LOCATIONS];
2073 2075
2074 enum pll_index *legacy_pll_map;
2075
2076 atomic64_t dram_used_mem;2076 atomic64_t dram_used_mem;
2077 u64 timeout_jiffies;2077 u64 timeout_jiffies;
2078 u64 max_power;2078 u64 max_power;
@@ -2387,9 +2387,9 @@ int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, · 308 unmodified lines
2387 struct hl_info_pci_counters *counters);2387 struct hl_info_pci_counters *counters);
2388int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,2388int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,
2389 u64 *total_energy);2389 u64 *total_energy);
2390int get_used_pll_index(struct hl_device *hdev, enum pll_index input_pll_index,2390int get_used_pll_index(struct hl_device *hdev, u32 input_pll_index,
2391 enum pll_index *pll_index);2391 enum pll_index *pll_index);
2392int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, enum pll_index pll_index,2392int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u32 pll_index,
2393 u16 *pll_freq_arr);2393 u16 *pll_freq_arr);
2394int hl_fw_cpucp_power_get(struct hl_device *hdev, u64 *power);2394int hl_fw_cpucp_power_get(struct hl_device *hdev, u64 *power);
2395int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg,2395int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg,
@@ -2411,9 +2411,9 @@ int hl_pci_set_outbound_region(struct hl_device *hdev, · 15 unmodified lines
2411int hl_pci_init(struct hl_device *hdev);2411int hl_pci_init(struct hl_device *hdev);
2412void hl_pci_fini(struct hl_device *hdev);2412void hl_pci_fini(struct hl_device *hdev);
2413 2413
2414long hl_get_frequency(struct hl_device *hdev, enum pll_index pll_index,2414long hl_get_frequency(struct hl_device *hdev, u32 pll_index,
2415 bool curr);2415 bool curr);
2416void hl_set_frequency(struct hl_device *hdev, enum pll_index pll_index,2416void hl_set_frequency(struct hl_device *hdev, u32 pll_index,
2417 u64 freq);2417 u64 freq);
2418int hl_get_temperature(struct hl_device *hdev,2418int hl_get_temperature(struct hl_device *hdev,
2419 int sensor_index, u32 attr, long *value);2419 int sensor_index, u32 attr, long *value);
drivers/misc/habanalabs/common/sysfs.c+2−2
@@ -9,7 +9,7 @@ · 8 unmodified lines
9 9
10#include <linux/pci.h>10#include <linux/pci.h>
11 11
12long hl_get_frequency(struct hl_device *hdev, enum pll_index pll_index,12long hl_get_frequency(struct hl_device *hdev, u32 pll_index,
13 bool curr)13 bool curr)
14{14{
15 struct cpucp_packet pkt;15 struct cpucp_packet pkt;
@@ -44,7 +44,7 @@ long hl_get_frequency(struct hl_device *hdev, enum pll_index pll_index, · 28 unmodified lines
44 return (long) result;44 return (long) result;
45}45}
46 46
47void hl_set_frequency(struct hl_device *hdev, enum pll_index pll_index,47void hl_set_frequency(struct hl_device *hdev, u32 pll_index,
48 u64 freq)48 u64 freq)
49{49{
50 struct cpucp_packet pkt;50 struct cpucp_packet pkt;
drivers/misc/habanalabs/gaudi/gaudi.c+20−35
@@ -105,36 +105,6 @@ · 104 unmodified lines
105 105
106#define GAUDI_PLL_MAX 10106#define GAUDI_PLL_MAX 10
107 107
108/*
109 * this enum kept here for compatibility with old FW (in which each asic has
110 * unique PLL numbering
111 */
112enum gaudi_pll_index {
113 GAUDI_CPU_PLL = 0,
114 GAUDI_PCI_PLL,
115 GAUDI_SRAM_PLL,
116 GAUDI_HBM_PLL,
117 GAUDI_NIC_PLL,
118 GAUDI_DMA_PLL,
119 GAUDI_MESH_PLL,
120 GAUDI_MME_PLL,
121 GAUDI_TPC_PLL,
122 GAUDI_IF_PLL,
123};
124
125static enum pll_index gaudi_pll_map[PLL_MAX] = {
126 [CPU_PLL] = GAUDI_CPU_PLL,
127 [PCI_PLL] = GAUDI_PCI_PLL,
128 [SRAM_PLL] = GAUDI_SRAM_PLL,
129 [HBM_PLL] = GAUDI_HBM_PLL,
130 [NIC_PLL] = GAUDI_NIC_PLL,
131 [DMA_PLL] = GAUDI_DMA_PLL,
132 [MESH_PLL] = GAUDI_MESH_PLL,
133 [MME_PLL] = GAUDI_MME_PLL,
134 [TPC_PLL] = GAUDI_TPC_PLL,
135 [IF_PLL] = GAUDI_IF_PLL,
136};
137
138static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {108static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {
139 "gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3",109 "gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3",
140 "gaudi cq 1_0", "gaudi cq 1_1", "gaudi cq 1_2", "gaudi cq 1_3",110 "gaudi cq 1_0", "gaudi cq 1_1", "gaudi cq 1_2", "gaudi cq 1_3",
@@ -810,7 +780,7 @@ static int gaudi_fetch_psoc_frequency(struct hl_device *hdev) · 669 unmodified lines
810 freq = 0;780 freq = 0;
811 }781 }
812 } else {782 } else {
813 rc = hl_fw_cpucp_pll_info_get(hdev, CPU_PLL, pll_freq_arr);783 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GAUDI_CPU_PLL, pll_freq_arr);
814 784
815 if (rc)785 if (rc)
816 return rc;786 return rc;
@@ -1652,9 +1622,6 @@ static int gaudi_sw_init(struct hl_device *hdev) · 835 unmodified lines
1652 1622
1653 hdev->asic_specific = gaudi;1623 hdev->asic_specific = gaudi;
1654 1624
1655 /* store legacy PLL map */
1656 hdev->legacy_pll_map = gaudi_pll_map;
1657
1658 /* Create DMA pool for small allocations */1625 /* Create DMA pool for small allocations */
1659 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),1626 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
1660 &hdev->pdev->dev, GAUDI_DMA_POOL_BLK_SIZE, 8, 0);1627 &hdev->pdev->dev, GAUDI_DMA_POOL_BLK_SIZE, 8, 0);
@@ -8783,6 +8750,23 @@ static void gaudi_enable_events_from_fw(struct hl_device *hdev) · 7122 unmodified lines
8783 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER);8750 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER);
8784}8751}
8785 8752
8753static int gaudi_map_pll_idx_to_fw_idx(u32 pll_idx)
8754{
8755 switch (pll_idx) {
8756 case HL_GAUDI_CPU_PLL: return CPU_PLL;
8757 case HL_GAUDI_PCI_PLL: return PCI_PLL;
8758 case HL_GAUDI_NIC_PLL: return NIC_PLL;
8759 case HL_GAUDI_DMA_PLL: return DMA_PLL;
8760 case HL_GAUDI_MESH_PLL: return MESH_PLL;
8761 case HL_GAUDI_MME_PLL: return MME_PLL;
8762 case HL_GAUDI_TPC_PLL: return TPC_PLL;
8763 case HL_GAUDI_IF_PLL: return IF_PLL;
8764 case HL_GAUDI_SRAM_PLL: return SRAM_PLL;
8765 case HL_GAUDI_HBM_PLL: return HBM_PLL;
8766 default: return -EINVAL;
8767 }
8768}
8769
8786static const struct hl_asic_funcs gaudi_funcs = {8770static const struct hl_asic_funcs gaudi_funcs = {
8787 .early_init = gaudi_early_init,8771 .early_init = gaudi_early_init,
8788 .early_fini = gaudi_early_fini,8772 .early_fini = gaudi_early_fini,
@@ -8866,7 +8850,8 @@ static const struct hl_asic_funcs gaudi_funcs = { · 77 unmodified lines
8866 .ack_protection_bits_errors = gaudi_ack_protection_bits_errors,8850 .ack_protection_bits_errors = gaudi_ack_protection_bits_errors,
8867 .get_hw_block_id = gaudi_get_hw_block_id,8851 .get_hw_block_id = gaudi_get_hw_block_id,
8868 .hw_block_mmap = gaudi_block_mmap,8852 .hw_block_mmap = gaudi_block_mmap,
8869 .enable_events_from_fw = gaudi_enable_events_from_fw8853 .enable_events_from_fw = gaudi_enable_events_from_fw,
8854 .map_pll_idx_to_fw_idx = gaudi_map_pll_idx_to_fw_idx
8870};8855};
8871 8856
8872/**8857/**
drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c+6−6
@@ -13,7 +13,7 @@ void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq) · 12 unmodified lines
13 struct gaudi_device *gaudi = hdev->asic_specific;13 struct gaudi_device *gaudi = hdev->asic_specific;
14 14
15 if (freq == PLL_LAST)15 if (freq == PLL_LAST)
16 hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value);16 hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);
17}17}
18 18
19int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)19int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)
@@ -23,7 +23,7 @@ int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) · 3 unmodified lines
23 if (!hl_device_operational(hdev, NULL))23 if (!hl_device_operational(hdev, NULL))
24 return -ENODEV;24 return -ENODEV;
25 25
26 value = hl_get_frequency(hdev, MME_PLL, false);26 value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);
27 27
28 if (value < 0) {28 if (value < 0) {
29 dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",29 dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",
@@ -33,7 +33,7 @@ int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) · 3 unmodified lines
33 33
34 *max_clk = (value / 1000 / 1000);34 *max_clk = (value / 1000 / 1000);
35 35
36 value = hl_get_frequency(hdev, MME_PLL, true);36 value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);
37 37
38 if (value < 0) {38 if (value < 0) {
39 dev_err(hdev->dev,39 dev_err(hdev->dev,
@@ -57,7 +57,7 @@ static ssize_t clk_max_freq_mhz_show(struct device *dev, · 17 unmodified lines
57 if (!hl_device_operational(hdev, NULL))57 if (!hl_device_operational(hdev, NULL))
58 return -ENODEV;58 return -ENODEV;
59 59
60 value = hl_get_frequency(hdev, MME_PLL, false);60 value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);
61 61
62 gaudi->max_freq_value = value;62 gaudi->max_freq_value = value;
63 63
@@ -85,7 +85,7 @@ static ssize_t clk_max_freq_mhz_store(struct device *dev, · 21 unmodified lines
85 85
86 gaudi->max_freq_value = value * 1000 * 1000;86 gaudi->max_freq_value = value * 1000 * 1000;
87 87
88 hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value);88 hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);
89 89
90fail:90fail:
91 return count;91 return count;
@@ -100,7 +100,7 @@ static ssize_t clk_cur_freq_mhz_show(struct device *dev, · 8 unmodified lines
100 if (!hl_device_operational(hdev, NULL))100 if (!hl_device_operational(hdev, NULL))
101 return -ENODEV;101 return -ENODEV;
102 102
103 value = hl_get_frequency(hdev, MME_PLL, true);103 value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);
104 104
105 return sprintf(buf, "%lu\n", (value / 1000 / 1000));105 return sprintf(buf, "%lu\n", (value / 1000 / 1000));
106}106}
drivers/misc/habanalabs/goya/goya.c+18−29
@@ -118,30 +118,6 @@ · 117 unmodified lines
118#define IS_MME_IDLE(mme_arch_sts) \118#define IS_MME_IDLE(mme_arch_sts) \
119 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)119 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
120 120
121/*
122 * this enum kept here for compatibility with old FW (in which each asic has
123 * unique PLL numbering
124 */
125enum goya_pll_index {
126 GOYA_CPU_PLL = 0,
127 GOYA_IC_PLL,
128 GOYA_MC_PLL,
129 GOYA_MME_PLL,
130 GOYA_PCI_PLL,
131 GOYA_EMMC_PLL,
132 GOYA_TPC_PLL,
133};
134
135static enum pll_index goya_pll_map[PLL_MAX] = {
136 [CPU_PLL] = GOYA_CPU_PLL,
137 [IC_PLL] = GOYA_IC_PLL,
138 [MC_PLL] = GOYA_MC_PLL,
139 [MME_PLL] = GOYA_MME_PLL,
140 [PCI_PLL] = GOYA_PCI_PLL,
141 [EMMC_PLL] = GOYA_EMMC_PLL,
142 [TPC_PLL] = GOYA_TPC_PLL,
143};
144
145static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {121static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
146 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",122 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
147 "goya cq 4", "goya cpu eq"123 "goya cq 4", "goya cpu eq"
@@ -775,7 +751,8 @@ static void goya_fetch_psoc_frequency(struct hl_device *hdev) · 627 unmodified lines
775 freq = 0;751 freq = 0;
776 }752 }
777 } else {753 } else {
778 rc = hl_fw_cpucp_pll_info_get(hdev, PCI_PLL, pll_freq_arr);754 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
755 pll_freq_arr);
779 756
780 if (rc)757 if (rc)
781 return;758 return;
@@ -897,9 +874,6 @@ static int goya_sw_init(struct hl_device *hdev) · 115 unmodified lines
897 874
898 hdev->asic_specific = goya;875 hdev->asic_specific = goya;
899 876
900 /* store legacy PLL map */
901 hdev->legacy_pll_map = goya_pll_map;
902
903 /* Create DMA pool for small allocations */877 /* Create DMA pool for small allocations */
904 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),878 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
905 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);879 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
@@ -5512,6 +5486,20 @@ static void goya_enable_events_from_fw(struct hl_device *hdev) · 4606 unmodified lines
5512 GOYA_ASYNC_EVENT_ID_INTS_REGISTER);5486 GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5513}5487}
5514 5488
5489static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
5490{
5491 switch (pll_idx) {
5492 case HL_GOYA_CPU_PLL: return CPU_PLL;
5493 case HL_GOYA_PCI_PLL: return PCI_PLL;
5494 case HL_GOYA_MME_PLL: return MME_PLL;
5495 case HL_GOYA_TPC_PLL: return TPC_PLL;
5496 case HL_GOYA_IC_PLL: return IC_PLL;
5497 case HL_GOYA_MC_PLL: return MC_PLL;
5498 case HL_GOYA_EMMC_PLL: return EMMC_PLL;
5499 default: return -EINVAL;
5500 }
5501}
5502
5515static const struct hl_asic_funcs goya_funcs = {5503static const struct hl_asic_funcs goya_funcs = {
5516 .early_init = goya_early_init,5504 .early_init = goya_early_init,
5517 .early_fini = goya_early_fini,5505 .early_fini = goya_early_fini,
@@ -5595,7 +5583,8 @@ static const struct hl_asic_funcs goya_funcs = { · 77 unmodified lines
5595 .ack_protection_bits_errors = goya_ack_protection_bits_errors,5583 .ack_protection_bits_errors = goya_ack_protection_bits_errors,
5596 .get_hw_block_id = goya_get_hw_block_id,5584 .get_hw_block_id = goya_get_hw_block_id,
5597 .hw_block_mmap = goya_block_mmap,5585 .hw_block_mmap = goya_block_mmap,
5598 .enable_events_from_fw = goya_enable_events_from_fw5586 .enable_events_from_fw = goya_enable_events_from_fw,
5587 .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx
5599};5588};
5600 5589
5601/*5590/*
drivers/misc/habanalabs/goya/goya_hwmgr.c+20−20
@@ -13,19 +13,19 @@ void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq) · 12 unmodified lines
13 13
14 switch (freq) {14 switch (freq) {
15 case PLL_HIGH:15 case PLL_HIGH:
16 hl_set_frequency(hdev, MME_PLL, hdev->high_pll);16 hl_set_frequency(hdev, HL_GOYA_MME_PLL, hdev->high_pll);
17 hl_set_frequency(hdev, TPC_PLL, hdev->high_pll);17 hl_set_frequency(hdev, HL_GOYA_TPC_PLL, hdev->high_pll);
18 hl_set_frequency(hdev, IC_PLL, hdev->high_pll);18 hl_set_frequency(hdev, HL_GOYA_IC_PLL, hdev->high_pll);
19 break;19 break;
20 case PLL_LOW:20 case PLL_LOW:
21 hl_set_frequency(hdev, MME_PLL, GOYA_PLL_FREQ_LOW);21 hl_set_frequency(hdev, HL_GOYA_MME_PLL, GOYA_PLL_FREQ_LOW);
22 hl_set_frequency(hdev, TPC_PLL, GOYA_PLL_FREQ_LOW);22 hl_set_frequency(hdev, HL_GOYA_TPC_PLL, GOYA_PLL_FREQ_LOW);
23 hl_set_frequency(hdev, IC_PLL, GOYA_PLL_FREQ_LOW);23 hl_set_frequency(hdev, HL_GOYA_IC_PLL, GOYA_PLL_FREQ_LOW);
24 break;24 break;
25 case PLL_LAST:25 case PLL_LAST:
26 hl_set_frequency(hdev, MME_PLL, goya->mme_clk);26 hl_set_frequency(hdev, HL_GOYA_MME_PLL, goya->mme_clk);
27 hl_set_frequency(hdev, TPC_PLL, goya->tpc_clk);27 hl_set_frequency(hdev, HL_GOYA_TPC_PLL, goya->tpc_clk);
28 hl_set_frequency(hdev, IC_PLL, goya->ic_clk);28 hl_set_frequency(hdev, HL_GOYA_IC_PLL, goya->ic_clk);
29 break;29 break;
30 default:30 default:
31 dev_err(hdev->dev, "unknown frequency setting\n");31 dev_err(hdev->dev, "unknown frequency setting\n");
@@ -39,7 +39,7 @@ int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) · 7 unmodified lines
39 if (!hl_device_operational(hdev, NULL))39 if (!hl_device_operational(hdev, NULL))
40 return -ENODEV;40 return -ENODEV;
41 41
42 value = hl_get_frequency(hdev, MME_PLL, false);42 value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, false);
43 43
44 if (value < 0) {44 if (value < 0) {
45 dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",45 dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",
@@ -49,7 +49,7 @@ int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) · 3 unmodified lines
49 49
50 *max_clk = (value / 1000 / 1000);50 *max_clk = (value / 1000 / 1000);
51 51
52 value = hl_get_frequency(hdev, MME_PLL, true);52 value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, true);
53 53
54 if (value < 0) {54 if (value < 0) {
55 dev_err(hdev->dev,55 dev_err(hdev->dev,
@@ -72,7 +72,7 @@ static ssize_t mme_clk_show(struct device *dev, struct device_attribute *attr, · 16 unmodified lines
72 if (!hl_device_operational(hdev, NULL))72 if (!hl_device_operational(hdev, NULL))
73 return -ENODEV;73 return -ENODEV;
74 74
75 value = hl_get_frequency(hdev, MME_PLL, false);75 value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, false);
76 76
77 if (value < 0)77 if (value < 0)
78 return value;78 return value;
@@ -105,7 +105,7 @@ static ssize_t mme_clk_store(struct device *dev, struct device_attribute *attr, · 26 unmodified lines
105 goto fail;105 goto fail;
106 }106 }
107 107
108 hl_set_frequency(hdev, MME_PLL, value);108 hl_set_frequency(hdev, HL_GOYA_MME_PLL, value);
109 goya->mme_clk = value;109 goya->mme_clk = value;
110 110
111fail:111fail:
@@ -121,7 +121,7 @@ static ssize_t tpc_clk_show(struct device *dev, struct device_attribute *attr, · 9 unmodified lines
121 if (!hl_device_operational(hdev, NULL))121 if (!hl_device_operational(hdev, NULL))
122 return -ENODEV;122 return -ENODEV;
123 123
124 value = hl_get_frequency(hdev, TPC_PLL, false);124 value = hl_get_frequency(hdev, HL_GOYA_TPC_PLL, false);
125 125
126 if (value < 0)126 if (value < 0)
127 return value;127 return value;
@@ -154,7 +154,7 @@ static ssize_t tpc_clk_store(struct device *dev, struct device_attribute *attr, · 26 unmodified lines
154 goto fail;154 goto fail;
155 }155 }
156 156
157 hl_set_frequency(hdev, TPC_PLL, value);157 hl_set_frequency(hdev, HL_GOYA_TPC_PLL, value);
158 goya->tpc_clk = value;158 goya->tpc_clk = value;
159 159
160fail:160fail:
@@ -170,7 +170,7 @@ static ssize_t ic_clk_show(struct device *dev, struct device_attribute *attr, · 9 unmodified lines
170 if (!hl_device_operational(hdev, NULL))170 if (!hl_device_operational(hdev, NULL))
171 return -ENODEV;171 return -ENODEV;
172 172
173 value = hl_get_frequency(hdev, IC_PLL, false);173 value = hl_get_frequency(hdev, HL_GOYA_IC_PLL, false);
174 174
175 if (value < 0)175 if (value < 0)
176 return value;176 return value;
@@ -203,7 +203,7 @@ static ssize_t ic_clk_store(struct device *dev, struct device_attribute *attr, · 26 unmodified lines
203 goto fail;203 goto fail;
204 }204 }
205 205
206 hl_set_frequency(hdev, IC_PLL, value);206 hl_set_frequency(hdev, HL_GOYA_IC_PLL, value);
207 goya->ic_clk = value;207 goya->ic_clk = value;
208 208
209fail:209fail:
@@ -219,7 +219,7 @@ static ssize_t mme_clk_curr_show(struct device *dev, · 9 unmodified lines
219 if (!hl_device_operational(hdev, NULL))219 if (!hl_device_operational(hdev, NULL))
220 return -ENODEV;220 return -ENODEV;
221 221
222 value = hl_get_frequency(hdev, MME_PLL, true);222 value = hl_get_frequency(hdev, HL_GOYA_MME_PLL, true);
223 223
224 if (value < 0)224 if (value < 0)
225 return value;225 return value;
@@ -236,7 +236,7 @@ static ssize_t tpc_clk_curr_show(struct device *dev, · 10 unmodified lines
236 if (!hl_device_operational(hdev, NULL))236 if (!hl_device_operational(hdev, NULL))
237 return -ENODEV;237 return -ENODEV;
238 238
239 value = hl_get_frequency(hdev, TPC_PLL, true);239 value = hl_get_frequency(hdev, HL_GOYA_TPC_PLL, true);
240 240
241 if (value < 0)241 if (value < 0)
242 return value;242 return value;
@@ -253,7 +253,7 @@ static ssize_t ic_clk_curr_show(struct device *dev, · 10 unmodified lines
253 if (!hl_device_operational(hdev, NULL))253 if (!hl_device_operational(hdev, NULL))
254 return -ENODEV;254 return -ENODEV;
255 255
256 value = hl_get_frequency(hdev, IC_PLL, true);256 value = hl_get_frequency(hdev, HL_GOYA_IC_PLL, true);
257 257
258 if (value < 0)258 if (value < 0)
259 return value;259 return value;
include/uapi/misc/habanalabs.h+33−0
@@ -239,6 +239,39 @@ enum gaudi_engine_id { · 238 unmodified lines
239 GAUDI_ENGINE_ID_SIZE239 GAUDI_ENGINE_ID_SIZE
240};240};
241 241
242/*
243 * ASIC specific PLL index
244 *
245 * Used to retrieve in frequency info of different IPs via
246 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be
247 * used as an index in struct hl_pll_frequency_info
248 */
249
250enum hl_goya_pll_index {
251 HL_GOYA_CPU_PLL = 0,
252 HL_GOYA_IC_PLL,
253 HL_GOYA_MC_PLL,
254 HL_GOYA_MME_PLL,
255 HL_GOYA_PCI_PLL,
256 HL_GOYA_EMMC_PLL,
257 HL_GOYA_TPC_PLL,
258 HL_GOYA_PLL_MAX
259};
260
261enum hl_gaudi_pll_index {
262 HL_GAUDI_CPU_PLL = 0,
263 HL_GAUDI_PCI_PLL,
264 HL_GAUDI_SRAM_PLL,
265 HL_GAUDI_HBM_PLL,
266 HL_GAUDI_NIC_PLL,
267 HL_GAUDI_DMA_PLL,
268 HL_GAUDI_MESH_PLL,
269 HL_GAUDI_MME_PLL,
270 HL_GAUDI_TPC_PLL,
271 HL_GAUDI_IF_PLL,
272 HL_GAUDI_PLL_MAX
273};
274
242enum hl_device_status {275enum hl_device_status {
243 HL_DEVICE_STATUS_OPERATIONAL,276 HL_DEVICE_STATUS_OPERATIONAL,
244 HL_DEVICE_STATUS_IN_RESET,277 HL_DEVICE_STATUS_IN_RESET,