Clean a capabilities enum to remove not-implemented bits.
Unified · Split
| @@ -51,10 +51,8 @@ u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev) · 50 unmodified lines | ||
| 51 | 51 | MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_decrypt)) |
| 52 | 52 | caps |= MLX5_ACCEL_IPSEC_CAP_ESP; |
| 53 | 53 | |
| 54 | − if (MLX5_CAP_IPSEC(mdev, ipsec_esn)) { | |
| 54 | + if (MLX5_CAP_IPSEC(mdev, ipsec_esn)) | |
| 55 | 55 | caps |= MLX5_ACCEL_IPSEC_CAP_ESN; |
| 56 | − caps |= MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN; | |
| 57 | − } | |
| 58 | 56 | |
| 59 | 57 | /* We can accommodate up to 2^24 different IPsec objects |
| 60 | 58 | * because we use up to 24 bit in flow table metadata |
| @@ -113,13 +113,10 @@ struct mlx5_accel_esp_xfrm { · 112 unmodified lines | ||
| 113 | 113 | |
| 114 | 114 | enum mlx5_accel_ipsec_cap { |
| 115 | 115 | MLX5_ACCEL_IPSEC_CAP_DEVICE = 1 << 0, |
| 116 | − MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA = 1 << 1, | |
| 117 | − MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 2, | |
| 118 | − MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 3, | |
| 119 | − MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 4, | |
| 120 | − MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER = 1 << 5, | |
| 121 | − MLX5_ACCEL_IPSEC_CAP_ESN = 1 << 6, | |
| 122 | − MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN = 1 << 7, | |
| 116 | + MLX5_ACCEL_IPSEC_CAP_ESP = 1 << 1, | |
| 117 | + MLX5_ACCEL_IPSEC_CAP_IPV6 = 1 << 2, | |
| 118 | + MLX5_ACCEL_IPSEC_CAP_LSO = 1 << 3, | |
| 119 | + MLX5_ACCEL_IPSEC_CAP_ESN = 1 << 4, | |
| 123 | 120 | }; |
| 124 | 121 | |
| 125 | 122 | #ifdef CONFIG_MLX5_EN_IPSEC |